.201039380 、 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種化合物半導體的蟲晶生長方法，應用於一執行 磊晶生長之設備，特別是指一種避免基板研磨之化合物半導體遙晶生 長方法，利用兩片基板來製作化合物半導體結構並達到避免後續研磨 製程之特性損失。 【先前技術】 化合物半導體材料，因其為直接能隙所以具有良好的發光特性， 〇 可應用於光電元件上，而此類材料的高電子遷移率也使其具有在高速 電子元件上的應用能力，尤其三五族的化合物半導體材料，目前已被 廣泛應用於發光二極體（LED)、半導體雷射與微波通訊等產品中。 在二五族的化合物半導體材料中，氮化鎵(GaN)因為可以應用於藍 光LED，所以備受矚目。通常氮化鎵化合物半導體的製作，通常會使 用晶格常數與氮化鎵相當但化學上穩定的藍寶石基板，並通常使用有 機金屬氣相磊晶法（MOCVD)在基板上成長磊晶層，以形成n型半導 體蟲晶層和p型半導體蟲晶層，接下來的製程需在蟲晶層的頂面透 過金屬蒸鍍，微影曝光和蝕刻來製作金屬電極，而後將基板磨薄並拋 〇 光，其目的在於去除磊晶在基板背面沉積的殘餘物，並可提高晶粒切 割的良率’接著在基板上鍍上另一金屬電極，形成化合物半導體元件， 而後切割為晶粒，再封裝成成品或直接應用在產品上。 其中，就用來提供化合物半導體磊晶層生長所使用的基材而言， 為了便於裝餘蟲晶生長設備的基板承載台上作絲晶生長的基底， 且根，不同的化合物半導體元件需求，必須在蟲晶之後將基板研磨至 ^既定厚度’因此’目前—般使用之基板厚度係厚達柳微米（㈣）， 往往必須磨掉許多的基板，而這樣大幅度的研磨不但浪費生產成本， 研磨過程所產生的機械應力的問題，也會使得基板的效能變差甚至 會影響到最後製成元件的品質。 3 201039380 【發明内容】 鑒於以上的問題，本發明的主要目的在於提供一種避免基板研磨 之化合物半導體磊晶生長方法，其係利用兩片薄的基板取代一片厚的 基板，來減輕基板被研磨的程度，從而可避免研磨造成的特性損失， 藉以大體上解決先前技術存在之缺失。 本發明的另一目的在於提供一種避免基板研磨之化合物半導體磊 晶生長方法，將一片基板作為可重複使用於蟲晶生長設備上的空白基 板（Dummy Wafer)，再搭配另一片基板來成長磊晶，藉此可使製程 成本降低。 因此 為達上述目的，本發明所揭露之避免基板研磨之化合物半 導體蟲晶士長方法，其步驟是先將第一基板裝載於遙晶室的基板承載 口上’接著’再將第二基板設置於第―基板上，紐進縣晶，以形 成蟲Ba層’並製得-包括有第二基板m晶層的化合物半導體結構， 在取下化合物半導魅構讀，紐承載自上_打—基板。本發 明之-具體實施例中，第-基板與第二基板的厚度各約15Q微米〜350 微米，第二基板在磊晶之後被研磨的程度將較習知基板大幅減少，可 避免研磨所造成_賴失，而第-基減可繼魏.基板承載台 上重複來製作其他化合物半導體結構，叫低元件製造的成本。 為使縣發·目的、概及其魏㈣—步的了解，兹配合圖 式洋細說明如下： 【實施方式】 之化二圖〜第1E圖，雜示本發明所提供之避免基板研磨 之化j轉體m長方法之第―具體實施例㈣程示意圖。 :實:，細晶生長的設備，可以選自一般習知晶生 ί: Li 氣減晶(M0CVD)、氣相卿pe)或分子束 t包==及諸如此類啦晶生長設絲執行。首^曰曰生長 "括“至’具有絲承魅板的基録載㈣，在此，第-基 201039380 ♦ 板20是裝載於基板承載台ι〇上，如第1A圖所示。第一基板2〇之厚 度比習知的厚基板為薄’大約為15〇微米〜35〇微米。 然後，如第1B圖所示，將第二基板3〇設置於第一基板2〇上。 此第二基板30的厚度也大約為15〇微米〜35〇微米，可選自氧化鋁 (sapphire)、碳化石夕(SiC)、氧化鋅(znO)、麟化姻(丨nP)、麟化鎵(Gap)、 石申化鎵(GaAs)或石夕（Si)基板，或是其他適合在其上以蟲晶方式成長 層狀結構的材料。前述第—基板2Q係可選擇和第二基板3G相同或不 同材質之基板；譬如，第一基板20可選自選自石英(Quartz)、石墨 ❽ (Graphite)、氮化蝴(bn>、氧化銘(sapphire)、碳化梦(sic)、氧化鋅 (ZnO)、鱗化銦(inp)、碟化鎵(Gap)、砷化鎵(GaAs)或矽（S|)基板。 ❹ 接^’如帛1C圖所示’第二基板3〇係在蟲晶生長設備内遙晶生 長’也就是在第二基板30上成長财層糾材料喊的化合物半導體 之蠢晶層40，以形成一特定結構之化合物半導體結構5〇。具體而言， 磊f曰層40可選自未摻雜的三五族化合物半導體，譬如氮化鎵，則製得 -氮化鎵化合物半導體結構5〇。而在形成蟲晶層4〇之前，可以視需 要先在第二基材30上生長諸如氮化鎵(GaN)、氣化銘（a|n)或碳 化石夕（s_c)層作為緩衝層60，之後再成長該蟲晶層4〇，以得到高品 質結曰曰’如第1D圖所不。且緩衝層6〇可以為低溫低溫緩衝層、高溫 緩衝層、雜溫_層與純緩_組合之彡祕 :低溫氮化鎵筆彻）嶋，編- 緩衝層。 夕人ί、,E圖所示’取下包含第二基板、緩衝層㈤與遙晶層4〇 。半導體結構50，而第一基板2〇係可繼續褒載於基板承載台 ’可重複使用躲晶生長設備上的空白基板（Dummy而沉）， 以’作其他化合物半導體結構，從轉低元件製造的成本。 蚀接Γ來的製程便是要將本實麵之化合物半導體結構經由金屬 曝光、研磨、切割等製程，形成化合物半導體元件。首先， 真M、、鍍方式’並配合微影、蚀刻製程，將化合物半導體結構的磊 5 201039380 晶層表面製作金屬電極，而後將第二基板背面磨薄至一定厚度，再予 以拋光形成鏡面，以去除研磨所帶來之應力層，然後在第二基板背面 製作另一金屬電極。或者，在化合物半導體結構的正、背面（分別指 磊晶層表面與第二基板背面）形成金屬電極之前，也可以先進行研磨 步驟。最後加以切割，然後封裝成成品或直接應用在產品上，其 的產品包括光電元件及高速元件。 、‘ 由於本實施例以二片薄的基板取代一般厚的基板，使得磊晶後的 化合物半導體結構具有較薄的基板厚度，基板不需要研磨太多可避 免研磨所造成的特性損失，並縮短製程時間。 雖然本發明以前述之實施例揭露如上，然其並非用以限定本發 明。在不脫離本發明之精神和範圍内，所為之更動與潤飾，均屬本發 明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之 專利範圍。 【圖式簡單說明】 第1A圖~第1E圖係本發明之避免基板研磨之化合物半導體蟲晶生長 方法之第一實施例的流程示意圖。 【主要元件符號說明】 基板承載台 2〇第一基板 3〇第二基板 40磊晶層 50化合物半導體結構 緩衝層.201039380, VI, invention description: [Technical field of invention] The present invention relates to a method for growing a crystal of a compound semiconductor, which is applied to a device for performing epitaxial growth, in particular to a compound semiconductor remote crystal for avoiding substrate polishing. The growth method utilizes two substrates to fabricate a compound semiconductor structure and achieves a characteristic loss that avoids subsequent polishing processes. [Prior Art] Compound semiconductor materials have good luminescence properties because of their direct energy gap, and 〇 can be applied to photovoltaic elements, and the high electron mobility of such materials also enables them to be applied to high-speed electronic components. In particular, compound semiconductor materials of the three or five families have been widely used in products such as light-emitting diode (LED), semiconductor laser and microwave communication. Among the compound semiconductor materials of the Group 2 and 5, gallium nitride (GaN) has attracted attention because it can be applied to blue LEDs. Generally, a gallium nitride compound semiconductor is produced by using a sapphire substrate having a lattice constant comparable to that of gallium nitride but chemically stable, and an epitaxial layer is usually grown on the substrate by an organic metal vapor phase epitaxy (MOCVD). Forming an n-type semiconductor worm layer and a p-type semiconductor worm layer, the next process requires metal evaporation, lithography exposure and etching to form a metal electrode on the top surface of the worm layer, and then the substrate is thinned and thrown Light, the purpose of which is to remove the deposit of epitaxial deposition on the back side of the substrate, and to improve the yield of die cutting. Then, another metal electrode is plated on the substrate to form a compound semiconductor device, which is then cut into crystal grains and then packaged. Into the finished product or directly applied to the product. Wherein, in order to provide a substrate for the growth of the epitaxial layer of the compound semiconductor, in order to facilitate the substrate for filament growth on the substrate carrier of the residual crystal growth apparatus, and the root, different compound semiconductor component requirements, The substrate must be ground to a predetermined thickness after the insect crystals. Therefore, the thickness of the substrate currently used is as thick as a micron ((4)). It is often necessary to wear off many substrates, and such large-scale grinding not only wastes production costs. The problem of mechanical stress generated during the grinding process can also deteriorate the performance of the substrate and even affect the quality of the final fabricated component. 3 201039380 SUMMARY OF THE INVENTION In view of the above problems, the main object of the present invention is to provide a compound semiconductor epitaxial growth method for avoiding substrate polishing, which uses two thin substrates instead of one thick substrate to reduce the substrate being polished. To the extent that the loss of properties due to grinding can be avoided, thereby largely addressing the lack of prior art. Another object of the present invention is to provide a method for epitaxial growth of a compound semiconductor which avoids substrate polishing, using a substrate as a blank substrate (Dummy Wafer) which can be repeatedly used on a crystal growth device, and then epitaxial growth with another substrate. Thereby, the process cost can be reduced. Therefore, in order to achieve the above object, the method for avoiding substrate polishing of the compound semiconductor worm crystal length disclosed in the present invention is to first load the first substrate on the substrate carrying port of the remote crystal chamber, and then set the second substrate to the second substrate. On the substrate, the Newcasting crystal is formed to form the insect Ba layer' and the compound semiconductor structure including the m-layer of the second substrate is removed, and the compound semi-conductive charm is read, and the bond is carried from the upper-trip substrate. In a specific embodiment of the present invention, the thickness of the first substrate and the second substrate are each about 15Q micrometers to 350 micrometers, and the degree of polishing of the second substrate after epitaxy is greatly reduced compared with the conventional substrate, thereby avoiding grinding. _ Lai lost, and the first-base reduction can be repeated on the substrate carrier to make other compound semiconductor structures, called the cost of low-component manufacturing. In order to understand the county, the purpose, the general and the Wei (four)-step, the following is a brief description of the following: [Embodiment] The second figure to the first one figure show the avoidance of substrate polishing provided by the present invention. The first embodiment of the method of transforming the body m length - the specific embodiment (four) process schematic. : Real:, the device for fine-grain growth can be selected from the conventional crystal growth: Li gas reduction (M0CVD), gas phase pe) or molecular beam t package == and the like. The first ^曰曰 growth" includes the "to" base recording (4), here, the base-based 201039380 ♦ the board 20 is mounted on the substrate carrying table ι, as shown in Figure 1A. The thickness of a substrate 2 is thinner than a conventional thick substrate by about 15 〇 to 35 μm. Then, as shown in Fig. 1B, the second substrate 3 is placed on the first substrate 2 。. The thickness of the second substrate 30 is also about 15 μm to 35 μm, and may be selected from the group consisting of alumina (sapphire), carbon carbide (SiC), zinc oxide (znO), lining (丨nP), and gallium nitride. (Gap), Shishenhua gallium (GaAs) or Shixi (Si) substrate, or other material suitable for growing a layered structure thereon in a serpentine manner. The aforementioned first substrate 2Q is selectable and the second substrate 3G The substrate of the same or different materials; for example, the first substrate 20 may be selected from the group consisting of quartz (Quartz), graphite ruthenium (Graphite), nitriding butterfly (bn), sapphire, carbonized dream (sic), zinc oxide ( ZnO), indium arsenide (inp), gallium gallium (Gap), gallium arsenide (GaAs) or germanium (S|) substrates. ❹ 接 ^' as shown in Figure 1C 'the second substrate 3 〇 in the worm Crystal growth The remote crystal growth in the device is the growth of the compound semiconductor semiconductor layer 40 on the second substrate 30 to form a compound semiconductor structure of a specific structure. Specifically, the germanium layer 40 An undoped tri-five compound semiconductor, such as gallium nitride, can be used to produce a gallium nitride compound semiconductor structure 5 Å. Before forming the worm layer 4 Å, the second substrate can be used as needed. A layer such as gallium nitride (GaN), gasification (a|n) or carbonized stone (s_c) is grown on the 30 as a buffer layer 60, and then the layer 4 is grown to obtain a high quality crucible' As shown in Fig. 1D, the buffer layer 6〇 can be a low temperature low temperature buffer layer, a high temperature buffer layer, a miscellaneous temperature layer and a pure slow _ combination of secrets: low temperature gallium nitride pen 嶋 嶋, braided - buffer layer.夕人ί,, E shows the removal of the second substrate, the buffer layer (5) and the tele-crystal layer 4〇. The semiconductor structure 50, and the first substrate 2 can continue to be carried on the substrate carrier' reusable A blank substrate (Dummy sinking) on the hiding device to make 'other compound semiconductor structures' The cost of manufacturing components from low-voltage components. The process of etching is to form a compound semiconductor device by metal exposure, grinding, cutting, etc., first, the first M, the plating method With the lithography and etching process, a metal electrode is formed on the surface of the compound semiconductor structure, and then the back surface of the second substrate is thinned to a certain thickness, and then polished to form a mirror surface to remove the stress layer caused by the polishing. Then, another metal electrode is formed on the back surface of the second substrate. Alternatively, the polishing step may be performed before the metal electrodes are formed on the front and back surfaces of the compound semiconductor structure (referred to as the surface of the epitaxial layer and the back surface of the second substrate, respectively). Finally, it is cut and then packaged into finished products or directly applied to the product. Its products include optoelectronic components and high-speed components. Since the present embodiment replaces a generally thick substrate with two thin substrates, the epitaxial compound semiconductor structure has a thin substrate thickness, and the substrate does not need to be ground too much to avoid the characteristic loss caused by the polishing and is shortened. Process time. Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. Modifications and modifications are within the scope of the invention as defined by the scope of the invention. Please refer to the attached patent scope for the scope of protection defined by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1E are schematic views showing the flow of a first embodiment of a method for growing a compound semiconductor crystallite which avoids substrate polishing according to the present invention. [Description of main component symbols] Substrate carrier 2 〇 first substrate 3 〇 second substrate 40 epitaxial layer 50 compound semiconductor structure buffer layer