201004512 九、發明說明： 【發明所屬之技術領域】 本發明涉及一種印刷電路板的保護處理，尤其是全面鍵 錫的處理方法。 x 【先前技術】 印刷電路板是安置電子零件最常使_裝置，而傳統 的單層印刷電路板至少具有一絕緣基板與一銅箔層，其中 该銅顯影蝴或其它加1方式形成特定電路圖 案，用以提供電路元件的電氣連接以及散熱等用途。 ,為防止銅電路圖案在空氣中氧化或受外力而刮傷，通 常在印刷電路板上會塗上一焊阻層（s〇lder Resist)，比如 防焊綠漆，該防焊綠制時具魏絕緣雜以及相當的機 械強度’因此能防止魏線路發生短路並社縣電路圖 案，而防焊綠漆裸露的區域舰焊接元制。防焊綠漆的 材料有熱烘烤硬侧環氧_(ThermQ Cured E卿)與紫 外線烘烤硬化型丙醯酸酷_v Curable㈣㈣）等。— 般的加工方法是網印、乾膜彼覆或結合二者的液態光成像 技術。 此外，銅箱電路圖案還需進一步的表面處理方法，以 產生適合焊接電子凡件的表面，因為電路圖案的銅表面對 電子元件的接腳具有不佳的焊接特性。 傳統印刷電路板的表面處理方法包括電鑛錄、電鍵金 ，無電雜化金的處理方式，在印刷電路板工業已經使用 夕年。财齡由於成本考量及無鱗料之焊接性問題， 201004512 許多新興的表面處理方式如有機保護膜（0rganic201004512 IX. Description of the Invention: [Technical Field] The present invention relates to a protection process for a printed circuit board, and more particularly to a method for processing a full-key tin. x [Prior Art] The printed circuit board is the most common device for arranging electronic components, and the conventional single-layer printed circuit board has at least one insulating substrate and a copper foil layer, wherein the copper developing butterfly or other adding a mode forms a specific circuit The pattern is used to provide electrical connection of circuit components and heat dissipation. In order to prevent the copper circuit pattern from being oxidized in the air or being scratched by external force, a solder resist layer (such as a solder resist green paint), such as a solder resist green paint, is usually applied on the printed circuit board. Wei insulation and considerable mechanical strength' can therefore prevent the short circuit of the Wei line and the circuit pattern of the county, while the anti-weld green paint is exposed to the area of the ship welding system. The material of the solder resist green paint is hot baked hard side epoxy _ (ThermQ Cured E Qing) and ultraviolet bake hardening type acrylic acid cool _v Curable (four) (four)). The general processing method is liquid-film imaging technology of screen printing, dry film coating or a combination of both. In addition, the copper box circuit pattern requires further surface treatment to produce a surface suitable for soldering electronic parts because the copper surface of the circuit pattern has poor soldering characteristics for the pins of the electronic component. The surface treatment methods of conventional printed circuit boards include electric mining, electric gold, and non-electric hybrid gold processing, which have been used in the printed circuit board industry. Due to cost considerations and weldability problems without scales, 201004512 Many emerging surface treatment methods such as organic protective film (0rganic
Solderability Preservatives，0SP)、浸鍍銀（Immersi〇nSolderability Preservatives, 0SP), immersion silver plating (Immersi〇n
Silver)、浸鍍錫（lmmerSi〇n Tin)以及純霧錫(matte tin) 等都快速發展之中，其中純霧錫是大批量半導體製造商鍍 層應用的首選。原因是，對於各種電子元件的接腳導線架 而言，霧錫製程不僅具有良好焊接特性，而且一種低成本 解決方案’不存在習用技術Sn-Ag、Sn-Bi和Sn-Cu系統中 的雙合金成份控制問題。霧錫解決方案得以廣泛應用的另 一個關鍵因素是其供應充足，此因素與上述技術密切相 關。霧錫最重要的優勢在於與舊有的含鉛焊料相容。鑒於 世界上許多無鉛政策在執行上存在延遲，這種後向兼容仍 較為重要。 浸鑛銀與浸鑛錫的技術，其製造流程相對較為簡單， 主要含銅表面的預清洗、微蝕、表面前處理、以及浸鍍等 步驟。其中浸鍍銀的鍍液以硝酸銀為主配方，焊接性良好 且焊點強度也十分可靠。但純銀表面在空氣中易產生硫化 及氧化的現象，所以需在浸鍍槽中添加有機抑制劑，來防 止表面變色的情況。此外，為避免有機銀產生遷移現象 (Silver Migration)，浸鍍液中還需添加表面潤濕劑盥 緩衝劑等。 ^ 新興的浸鍍錫技術則是以硫脲(Thiourea)為主劑，鍍 液穩定，焊錫性也較佳。不過浸鍍錫過程易造成綠漆變色 或側蝕的問題，焊接後機版墊片與焊點間快速成長之脆性 的介金屬層（IMC)，焊接性將受到影響。對於純錫電鑛層表 面易產生錫鬚（Tin Whisker)的問題，也是浸鑛錫技術的 201004512 一大隱憂。 參閱圖1，習用技術之一次鍍錫方法的印刷電路板結 翻。利用接著層12將銅猪層安置在絕緣層1〇上，接著 進行顯影_處理’讓銅騎形成具電路_的電路圖案 層3〇 ° _適當的方法，將烊阻層2G，比如防焊綠漆，塗 ，在電路圖案層30上’保護電路圖案層30，同時留下裸 路的烊接區域供後續焊接電子元侧。最後，糊適當的 鍍錫方法，將裸露的焊接區域鍍上保護性的第一錫層31❶ 該一次鍍錫方法中的錫會侵蝕焊阻層2〇與電路圖案 層30的邊緣交接區的銅而形成侵蝕區邪，如圖丨所示， 原因是該交接面的銅與錫會產生電位差，形成局部陰極區 與陽極區，使得金屬銅被氧化層銅離子，造成該部分被侵 I虫掉，進而造成印刷電路板的損壞或甚至短路。 參閱圖2，習用技彳标之二次鑛錫方法的印刷電路板結 構圖。該結構圖是被揭露於日本專利特許3〇76342的二次 鍍錫方法。該二次鍍錫方法是在電路圖案層3〇完成後，先 利用適當的鍍錫方法’將整個電路圖案層3〇上電鍍保護性 的第一錫層31，亦即第一錫層31包覆住整個電路圖案層 30，如圖2所示。接著進行焊阻層2〇的塗佈處理，覆蓋住 部分的電路圖案層30。最後進行第二次鍍錫處理，將第二 錫層33覆蓋住未被焊阻層20彼覆的區域。第一錫層31因 與電路圖案層30接觸’而會在老化或烘烤過程中讓電路圖 案層30的銅擴散到第一錫層31内，亦即第一錫層31含有 擴散而來的銅。苐·一錫層33包覆第一錫層31，所以不含銅。 該方法可以解決習用技術中焊阻層20與電路圖案層3〇的 7 201004512 邊緣交接區發生鋼被侵敍的問題。 然而，日本專利特許_342所揭示的二次鍍錫方 法，仍有可能因焊阻層在錫射溶出，而導致錫液壽命縮 紐’且受到錫液攻擊之焊阻層，可能產生產品可靠度劣化。 【發明内容】 +本發明之主要目的在提供—種印刷電路板 包括第-次鍍錫處理、第二次全面鏟錫處理以及焊阻層塗 佈處理，產生保護層並避免發生局部侵钱。 所形成的銅電路圖案上，利用第一次鍍锡處理形成= 層二該第-錫層將整個銅電路圖案包覆住而提供保護，經 氮氣烘烤’使得第-錫層轉換為界金屬共化物，而使得^ 一錫層含有從銅電路圖案擴散而來的銅。接著進行第二欠 全面鍍錫處理以形成第二錫層，該第二錫層完全包覆^ 一錫層，提供優良的焊接特性，用於焊接安置各種電子元 件。取後進行焊阻層塗佈處理，將需要絕緣保護的區域用 t 焊阻層覆蓋住’同時提供機械強度以防止外力的到傷損壞。 本發明的印刷電路板鍍錫方法’可以解決制技術中 發生局部侵蝕的問題，防止錫進一步攻擊銅，並避免錫鬚 發生。同時因全面性的化錫層可避免銅與印刷電路板中的 防焊綠漆、PI(聚乙醯胺）、Cover Layer(保護膠）、銀漿片、 接著層、補強板等異質材料交界處之局部電位差發生，進 而提高產品可靠度與使用壽命。並避免因焊阻層在錫液中 溶出，而導致錫液壽命縮短，及焊阻層表面受到錫液攻擊， 產生產品可靠度劣化之可能。 8 201004512 【實施方式】 以下配合赋及元件符麟本發明之實施方式做更詳 =的酬’俾使熟習該項技藝者在研讀本說明書後能據以 實施。 參閱圖3 ’顯示本發明印刷電路板鑛錫方法的全面鑛 錫結構圖。在本發_方法t，包括第—次鍍錫處理、第 二次全面麟處理以及焊阻層_處理，產生保護層並避 免發生局部侵餘。 首先’在絕緣層10上藉接著層12而貼附的銅落，經 適當方法而完成的電路圖案30，進行第一次鍍錫處理形成 第錫層3卜该第一錫層31將整個電路圖案3〇包覆住而 提供保護’贱氣烘烤，使得第轉換為界金屬共化 物’而含有從銅電路圖案3〇擴散而來的銅，亦即第一錫層 31 s有銅接著進行第二次全面鐘錫處理以形成全面性化 的第二錫層33 ’該第二錫層33完全包覆住第—錫層31， 提供優㈣焊接紐1於焊接安置各種電子元件。最後， 進行焊阻層塗佈處理以形成烊阻層2G，將需要絕緣保護的 區域用烊關20錢住，_提供機度雜止外力的 刮傷損壞。 該第-次鍍錫處理與第二次全面鍍錫處理可以使用浸 鍵錫方法、純義方域其它賴方法。由於第-錫層31 提供阻障的功能’防止後續的錫進—步攻擊金屬銅，同時 避免錫鬚發生。此外，全面性化的第二錫層33可避免金屬 銅與印刷電贿上的J：辑綠漆、PI(聚乙_)、c__Silver, immersion tin (lmmerSi〇n Tin) and pure matte tin are rapidly evolving, with pure matte tin being the first choice for coating applications for high volume semiconductor manufacturers. The reason is that for the lead frame of various electronic components, the matte tin process not only has good soldering characteristics, but also a low-cost solution 'there is no double in the conventional Sn-Ag, Sn-Bi and Sn-Cu systems. Alloy composition control issues. Another key factor in the widespread use of the matte tin solution is its adequate supply, which is closely related to the above technologies. The most important advantage of matte tin is its compatibility with older lead-containing solders. Given the delays in implementation of many of the world's lead-free policies, this backward compatibility is still important. The technology of immersion silver and immersion tin has a relatively simple manufacturing process, mainly including pre-cleaning, micro-etching, surface pre-treatment, and immersion plating of copper surfaces. The silver-plated plating solution is mainly composed of silver nitrate, which has good weldability and reliable solder joint strength. However, the surface of pure silver is prone to vulcanization and oxidation in the air, so it is necessary to add an organic inhibitor to the immersion plating tank to prevent discoloration of the surface. In addition, in order to avoid the migration of organic silver, a surface wetting agent, a buffer, and the like are added to the immersion bath. ^ The emerging immersion tin plating technology is based on thiourea (Thiourea), which is stable in plating solution and excellent in solderability. However, the immersion tin plating process is liable to cause discoloration or side etching of the green paint. The weldability of the fast-growing brittle metal layer (IMC) between the machine-shield gasket and the solder joint will be affected. For the problem of tin whisker (Tin Whisker) on the surface of pure tin electro-mineral layer, it is also a major concern for 201004512 of immersion tin technology. Referring to Figure 1, the printed circuit board of a conventional tin plating method is turned over. The copper layer is placed on the insulating layer 1 by means of the adhesive layer 12, followed by development_processing 'Let the copper ride to form the circuit pattern layer with the circuit_3 〇 _ _ appropriate method, the barrier layer 2G, such as solder mask The green lacquer, coated, protects the circuit pattern layer 30 on the circuit pattern layer 30 while leaving the splicing area of the bare road for subsequent soldering of the electronic element side. Finally, a suitable tin plating method is applied to coat the exposed soldering region with a protective first tin layer 31. The tin in the primary tin plating method erodes the copper of the solder resist layer 2 and the edge of the circuit pattern layer 30. The formation of the erosion zone evil, as shown in Figure ,, is due to the potential difference between the copper and tin of the interface, forming a local cathode zone and an anode zone, so that the copper is oxidized by the copper ions, causing the part to be invaded. , which in turn causes damage to the printed circuit board or even a short circuit. Referring to Figure 2, a printed circuit board structure diagram of the secondary tin-staining method of the conventional technique. This structural drawing is a secondary tin plating method disclosed in Japanese Patent No. 3,763,422. The secondary tin plating method is: after the circuit pattern layer 3 is completed, the entire circuit pattern layer 3 is first plated with a protective first tin layer 31 by using a suitable tin plating method, that is, the first tin layer 31 is packaged. The entire circuit pattern layer 30 is covered, as shown in FIG. Next, a coating process of the solder resist layer 2 is performed to cover a portion of the circuit pattern layer 30. Finally, a second tin plating treatment is performed to cover the second tin layer 33 over the region not covered by the solder resist layer 20. The first tin layer 31 is in contact with the circuit pattern layer 30, and the copper of the circuit pattern layer 30 is diffused into the first tin layer 31 during the aging or baking process, that is, the first tin layer 31 contains diffusion. copper. The bismuth-tin layer 33 covers the first tin layer 31, so it does not contain copper. The method can solve the problem that steel intrusion occurs in the edge intersection area of the 2010 20101212 solder resist layer 20 and the circuit pattern layer 3 in the conventional technology. However, the secondary tin plating method disclosed in Japanese Patent No. 342, there is still a possibility that the solder resist layer is melted in the tin, and the tin liquid life is shortened and the solder resist layer is attacked by the tin liquid, which may result in reliable products. Degree is degraded. SUMMARY OF THE INVENTION The main object of the present invention is to provide a printed circuit board comprising a first tin plating process, a second full tinning process, and a solder resist layer coating process to create a protective layer and avoid local intrusion. On the formed copper circuit pattern, the first tin plating treatment is used to form = layer 2, the first tin layer covers the entire copper circuit pattern to provide protection, and the nitrogen-baking is performed to convert the first-tin layer into a boundary metal. The eutectic is such that the tin layer contains copper diffused from the copper circuit pattern. A second under-plating treatment is then performed to form a second tin layer that completely encapsulates the tin layer, providing excellent soldering characteristics for soldering various electronic components. After the solder resist coating process is performed, the region requiring insulation protection is covered with a solder resist layer while providing mechanical strength to prevent damage to the external force. The tin plating method of the printed circuit board of the present invention can solve the problem of local erosion in the manufacturing technology, prevent tin from further attacking copper, and avoid tin whisker. At the same time, the comprehensive tin layer can avoid the boundary between copper and solder resist green paint, PI (polyacetamide), Cover Layer (protective adhesive), silver paste sheet, subsequent layer, reinforcing plate and other heterogeneous materials. The local potential difference occurs, which improves product reliability and service life. And to avoid the dissolution of the solder resist layer in the tin liquid, the tin liquid life is shortened, and the surface of the solder resist layer is attacked by the tin liquid, which may cause deterioration of product reliability. 8 201004512 [Embodiment] The following is a more detailed remuneration for the implementation of the present invention, so that those skilled in the art can implement it after studying the present specification. Referring to Figure 3', there is shown a comprehensive tin structure diagram of the tin-plating method of the printed circuit board of the present invention. In the present invention, method t, including the first tin plating treatment, the second comprehensive lining treatment, and the solder resist layer treatment, a protective layer is generated and localized invasion is avoided. First, the copper pattern attached to the insulating layer 10 by the layer 12 is applied, and the circuit pattern 30 completed by a suitable method is subjected to a first tin plating treatment to form a tin layer 3. The first tin layer 31 will be the entire circuit. The pattern 3〇 is covered to provide protection of 'helium baking, so that the first transition to the boundary metal complex' and contains copper diffused from the copper circuit pattern 3, that is, the first tin layer 31 s has copper followed by The second comprehensive treatment of the tin tin to form a comprehensive second tin layer 33 'the second tin layer 33 completely covers the first tin layer 31, providing a superior (4) solder bump 1 for soldering various electronic components. Finally, the solder resist layer coating process is performed to form the germanium resist layer 2G, and the area requiring insulation protection is used for the damage of the external force of the machine. The first tin plating treatment and the second full tin plating treatment may use a immersion tin method or a purely square method. Since the first-tin layer 31 provides a barrier function, the subsequent tin is prevented from attacking the metal copper while avoiding tin whiskers. In addition, the comprehensive second tin layer 33 can avoid metal copper and printed bribes on J: green paint, PI (poly _), c__
Layer(保護膠）、銀漿片、接著層、補強板等異質材料交界 201004512 處之局部電位差發生，。 阳蛤致錫液辱命縮短，及 攻擊’產生產品可靠度劣化之可能。 企圖播、# 4者僅翻以轉本發觀健實闕，並非 止回以對本發明做任何形式上之限制，是以，凡有在相 同之么明精神下所作有關本發明之任何修*或變更，皆仍 應包括在本發明意圖保護之範疇。 【圖式簡單說明】 圖1為顯示習用技術之一次鍍錫方法的印刷電路板結構圖。 圖2為顯示習用技術之二次鍍錫方法的印刷電路板結構圖。 圖3為顯示本發明印刷電路板鐘錫方法的全面鍍錫結構圖。 【主要元件符號說明】 10絕緣層 12接著層 20焊阻層（防焊綠漆） 30電路圖案層（銅箔） 31第一錫層 33第—錫層 35侵蝕區Layer (protective rubber), silver paste sheet, adhesive layer, reinforcing plate and other heterogeneous materials at the junction of 201004512 local potential difference occurs. Yangshuo caused the tin liquid to be shortened, and the attack 'produced the possibility of product reliability deterioration. In the case of attempting to broadcast, the #4 is only turned over to the actual situation, and it is not intended to limit the invention to any form. Therefore, any modification of the invention made under the same spirit of the present invention* Changes or modifications are intended to be included within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural view showing a printed circuit board of a conventional tin plating method of the prior art. Fig. 2 is a structural view showing a printed circuit board of a secondary tin plating method of a conventional technique. Fig. 3 is a view showing the overall tin plating structure of the tin-tin method of the printed circuit board of the present invention. [Main component symbol description] 10 insulating layer 12 adhesive layer 20 solder resist layer (solderproof green paint) 30 circuit pattern layer (copper foil) 31 first tin layer 33 first - tin layer 35 erosion zone