200913840 九、發明說明： -【發明所屬之技術領域】 -本發明係有關於一種電路板及其製法，更詳而言之， =有關於一種於電鐘導通孔之端面形成金屬連接墊以供 生連接使用，藉以縮小產品尺寸之電路板及其 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Sennconducts device)已開發出不同的 半導體裝置，要係在一封裝基板(packagesubstm= 導線架上先设置-具有積體電路之半導體元件，再將該半 導體元件電性連接在該封褒基板或導線架上，接著以膠體 進行封裝，·其中球柵陣列式（Ballgridarray，_ 如隨、腿、⑽八等，為一種先進的半導體封裝技術， 其特點在於採用-縣基板來安置且電性連接該半導體 兀件’並於該封褒基板背面植置多數個成栅狀陣列排列之 錫球（Solder ball)，使相同單位面積之半導體元件承載 件上可以容納更多輸入/輸出連接端（I/Q c◦職⑴㈤）， 以符合高度集積化(integrati〇n)之半導體晶片所需，藉 由該些錫球以電性連接外部電子裝置。 9 另為因應微處理器、晶片組、繪圖晶片等高效能晶片 之運算需要，該用以封裝之封裝基板亦需提昇其傳遞晶片 訊號、改善頻寬、控制阻抗等功能，以供高1/〇數^件 的發展；然而，為符合半導體封裝件輕薄短小、多功能、 高速度及高頻化的開發方向，半導體晶片封裝用之封^基 110380 6 200913840 板已朝向細線路及小孔徑發展；現有電路板製程從傳統 100微米之線路尺寸：包括導線寬度(Line width)及線路 .間距（Space)，已縮減至託微米，並持續朝向更小的線 精度進行研發。 制明芩閱第1 A至1Η圖，係為習知形成封裝用電路板之 衣t剖視圖，首先提供-核心板10，於該核心板1〇兩表 面刀別具有第-金屬層12a，並以雷射或機械鑽孔的方式 ,瓜成複數貫穿之貫孔（thr〇ugh_h〇le)1〇2(如第ia圖所 不接著，於該核心板1 〇之兩表面以及貫孔102中之表 成苐導電層lla(如第1B圖所示）；於該第一導 “曰la表面承錢开》成一第二金屬層12b，並於該貫孔1〇2 中开/ 成电錢導通孔（plated through-hole，PTH)120a， 且以填充材料12〇填入該電鍍導通孔12〇a中（如第1C圖 所不），接著，於該第二金屬層12b、電鍍導通孔12(^及 真充材料I20表面電鍍形成一第二導電層lib(如第1D圖 (所不），之後於該第二導電層lib表面電鍍形成一第三金 屬層12c(如第ιΕ圖所示）；之後，於該第三金屬層12仁 表，形成一阻層13，且該阻層13中形成有開口 13〇以露 出部份之第三金屬層12c表面（如第1F圖所示）；然後以 光學微影、蝕刻等方式移除該開口 13〇中之第一金屬層 2a第一導電層11a、第二金屬層12b、第二導電層lib 與第三金屬層12c以形成圖案化之線路層14，且該線路 層14具有複數金屬連接墊141，並移除該阻層13以露出 該線路層14及金屬連接墊141，且該些金屬連接墊141 110380 7 200913840 係位於該電錢導通孔12Ga之端面（如第ig圖所示）；之 後方、該核〜板1 〇及線路層〗4表面形成一線路增層結構 15 I泉路增層結構J 5係包括有介電層n疊置於兮 介電層上之線路層151，以及形成於該介電層中之導電盲 孔（conduct iVe Vla) 152 ’且部份之導電盲孔152電性連 接該線路層u之金屬連接塾141，以形成一導電盲孔152 形成於該電鍍導通孔12〇a表面之結構（Via〇npTH， V0P)，如此可無須另從電鍍導通孔處延伸出接觸墊 (P a d ) ’以供接置導雷亡3丨田 ， 線密度。出-目孔用’如此可增加内層線路之佈 之後於該線路增層結構15表面形 塾(p 一且於該線路增層結構15表面具有二= ㈣厂絕緣保護層16表面具有複 6、.表： =。該線路增層結構15之電性連接塾153(如第丨： 然而，上述之方法的缺點在於必須進行兩 於核心板1〇兩側全部表面形成該第二及第三^衣転 12b’12c’經由前述製程則會使該核心板i : 度過厚，再㈣形成線路時，因側㈣因素厂子 線距僅能達到75靖㈣，而無法形成二路 此外猎由電鐘兩次而形成第二及第三 〔、泉路， 會有線路層厚度過厚問題，而無法形成，^則 因此’如何提出—種電路板及製法，以避二構。 中，電路板兩侧全部表面刑 免白知技術 乂成一層至屬銅使電路板兩表面 110380 8 200913840 度過後’而無法形成細線路，因而不易滿足高階電 .:之細線路高密度佈線之使用需求，實已成爲目前業 界虽待克服之課題。 【發明内容】 供一 ^上述習知技術之缺點，本發明之主要目的在於提 且於兮$路板及其製法’藉以於該電路板1ί7形成細線路， =電料通孔之端部上形成金屬連接塾，以供钱刻製 成細線路之使用需求。 =達上述及其他目的，本發明提供—種電路板，係包 祜.核心板，係具有相對靡 有:目對應之兩表面、及貫穿該兩表面之 τ貝孔’该核心板係為—雙面㈣基板（C_erClad200913840 IX. Description of the invention: - [Technical field to which the invention pertains] - The present invention relates to a circuit board and a method of manufacturing the same, and more particularly, to a metal connection pad formed on an end face of a conduction hole of an electric clock for A circuit board for reducing the size of a product and its prior art. With the evolution of semiconductor packaging technology, semiconductor devices (Sennconducts devices) have developed different semiconductor devices to be packaged on a package substrate (packagesubstm= lead frame) Firstly, a semiconductor component having an integrated circuit is electrically connected to the sealing substrate or the lead frame, and then encapsulated by a colloid, wherein the ball grid array (10) Eight, etc., is an advanced semiconductor packaging technology, characterized in that a -substrate substrate is used to place and electrically connect the semiconductor device', and a plurality of solder balls arranged in a grid array are implanted on the back surface of the sealing substrate. (Solder ball), which can accommodate more input/output connections on the semiconductor component carrier of the same unit area (I/Q c (5)) In order to meet the requirements of a highly integrated semiconductor wafer, the solder balls are electrically connected to the external electronic device. 9 In addition, high-performance chips such as microprocessors, chipsets, and graphics chips are required. The operation of the package substrate for packaging needs to improve the function of transmitting the chip signal, improving the bandwidth, controlling the impedance, etc., for the development of high 1/〇 components; however, in order to meet the thinness and shortness of the semiconductor package, Development direction of multi-function, high-speed and high-frequency, the package for semiconductor chip packaging 110380 6 200913840 The board has been developed towards fine lines and small apertures; the existing circuit board process is from the traditional 100 micron line size: including wire width ( Line width and line. Space has been reduced to micron and has been continuously developed for smaller line precision. The first reading of Figures 1A to 1 is for the purpose of forming a circuit board for packaging. The cross-sectional view first provides a core plate 10 having a first metal layer 12a on both surfaces of the core plate, and is formed by a laser or mechanical drilling to form a plurality of through holes (thr Ugh_h〇le)1〇2 (as shown in the ia diagram, the two surfaces of the core plate 1 and the through holes 102 are formed into a conductive layer 11a (as shown in FIG. 1B); Leading the surface of the 曰la surface into a second metal layer 12b, and opening/forming the plated through-hole (PTH) 120a in the through hole 1〇2, and filling it with the filling material 12〇 The electroplating via hole 12〇a (as shown in FIG. 1C), and then the second metal layer 12b, the plating via 12 (ie, and the surface of the true filling material I20 are plated to form a second conductive layer lib (eg, 1D (none), and then a third metal layer 12c is formed on the surface of the second conductive layer lib (as shown in FIG. 1); thereafter, a resist layer 13 is formed on the third metal layer 12 And the opening 13 is formed in the resist layer 13 to expose a portion of the surface of the third metal layer 12c (as shown in FIG. 1F); then the first of the openings 13 is removed by optical lithography, etching, or the like. a metal layer 2a, a first conductive layer 11a, a second metal layer 12b, a second conductive layer lib and a third metal layer 12c to form a patterned circuit layer 14, and the line 14 has a plurality of metal connection pads 141, and the resist layer 13 is removed to expose the circuit layer 14 and the metal connection pads 141, and the metal connection pads 141 110380 7 200913840 are located at the end faces of the money money vias 12Ga (eg, Ig diagram); the rear side, the core ~ plate 1 〇 and the circuit layer 〗 4 surface forming a line build-up structure 15 I spring road build-up structure J 5 series including a dielectric layer n stacked on the 兮 dielectric layer a circuit layer 151, and a conductive via hole 152 ′ formed in the dielectric layer, and a portion of the conductive via 152 electrically connected to the metal connection 塾 141 of the circuit layer u to form a conductive The blind hole 152 is formed on the surface of the plated via hole 12〇a (Via〇npTH, V0P), so that the contact pad (P ad ) is not required to be extended from the plated via hole for the connection of the lead. Field, line density. The surface of the line-increasing layer 15 is formed after the cloth of the inner layer line is increased (p and the surface of the line-adding structure 15 has two = (4) the surface of the factory insulating protective layer 16 has a complex Table: =. The electrical connection 153 of the line build-up structure 15 (such as the third: However, the above method has the disadvantage that two surfaces on both sides of the core board 1 must be formed to form the second and third ^ The 転 12b'12c' will pass the above process to make the core board i: too thick, and then (4) when forming the line, due to the side (four) factor, the factory line spacing can only reach 75 Jing (four), but can not form the second road. The clock is formed twice and the second (the spring road, there will be a problem that the thickness of the circuit layer is too thick, and it cannot be formed, so ^ how to propose a kind of circuit board and method to avoid the two structures. On both sides, all the surfaces are exempted from the white knowing technology into a layer of copper to make the two surfaces of the circuit board 110380 8 200913840 after the 'though can not form a fine line, so it is not easy to meet the needs of high-order electricity. Has become the industry to be overcome SUMMARY OF THE INVENTION [Technical Summary] The present invention is directed to the disadvantages of the above-mentioned prior art, and the main object of the present invention is to provide a thin circuit for the circuit board 1ί7, which is the end of the electric material through hole. A metal connection port is formed on the part for the purpose of making money for the use of fine lines. = For the above and other purposes, the present invention provides a circuit board, a package, a core board, which has a relative relationship: Two surfaces, and a τ shell hole penetrating the two surfaces, the core plate is a double-sided (four) substrate (C_erClad
Laminates, CCL)或内層具有岭路 雷跟如· 曰八有、，泉路而表面壓合有介電層之 痛通孔，係設於該貫孔中；填充材 殖 表面，且係由第一及第二圖荦化全：厶板 圖案化金屬層設於該核心板==== =電錄導通孔之外側表面，而該第 圖案化金屬層表面並具有覆蓋於該電鍍導通曰孔：、 端部、填充材料及金屬環的金屬連接塾。 之 2述結構，於該電鑛導通孔中具有 充材料係為導電材料不導料料；於㈣—及=-該填 案化金屬層之間具有第二導電層。 —圖 ::該核心板及第—線路;表面具有 構，輯路增層結構係包括有介電層、疊置於該介曰電曰;上 110380 9 200913840 之第二線路層，以及形成於該 -線路層之導電盲孔，且部分 ：中亚電性連接該第二 路層及金屬連接墊所組群組之其n電性連接該第一線 構表面復包括有電性連接該第 x °玄線路增層結 於該線路增層結構表面具有表;電性連接塾，且 表面具有複數個開孔以露該絕緣保護層 本發明復提供-種電路板之L係包括 、板，係具有相對應之兩表面， "人 ，層，以及貫穿該兩表面之至少一==有弟-金屬 中之表面形成電鍍導通孔;㈣二於㈣心板之貫孔 料；於該第一金屬層表 充材 -第二導電層:於該第二導電二=之：面形成有 ^ „ 笔0上形成有一弟二阻層，續 弟-阻層中形成複數第二開口及第三開口，发中該第二門 於該核：板之電鑛導通孔的端部位置;於該第二： ^形成-第—圖案化金屬層，並於該第三開口中形成金 I =接墊，以對應該電錢導通孔的端部；卩及移除該第二 ^及其所覆蓋之第二導電層、與第一金屬層，使該第二 ^層及第-金屬層形成第一圖案化金屬層，且該第一圖 二化金屬層具有電性連接該電銀導通孔之外側表面之金 屬環’並使該金屬連接塾覆蓋於該電鑛導通孔之端部、'殖 充材料及金屬環，俾使該第一及第二圖案化金屬層構成第 "線路層。 依上述之製法，該電鍍導通孔之製法，係包括：該核 心板兩表面具有第-金屬層；於該核心板兩表面之第一 110380 10 200913840 金屬層及該貫孔中 .導電層表面形成有：一形、有二第：導電層;於該第一 -孔形成有第一開口. 阻層且5亥第一阻層中對應該貫 -導電層表面二二路=阻層之第-開口中的第 成該電鍍導通孔；移 、〜貝孔中之表面形 入該填充材料，二於該電鑛導通孔中填 以及移除該第二全屬電材料或不導電娜 ，以完全露出該第層“電層與多餘之填充材料， 構，該線層表面形成有一線路增層結 之第二該介電層上 線路層之導電盲孔，且部份之導；；孔：：：該第二 及金屬連接墊所組群組之其中一者，又二 =接遠線路層 面復包括右雨Μ·、± 卜 者又该線路增層結構表 崎路抑展％連接該第二線路層之電性連接塾，且於★亥 且有射 =構表面形成一絕緣保護層，該絕緣保護層表面 八有设數個間孔以露出該電性連接墊。 電鐘=1 月Γ電路板及其製法，主要係在核心板之貫孔中 -線路居導通孔，亚於該核心板之二相對表面形成第 成，1二^第一線路層係由第—及第二圖案化金屬層組 之入^ 圖案化金屬中具有位於該電鑛導通孔周緣 。孟屬龟，使後續形成於該第一圖案化金屬上表面之第二 圖案化金屬層及金屬連接墊，該金屬連接墊位於該電鍍導 :孔之蠕部、填充材料及金屬環上，使形成於該第—線路 曰上之線路增層結構，其中之導電盲孔電性連接該金屬連 U0380 11 200913840 .i妾塾二：有效利用辕路佈局面積，以提高線路佈設密 : 〜“反之貝孔令電鍍形成該電鍍導通孔，並移除 -核心板表面之笫-厶居& 钞丨示 金屬層及第一導電層’僅留下貫孔中之 :又（孔及该核心板表面之第一金屬層，而非如 在核心板兩側之整個声 般 、面王邛電鍍形成一層金屬，因而可 低核心板表面供形成線路之全屬戶之厚戶，w 4丨μ 細線路。 峪之孟屬層之厚度’以利於形成 【實施方式】 广下係#由特定的具體實例說明本發明之實施方 式’熟悉此技藝之人4- 7 Λ + 由本说明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 ^閱第2U2L圖’係為詳細説明本發明之電路板 之衣法的剖面示意圖。 如第2A圖所示，首先，提供兩相對表面形成有第一 二屬層21 a之核^板2 G ’該核（、板2 Q係為—雙面銅羯基 ^PPer Clad Laminates，CCL)或内層具有線路而表面 ^ ΐί ;1電層之電路板；本實施例係以銅㉝基板（CCL)為 歹Μ况明’該核心板20 @表面分別具有—第一金屬層 叫，復以機械鑽孔方式或雷射鑽孔方式於該核心板 中形成複數個貫穿之貫孔200;該第一金屬層2u係為導 電性較佳之銅（Cu)，且該第一金屬層…以壓合或沉積於 邊核心板2 0表面上。 如第2B圖所示，接著，利用物理沈積例如㈣ (Spuuering)或化學沈積例如無電鍍方式，以於該核心板 110380 12 200913840 f =兩表面及貫孔200中之表面形成一第一導電層22a， 第V笔層22a主要作為後述電鐘金屬材料所需之電 流傳導路徑’其可由金屬、合金或沉積數層金屬層所構 成如選自銅、錫、錄、鉻、鈦及銅_鉻合金等所組群組 之其中一者’或該第一導電層仏係為聚乙炔、聚苯胺或 有機硫聚合物等導電高分子材料。 弟2C圖所示，於該第一導電層22a上形成一第一 〆 :層23a’以―阻層23a可為一例如乾膜或〉夜態光阻等 光阻層（PhotQresist)，其係利用印刷 式形成於該第-導電卿面，再藉由曝光;;;： 式加以圖案化以形成複數個第一開口 23ia，且該此第一 化係相對應形成於該貫孔2。〇 ;弟; 核心板2〇表面及該貫孔200外端面之 = 部分表面。 守电層22a的 如弟2D圖所示，葬由兮穿 奎道w 猎由5亥弟一導電層22a作為電铲之 毛流傳導路徑，以於該些第_開口心 电鐘之 表面及貫孔200中之表面之部^ 2^0 成一第二金屬層並於該貫卿中仏:形 孔211b;其中該第-厶展昆〇1 X 电鍍導通 加八 屬層2lb之材料可為鉛、銘/ :、金，録、鋅、錄、錯、鎂、銦、 踢、：、 惟，依實際操作之經驗，由於銅為成熟之金屬； 二低’因此，該第二金屬層叫以由電鍍 ：成本 佳’但非以此為限。 成者為較 如第2E圖所示，移除哕筮 鍍 除°亥苐-阻層％以露出該電 110380 13 200913840 導通孔211b之外端面。 如第2F圖所不’於該電鍍導通孔中填入帝 IS::填充材料24(如絕緣性油墨或含銅導電膏等） 填滿该電鍍導通孔211b殘留之空隙。 广圖所示’移除該第二:屬層2ib、第 fla a與夕餘之填充材料24,以完全露出該第一金屬層 '導通孔圖所不’於该第—金屬層21a表面及該電鍍 端面形成有-第二導電層㈣該第二導 久盆後述電錢金屬材料所需之電流傳導路 用%二 合金或沉積數層金屬層所構成，或可使 用例如小乙块、聚苯胺或有機硫 = 以作為該第二導電層22b。 刃年绔电间刀子材科 如弟21圖所示，於該兹_憎+ 阻層23b，該第二阻層23b ^氣層娜上形成一第二 (^^CPh〇t〇resls；) 、式形成於該第二導電層22b 刷/旋塗或貼合等方 式加以圖案化，使該第二稽由曝光、顯影等方 灿及第三開口，其中層4 成複數第二開。 心板之μ導軌⑽_卩;;心2咖形成於該核 如第2 J圖所示，然後進行 電層22b具導電特性以作為•時二程’精由該第二導 該第二阻層23b之第二開口伽、之^流傳導路徑，俾於 化金屬層25b，且於該第三開：鍍形成-第二圖案 開口 233b中形成一金屬連接 110380 14 200913840 墊251b對應該電鍍導通孔2m外端部，以與該電鍍導通 孔211b直接電性連接；其中該第二圖案化金屬層挪及 金屬連接墊251b之材料係如斜、錫、銀、銅、金、叙、 銻、鋅、鎳、锆、鎂、銦、碲以或鎵等金屬；惟，依實際 操作” ’由於銅為成熟之電鍍材料且成本較低，因' 此忒第一圖案化金屬層25b及金屬連接墊251b以由電 錢銅所構成者為較佳，但非以此為限。 如第2K圖所不’移除該第二阻層23b及其所覆罢之 ‘第二導電請、與第一金屬層…，使該 圖案化金屬層25a具有電性連接該電鑛導通孔2爪之外 之金屬環251a’並使該金屬連接墊抓覆蓋於該 孔211b之端部、填充材料24及金屬環仙， =及第二圖案化金屬層㈣細構成第一線路 曰25，由於移除該第二阻^^ , M ^ 丨且層23b及第二導電層22b之製 (各知屬篇知者，故於此不再為文贅述。 如第2L圖所示，於該核拓 A x。板20及苐一線路層25表 面形成有一線路增層結構26，爷的 入 及、、泉路增層結構26係包括 有彳丨电層261、疊置於該介電芦 η ,, θ 之弟一線路層2 6 2，以 及形成於該介電層中並電性遠 oco 運接该弟二線路層262之導 兒目孔263,且該些導電盲不9rq^ 八β人η忠 L 263电性連接該第一線路層 及孟屬連接墊251b所組群組之其中一 層結構26表面復包括有並電性 …7 a 1*^ - OC/f Q 电芘連接5亥弟二線路層262之 包〖生連接墊264，且於該線路增 曰智結構26表面形成一絕 110380 15 200913840 緣，護層…朗絲護層27表面具有複數個開孔27〇 -以露出該電性連接墊264。 -纟於該線路增層結構26中之部份導電盲孔挪電性 ^妾位於該電链導通孔211b之端面的金屬連接墊25lb ^面’使該線路增層結構26中之導電盲孔263直接電性 連接於該電鍍導通孔211bi μ ,丄 、孟屬運接墊251b，以達到 縮小線路以達線路細間距 a n 的進而付有效利用線路佈 局面知，以提高線路佈設密度。 忐2卜本％明係於该核心板20之貫孔200中電鍍形 ^電鑛導通孔⑽，並移除核心板2〇表面之第二^屬 層21b及第一導電層22a，而僅 、’ 導通孔2Ub,而非如習知_在妨下f貝孔200中之電鑛 部電鐘形成—層金屬，因而之整個表面全 =層之厂子度以利於形成細線路，且可降低電路板之整 復提供一種電路板’係包括：核心板 具有兩表面，於該核心板 200 * , 夕―貝穿該兩表面 該電二二設於該貫孔2◦。中，於 ^ f # .4 ^ ^ ''24 5 ^ ^ 24 於該核心板2〇表面，且及第f線路層25,係設 25a，25b組成，” “弟一及第二圖案化金屬層 板20表面並具有金屬 。又、〜核心 ⑽之外側表面，而:第251二電性連接該電錢導通孔 而4弟二圖案化金屬層2讥設於該第 110380 】6 200913840 一圖案化金屬層25a並具有覆蓋於該電鍍導通孔21化之 端部、填充材料24及金屬環251a的金屬連接墊2仍。 依上述結構，該核心板2〇係為一雙面銅箔基板 (Copper Clad Laminates，ca)或内層具有線路而表面壓 合^背膠㈣之電路板；復包括第二導電層挪’係設於 該第一及第二圖案化金屬層25a，25b之間。 又於該核心板2〇及第—線路層25表面具有一線路增 層、·-口構26,該線路增層結構26係包括有介電層261、疊 置於該介電層上之第二線路層262,以及形成於 ； 二線路層!62之導電盲孔263,且:： 251b= , 3 $性連接該第-線路層25及金屬連接墊 勺括右^群組之其中—者’又該線路增層結構2 6表面復 匕有书性連接該第二線路層262之電 ==結構26表面具有-絕緣保護層二: _。有㈣㈣孔270以露出該電性連接墊 電㈣ 板及其製法’主要係在核心板之貫孔中 :細核心板表面形成有苐-線路 ”第：“τ'由弟一及第二圖案化金屬層組成，1 屬^ Μ 金屬中具有位於該電料通孔周緣之全、 使後續形成於該第-圖案化金屬上表面之第二圖安 之連接墊，該金屬連接塾位於該電鑛導通： 之線路”?： 2屬環上，使形成於該第-線路層上 曰層結構’其中之導電盲孔電性連接該金屬連接 110380 17 200913840 墊，而得有效利用線路佈 此外，本發明係於:::板積二高線路佈設密度。 .銀導通孔，並移除核心板表面=貝孔中電鑛金屬形成電 之電錢導通孔，而非如一 f屬層僅留下貫孔中 部電㈣成-層金屬，因而=板=之整個表面全 之金屬層之厚度，有利於:路==供形成線路 整體厚度。 泉路’且可降低電路板之 上述實施例僅—性說明 非用於限制本發明。任何iw 及其功效’而 北丄 j热自此項技#之人士均可a兀、音 月本發明之精神及範疇下， 不延 變。對上述具施例進行修飾與改 冲 ,%之#利保護範圍，應如後述之申靖專利 範圍所列。 、、甲。月專利 【圖式簡單說明】 第1Α至1 η圖係為習知封裝 弟2 Α至2 L圖係為本發明 用電路板之製法；以及 電路板及其製法之剖面示意 【主要元件符號說明】 1 〇、2 0核心板 102、200 貫孔 120、24填充材料 12c 第三金屬層 130 開口 141、251b金屬連接墊 150 ' 261介電層 12a、21a第一金屬層 12b ' 21b 弟二金屬層 120a、211b 電鍍導通孔 13 阻層 14、 151 線路層 15、 26線路增層結構 152、263 導電盲孔 110380 18 200913840 153、264 電性連接墊 κ 160、270 開孔 ,22b、lib 第二導電層 231a 第一開口 232b 第二開口 25 第一線路層 25b 第二圖案化金屬層 262 第二線路層 16、27 絕緣保護層 22a、11a 第一導電層 23a 第一阻層 23b 第二阻層 233b 第三開口 25a 第一圖案化金屬層 251a 金屬環 i 19 110380Laminates, CCL) or the inner layer has a ridge ridge with a 曰 有 、, a spring road and a surface of the dielectric layer with a pain layer through the hole, is placed in the through hole; the filler material surface, and the The first and second figures are all: the ruthenium patterned metal layer is disposed on the core plate ==== = the outer surface of the galvanic via hole, and the surface of the first patterned metal layer has a covered via hole :, metal fittings for ends, packing materials and metal rings. In the structure of the electric ore, the filling material has a conductive material as a conductive material non-conductive material; and (4)- and =- the second conductive layer between the filled metal layers. - Figure: the core board and the first line; the surface has a structure, and the layer-added structure includes a dielectric layer stacked on the dielectric layer; a second circuit layer on 110380 9 200913840, and formed on a conductive via hole of the circuit layer, and a portion: the central Asia is electrically connected to the second circuit layer and the group of the metal connection pads, wherein the n-wire connection is electrically connected to the first wire structure surface The x ° mysterious line is formed on the surface of the added layer structure of the line; the electrical connection is 塾, and the surface has a plurality of openings to expose the insulating protective layer. The present invention is provided in the form of a circuit board, the L system includes, the board, Correspondingly having two surfaces, "people, layers, and at least one of the two surfaces extending through the surface of the two sides to form a plated through hole; (d) two (four) core plate through hole material; a metal layer surface filling material - a second conductive layer: in the second conductive second =: the surface is formed with a „ pen 0 formed a second two-resist layer, the second-opening and the third forming a plurality of second opening and third Opening, the second door is in the core: the end position of the electric ore conduction hole of the plate; in the second: Forming a -first patterned metal layer and forming a gold I = pad in the third opening to correspond to the end of the money guiding via; and removing the second and the second covered a conductive layer and a first metal layer, the second layer and the first metal layer are formed into a first patterned metal layer, and the first metal layer of the first metal layer is electrically connected to the outer surface of the conductive silver via hole. The metal ring 'and the metal connection layer covers the end portion of the electric ore conduction hole, the 'carrying material and the metal ring, and the first and second patterned metal layers constitute the first line layer. The method for manufacturing the plated via hole comprises: a first metal layer on both surfaces of the core plate; a first 110380 10 200913840 metal layer and the through hole in the two surfaces of the core plate. The surface of the conductive layer is formed: Forming, having two: a conductive layer; forming a first opening in the first hole; the resistive layer and the first resist layer in the 5th first resistive layer corresponding to the surface of the through-conducting layer The first plating hole; the surface of the shifting, the hole is formed into the filling material, and the electric ore is Filling and removing the second all-electric material or non-conducting nano-holes in the via hole to completely expose the first layer of the "electric layer and the excess filling material, and forming a second line-forming layer on the surface of the layer a conductive blind hole of the circuit layer on the dielectric layer, and a part of the guide;; hole::: one of the group of the second and metal connection pads, and two = the remote line level includes the right rain · 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Eight holes are provided to expose the electrical connection pads. Electric clock = 1 month Γ circuit board and its manufacturing method, mainly in the through hole of the core board - the line leads through the hole, the second surface of the core board is formed into the first phase, and the first circuit layer is formed by the first - and the second patterned metal layer group of the patterned metal has a periphery of the electroconductive via hole. a Meng turtle, which is formed on the second patterned metal layer and the metal connection pad formed on the upper surface of the first patterned metal, and the metal connection pad is located on the etched portion, the filling material and the metal ring of the plating guide hole. a line build-up structure formed on the first line, wherein the conductive blind hole is electrically connected to the metal connection U0380 11 200913840 .i妾塾2: effectively utilizing the layout area of the circuit to improve the line layout density: The behole is electroplated to form the electroplated via, and the surface of the core plate is removed - the crucible and the metal layer and the first conductive layer are left in the through hole only: (the hole and the core plate) The first metal layer on the surface, instead of the entire sound on both sides of the core board, the surface of the king is plated to form a layer of metal, so that the surface of the low core board can be used to form a line of all households, w 4丨μ thin line The thickness of the layer of the genus of the genus is formed to facilitate the formation. [Embodiment] The embodiment of the present invention is described by a specific specific example. The person familiar with the art 4- 7 Λ + disclosed by the present specification Easily understand the invention Other advantages and effects. ^2U2L图' is a schematic cross-sectional view illustrating the coating method of the circuit board of the present invention. As shown in Fig. 2A, first, two opposite surfaces are formed with a first two-layer layer 21a. Nuclear plate 2 G 'the core (, plate 2 Q is - double-sided copper bismuth base ^ PPer Clad Laminates, CCL) or the inner layer has a line and the surface ^ ΐ ;; 1 electrical layer of the circuit board; this embodiment is copper 33 substrate (CCL) is the condition of the core plate 20 @the surface has - the first metal layer is called, the mechanical drilling method or the laser drilling method is used to form a plurality of through holes in the core plate 200; the first metal layer 2u is copper (Cu) which is preferably electrically conductive, and the first metal layer is pressed or deposited on the surface of the edge core plate 20. As shown in FIG. 2B, then, Physical deposition such as (S) or electroless deposition, such as electroless plating, to form a first conductive layer 22a on the surface of the core plate 110380 12 200913840 f = both surfaces and through holes 200, the V-th layer 22a is mainly described later The current conduction path required for the metal material of the electric clock, which can be made of metal or alloy Or depositing a plurality of metal layers, such as one selected from the group consisting of copper, tin, copper, chromium, titanium, and copper-chromium alloys, or the first conductive layer is polyacetylene, polyaniline or A conductive polymer material such as an organic sulfur polymer. As shown in FIG. 2C, a first layer 23a is formed on the first conductive layer 22a, and the resist layer 23a can be a dry film or a night photoresist. a photoresist layer (PhotQresist) formed on the first conductive surface by printing, and patterned by exposure to form a plurality of first openings 23ia, and the first chemical system Correspondingly formed in the through hole 2. 〇 ; brother; the core plate 2 〇 surface and the outer surface of the through hole 200 = part of the surface. As shown in the 2D diagram of the power-storing layer 22a, the burial path is made by the 亥 奎 w 由 由 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 a portion of the surface of the through hole 200 is formed into a second metal layer and is formed in the through hole: a hole 211b; wherein the material of the first 厶 〇 X 1 X plating and the octagonal layer 2 lb can be Lead, Ming/:, gold, record, zinc, record, wrong, magnesium, indium, kick,:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, To be electroplated: cost is good but not limited to this. As shown in Fig. 2E, the 哕筮 镀 plating layer is removed to expose the outer surface of the via hole 211b of the 110380 13 200913840. As shown in Fig. 2F, the plating via hole is filled with a filling material 24 (e.g., an insulating ink or a copper-containing conductive paste) to fill the void remaining in the plating via 211b. As shown in the broad view, 'the second layer 2 ii, the first fla a and the outer filling material 24 are removed to completely expose the first metal layer' via hole pattern to the surface of the first metal layer 21a and The plated end face is formed with a second conductive layer (4). The second conductive plate is composed of a second conductive alloy or a plurality of deposited metal layers required for the electric money metal material described later, or may be used, for example, a small block or a poly layer. An aniline or organic sulfur = as the second conductive layer 22b. In the figure of the knives of the knives of the knives, as shown in Fig. 21, in the 憎 憎 + resist layer 23b, the second resist layer 23b forms a second layer on the gas layer (^^CPh〇t〇resls;) The pattern is formed by brushing/spinning or laminating the second conductive layer 22b, and the second layer is exposed, developed, and the like, and the third opening is formed in the second layer. The core guide rail (10) _ 卩;; heart 2 coffee is formed in the core as shown in Fig. 2 J, and then the electrical layer 22b is electrically conductive to serve as the second phase of the second guide The second opening gamma of the layer 23b, the flow conduction path, the metallization layer 25b, and a metal connection 110380 in the third opening: plating formation-second pattern opening 233b 14 200913840 pad 251b corresponding to the plating conduction The outer end portion of the hole 2m is directly electrically connected to the plating via hole 211b; wherein the material of the second patterned metal layer and the metal connection pad 251b is oblique, tin, silver, copper, gold, Syria, 锑, Metals such as zinc, nickel, zirconium, magnesium, indium, antimony or gallium; however, depending on the actual operation, 'Because copper is a mature electroplating material and the cost is lower, because of this, the first patterned metal layer 25b and the metal connection The pad 251b is preferably made of electric money copper, but is not limited thereto. As shown in FIG. 2K, the second resist layer 23b and the second conductive layer 23b are removed. a metal layer... such that the patterned metal layer 25a has a metal ring 2 electrically connected to the electrode of the electric mine via 2 51a' and the metal connection pad is covered at the end of the hole 211b, the filling material 24 and the metal ring, and the second patterned metal layer (4) is finely formed into the first line 曰25, since the second resistance is removed ^^ , M ^ 丨 and the layer 23b and the second conductive layer 22b (each of which is known to the person, so it will not be described here. As shown in the 2L figure, the core extension A x plate 20 And a circuit layer-forming structure 26 is formed on the surface of the circuit layer 25, and the gate layer 26 includes a germanium layer 261 and a dielectric layer 261 stacked thereon. a circuit layer 2 6 2 , and a conductive hole 263 formed in the dielectric layer and electrically connected to the second circuit layer 262, and the conductive blinds are not 9rq^ 八β人η忠 L 263 One of the layers 26 of the group of the first circuit layer and the genus connection pad 251b is connected to the surface of the structure. The surface of the layer 26 includes a galvanic connection. 7 a 1*^ - OC/f Q The package 〖 raw connection pad 264, and on the surface of the line to enhance the structure of the 26 structure to form a 110380 15 200913840 edge, the protective layer ... the surface of the Langer sheath 27 has a plurality of openings 27 〇 - to dew The electrical connection pad 264 - a portion of the conductive via hole in the line build-up structure 26 is electrically connected to the metal connection pad 25 lb ^ face of the end face of the electrical chain via 211b The conductive blind vias 263 in the structure 26 are directly electrically connected to the plating vias 211bi μ, 丄, 孟 运 接 垫 pads 251b, in order to reduce the line to reach the fine pitch of the line, and to effectively utilize the line layout, Improve the wiring density of the line.忐2布本%明 is in the through hole 200 of the core plate 20, electroplating electro-conducting via hole (10), and removing the second sub-layer 21b and the first conductive layer 22a of the surface of the core plate 2, and only , 'the via hole 2Ub, instead of forming a layer of metal in the electric field of the electric mine in the b-hole 200, so that the entire surface is full of layers to facilitate the formation of fine lines and can be reduced The circuit board is provided with a circuit board comprising: the core board has two surfaces, and the core board 200* is disposed on the two surfaces, and the electric pole is disposed on the through hole 2◦. Wherein, ^ f # .4 ^ ^ ''24 5 ^ ^ 24 on the surface of the core plate 2, and the f-th circuit layer 25, is composed of 25a, 25b," "Di brother and second patterned metal The surface of the laminate 20 has a metal. And the outer surface of the core (10), and the second electrode is electrically connected to the electric money via hole, and the second patterned metal layer 2 is disposed on the patterned metal layer 25a and has a covering layer The end portion of the plating via 21, the filling material 24, and the metal connection pad 2 of the metal ring 251a remain. According to the above structure, the core board 2 is a double-sided copper foil substrate (Copper Clad Laminates, ca) or a circuit board having an inner layer and a surface pressed and a backing (4); the second conductive layer is included Between the first and second patterned metal layers 25a, 25b. Further, on the surface of the core board 2 and the first circuit layer 25, there is a line build-up layer, and the port layer structure 26 includes a dielectric layer 261 and a layer stacked on the dielectric layer. a second circuit layer 262, and a conductive blind hole 263 formed in the second circuit layer! 62, and :: 251b=, 3 $ is connected to the first circuit layer 25 and the metal connection pad is included in the right group 'The line build-up structure 2 6 surface reclamation has a book connection to the second circuit layer 262. == Structure 26 surface has - insulation protection layer 2: _. There are (4) (four) holes 270 to expose the electrical connection pad (four) board and its method of 'mainly in the through hole of the core board: the surface of the thin core board is formed with a 苐-line": "τ" by the brother and the second pattern The metal layer is composed of a metal lining in which the metal is connected to the periphery of the through hole of the electric material to form a second connection layer formed on the upper surface of the first patterned metal. Conduction: The line "?: 2 is on the ring, so that the conductive blind hole formed on the first-layer layer" is electrically connected to the metal connection 110380 17 200913840 pad, and the wire is used effectively. The invention is based on::: slab two high-line layout density. Silver through-holes, and remove the core plate surface = Beikongzhong electric ore metal to form electricity money money conduction holes, instead of leaving only a genus layer The middle of the hole is electrically (four) into a layer of metal, so = the thickness of the entire surface of the plate = the thickness of the metal layer is favorable: the road = = for forming the overall thickness of the line. The spring road 'and the above embodiment of the circuit board can only reduce the The description is not intended to limit the invention. Any iw and its efficacy However, the people of Beibei j heat from this technology can be a兀, 音月, under the spirit and scope of the invention, and do not change. The above-mentioned examples are modified and modified, and the scope of protection of % As listed in the scope of Shenjing patents mentioned later, , A. Month patent [Simple description of the diagram] The first to the 1st η diagram is a conventional packaged brother 2 Α to 2 L diagram is the method of manufacturing the circuit board for the invention; And the schematic diagram of the circuit board and its manufacturing method [main component symbol description] 1 〇, 20 core board 102, 200 through hole 120, 24 filling material 12c third metal layer 130 opening 141, 251b metal connection pad 150 ' 261 dielectric Layer 12a, 21a first metal layer 12b' 21b second metal layer 120a, 211b plated via 13 resist layer 14, 151 circuit layer 15, 26 line build-up structure 152, 263 conductive blind hole 110380 18 200913840 153, 264 electrical Connection pad κ 160, 270 opening, 22b, lib second conductive layer 231a first opening 232b second opening 25 first wiring layer 25b second patterned metal layer 262 second wiring layer 16, 27 insulating protective layer 22a, 11a First conductive layer 23a first resistive layer 23b second resistor 233b third opening 25a of the first patterned metal layer of the metal ring 251a i 19 110380