TW200900951A - Serialization of data for multi-chip bus implementation - Google Patents

Abstract

Bus communication for components of a system on a chip. In One aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer provided on a first device serializes information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device. In an aspect of the invention, a slave uses the first protocol and is coupled the second serializer, where the deserialized information is provided the slave, and the slave provides a response to the information from the bridge.

Description

200900951 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to an integrated circuit system, and more particularly to a busbar architecture for an integrated circuit system. [Prior Art] System single-chip (S〇C) design integrates computer or other electronic I or system components into two or all components into a single integrated circuit chip, and is generally used to improve system performance. And easy to manufacture. A typical Soc includes - or multiple microcontrollers (eg microprocessor or DSP core) memory, peripherals, interfaces, timing sources, voltage regulators and power management circuits and external interfaces. The components of 〇C are connected by a proprietary or industry-standard crystal busbar, allowing the components of the SoC to interface with each other. - This type of Guardian standard busbar is from ARM's advanced microcontroller busbar architecture. (AMBATM) 'One of the 丧 丧 ( (10) is a common epoch structure. The AMBA crystal bus is an open specification that is used as a framework for s〇c design. The use of the AMBA specification will The library cores are combined and used by the library components. By designing for the standard AMBA interface, modules can be implemented and tested without the prior knowledge of the system that the component will eventually integrate. The AMBA bus includes two different protocols, an Advanced High Performance Bus (AHB) and an Advanced Peripheral Bus (APB). The ahb bus is faster than the APB bus and is typically used as a high-performance system backbone. Figure 1 is a block diagram of a typical AMBA system 10 and shows the integration of AMBA AHB and APB busbars using a multi-130924.doc 200900951 layer interconnect matrix. These layers include: an AHB matrix 12, which will AHB -Lite master device 14 is coupled to AHB-Lite slave device 16; and an AHB/APB bridge 18 that connects APB slave device 20 to the AHB matrix 12. A bus master device can provide address and control by providing address Information to initiate read and write operations. Generally, only one master device is actively used to use the bus at any one time. A sink _ stream slave responds to a device within a given address space. Read or write operation. The slave device will transmit the success, failure or waiting to send back to the active master device. The master device and the slave device in the system 10 can be standard AMBA AHB components, or "AHB-Lite" components (as shown 1)) AHB-Lite is a subset of the complete AHB specification and can be used to design a single busbar master, ie a simple single master system or one with only one AHB master per layer. Multi-layer AHB system. AHB-Lite simplifies the AHB specification by removing the protocols required for multiple bus masters, making the main design for the AHB-Lite interface specification compared to a complete AHB master.

V is simpler in terms of interface design. Figure 2 is a block diagram of an AMBA bus system including one of two integrated circuit chips. A common method is to divide a SoC component onto two or more wafers (e.g., wafers 42 and 44) that communicate with one another using a standard interface (e.g., AMBA). Typically, the AHB and APB busbar interfaces are available for each master and slave device outside each wafer to allow interfacing with other wafers. In Figure 2, the AHB busbars 46 and APB busbars 48 interconnect the two wafers 42 and 44, wherein the wafer 130924.doc 200900951 44 provides the system 40 with 12 additional master and slave devices. One of the disadvantages of the system is that the complexity and overall cost of the system grow exponentially based on the number of ahb and smoke interface busbars required for all wafers in the entire system. On average, the number of lines required for each thin and APB bus is (10) or higher; this number depends on the number of addresses required by the slaves. This method becomes impractical when the number of required AHB and APB interface bus bars is limited by the available ι/〇 pin. Drag + + . T丨 does not change 5. The maximum number of AHB and ΑΡΒ interface buss depends directly on the number of available 1/pins. Therefore, for example, in the example of FIG. 2, if the average number of lines per busbar is 100, and the number of such lines is multiplied by the number of master devices and slave devices (12), at least I·1 is required. 〇 pin to meet the interface requirements. Therefore, if a plurality of master devices and slave devices are included in the system (this is generally the case), the number of communication lines required may be greatly increased, which may be impractical due to the high requirements of I/O pins. And/or greatly increase the complexity and cost of the SoC. Therefore, in many applications, it would be desirable to connect one of the components of the system single chip by means of a busbar architecture without the need for many communication lines and the accompanying complexity.

SUMMARY OF THE INVENTION The present invention of the present application relates to bus communication for components of a system single wafer. In one aspect of the invention, a system comprising busbar communication includes a -matrix' that is operable to select a destination for information on a busbar connected to the matrix. Provided on the first fruit, one of the first 130924.doc 200900951 The continuator contiguously receives the information received from the matrix and transmits the continuously synchronized information through a communication bus. Providing, on a second device, the first continuator receives the continuously synchronized information and de-continuing the continuous information. The providing the de-continuated information is provided to the second Peripherals on the device. In another aspect of the invention, a method for providing bus communication includes continuing to communicate bus information received from a matrix and communicating through a communication using a first continuator provided on a first device The bus bar transmits the continuously updated bus information. Using a second continuator provided on a second device to receive and de-continuation of the successive bus queriers from the communication bus, wherein the de-continued information is provided for providing A peripheral device on the second device. A similar aspect of the present invention is a medium-capable medium that includes program instructions for implementing similar features. In another aspect of the invention, a system including busbar communication includes a matrix operative to select a destination for information on a plurality of busbars connected to the matrix, wherein the matrix is provided On a first wafer. A first contigator provided on the first wafer contiguously receives information received from the matrix and transmits the continuous scallop via a communication bus. A second continuator provided on a second wafer receives the serialized information and de-continuates the successive information. A peripheral device provided on the second wafer receives the decomposed information from the second serializer. The first and second contigators will automatically wait for the loop to introduce a communication protocol for the communication bus to allow for the continuation of the information. 130924.doc -9- 200900951 The invention of the present application relates to the use of (iv) for the assembly of components of a system single wafer, and the provision of a row. In one of the present invention, s. ^ 〜, the sample includes a convergence to a slave device, and a system includes a selectable field, ..ra ^ ', 乍 for the first A bus bar protocol and a bridge that uses a two-bus-bus protocol to enter the row matrix. Coupling a to one of the bridges - 嫱 β ' Continuation D. The information received from the bridge is connected, and only through a communication bus, the information is continuously updated. Coupling to the communication bus - the first _ spears a continuation of the fast receiving the contiguous capital

The news and the continuous information release car 嫱 'Beiyu solution continuous. A slave device uses the first protocol and engages the second contigator, wherein the de-continued information is provided to the slave device, and the slave device provides a response to one of the information from the bridge . In another aspect of the invention, a method for interfacing a busbar system: a busbar communication for a slave device includes receiving parallel busbar information from a bridge. The parallel busbar information is addressed to The slave device, wherein the bridge is operative to interface a first bus bar protocol with a bus bar matrix using a second bus bar protocol different from the first protocol, and wherein the slave device is used The first busbar agreement. The parallel bus information is continually transmitted and transmitted on a communication bus. A wait loop for one of the bridges is inserted during the continuation of the parallel bus information and the transmission of continuous information. A similar aspect of the present invention provides a computer readable medium that includes program instructions for implementing similar features. In another aspect of the invention, a method for interfacing communication with a slave device includes providing a selection signal to the slave device and enabling a k number to enable communication with the slave device. The choices provided by the bridge 130924.doc -10- 200900951 The signal and enable signals are operable to interface between two different busbar protocols in a busbar system. A receive-wait signal that causes one of the bridge (four) to wait until continuous communication with the slave is completed. A similar aspect of the invention provides a computer readable medium that includes program instructions for the actual features. The present invention reduces the interconnect complexity and expense when providing a bus system (e.g., a gossip system) across multiple devices (e.g., wafers). The number of lines required to allow inter-wafer 2 devices and slave devices to communicate in the system is reduced by a value of f. Moreover, the cost of the entire system board is reduced by reducing the high cost of the 1/0 pin. [Embodiment]: The invention relates to an integrated circuit system, and more particularly to a busbar architecture of an integrated circuit system. The skilled person can make and use the present invention to provide: in the context of the requirements of this requirement, 1 2 = a patent application and V.. various modifications of the specific embodiment 'and 2 will easily understand the comparison Sign. Therefore, the present invention is not intended to be limited to the scope of the invention described herein, and the invention may be limited to the specific embodiments disclosed herein. mouth. The invention is based on (4) the specific circuit provided in the specific real (4). = Lieutenant This technology will easily understand that this circuit will operate effectively in other implementations and =. It will also be based on a particular disk having a particular step or state: the invention. However, the method and system are effective for other methods having different and/or additional steps of operational inconsistency. 130924.doc 200900951 To more specifically illustrate the features of the present invention, reference is made to Figures 3 through 29 in conjunction with the following description. Figure 3 is a multi-chip system single chip (S〇C) 100 of the present invention - block diagram 0 can be used in a number of stations / devices (such as integrated circuit chips or similar devices) System 100 is provided on any suitable board, platform or substrate for communication between such devices. In the exemplary embodiment of FIG. 3, system 100 includes two dies (wafer 1 〇 2 and wafer 〇 3), the system 100 is distributed over the crystals, and the wafers are via multiple communications. Bus connection. For example, the present invention can be used to prototype a mine eight bus system on a development board using a base system wafer (a wafer 1 in the example of FIG. 3) including one of the main components as a reference and Additional primary and/or secondary devices are added to one or more different devices (wafers 1〇3 in the example of Figure 3). Other embodiments of the system 100 can distribute the components in different ways in different ways, S/Both, and/or include additional devices required by the desired application. system! 〇〇 includes a processor 104 and a matrix 1〇6. The processor 1〇4 can be any suitable controller, such as one or more microprocessors, an application specific integrated circuit (ASIC), a digital signal processor (Dsp), and the like. The processor 1-4 is consuming to the matrix 1G6, which provides a communication architecture that interconnects the various slave devices of the SqC system with the host device to allow it to communicate. The matrix 106 generates control signals in accordance with management protocol timing (e.g., the illustrated protocol timing of the example_). The matrix 106 generally includes a plurality of bus rows provided in parallel. Each bus bar supports a high frequency wide information stream. The matrix 1 可 6 can be configured to communicate 'including maintaining incoming signals for receiving slave devices and I selecting signals for the 130924.doc 200900951 slave device. The matrix 106 can select which of the slave devices to transmit to a slave device and which signals from the slave device to a master device. The matrix 10 can handle simultaneous requests from a plurality of master devices to a particular slave device by selecting a master device that will access the slave device. The matrix 106 is connected to a variety of multiple master and slave devices. These master and slave devices can be used with a variety of electronic devices and components. Here, the main device and the slave device are collectively referred to as "peripherals". In the example of FIG. 3, a plurality of master devices and slaves are included on the same wafer 1〇2 as the processor 104 and the matrix 〇6, thereby allowing a complete system single chip 丨〇2. These primary and secondary devices include an AHB master 110 that is coupled to the matrix 106 by an AHB bus 112. Also included on the wafer 1 〇 2 is an ahb slave device 114' which is connected to the matrix by the AHB bus bar 112. An ahb/APB bridge 116 can be included on the wafer 102 to allow connection from an AHB matrix to an [alpha][beta] device. The bridge 丨6 is coupled to the matrix 〇6 by the AHB bank 112, and is connected to the APB slave device 1 i on the wafer 〇2 by the bus bar 12 。. A plurality of other busbars and their connections are provided on the wafer 102, and the busbars and their connections are intended to be connected to other additional master devices and slaves on other wafers (e.g., wafers i3).曰曰曰#1〇3 includes additional peripherals that can communicate with other peripherals of the system, including additional master and slave devices. According to the present invention, the connection bus between the wafers 1〇2 and 1〇3 has a continuator on the wafer 102 and the wafer 103 to greatly reduce the number of busbar connections required, thereby reducing the complexity of the system 100. Sex and cost. In communication with the master and slave devices on other wafers, the present invention has a 130924.doc •13-200900951 continuator and de-continuator that replaces hundreds of wires. The type of continuator on wafer 102 differs for different devices and includes: a main continuator (MS) 1 26 ' is connected to the ahb bus bar 112 and used for the AHB master device 110; from the continuator (SS 128 is connected to the 5 HM AHB bus bar 112 and used for the AHB slave device 114; and the APB is connected to the bus bar 120 from the continuator (APB S) 130 0 ' and is used for the ΑΡΒ slave device 118. Each type of continuator has a specific interface and components to control the appropriate timing for its associated bus and device. These continuators are generally described in more detail in conjunction with FIG. The continuous information transmitted from a serializer 126, 128 or 130 is transmitted to a serializer on the other wafer ι by an inter-wafer communication bus. The bus bars 132 are used for the primary continuators 126, the bus bars I34 are used for the slave continuators 128, and the bus bars 136 are used for the ΑΡΒ slave continuators 130. In this example, the bus bars are shown as having only 11 or 12 lines each' compared to the more than 100 lines used in previous implementations of the standard, which significantly reduces the number of lines. A continuous clock 丨 24 is used to manage the continuous communication provided through the bus bars 132, 134 and 136. A similar continuator on the chip 103 transmits and receives information through the bus bars 3, 134 and 136. The main serializer 138 transmits and receives signals on the bus bar 132, transmits and receives signals from the serializer 140 on the bus bar 134, and the APBS serializer transmits and receives signals on the bus bar 136. The successiveizers de-continuation of the received signals and provide the de-continuated signals to the masters on the wafer 103 connected to the serializers 130924.doc -14- 200900951% Or from the device. For example, the continuator 138 provides signals to the additional AHB master 144 on the bus 145, the continuator 140 provides signals to the additional AHB slave 146 on the bus 147, and the continuator 142 is in the bus The signal is supplied to the additional aPB slave device 148. When the peripheral device on the wafer 103 transmits the tribute back to the components provided on the wafer 102 through the bus bars 132, 134, and 136, a communication similar to the communication described above but in the opposite direction is performed. The serializers can be implemented by software instructions that can be stored on a computer readable medium (such as a memory, a hard disk drive, another magnetic disk, a compact disk (CD_R〇M, DVD-ROM), etc.). And the functionality of other components of the system. Alternatively, some or all of the functions may be implemented using a hardware (logic gate, etc.) or a combination of software and hardware. Figure 4 is a block diagram showing one of the continuousizer systems of the present invention. These continuators need to adhere to the bus protocol timings used (for example, AMBA bus timing) so that they do not violate the agreement. The continuator system i5 includes a continuator 152 and a continuator 154 that can communicate across a communication bus 1S6. In the illustrated example, a continuator 152 is provided on the wafer 102 and a continuator 154 is provided on the wafer 1' such that the busbar 156 is coupled between the two wafers. Other configurations may be used in other embodiments. In the example of Figure 4, the continuator ι 52 receives parallel information from a "continuous front" ahb or APB bus 158, where it is intended to transfer the information to another wafer 103. Continuator i 52 includes a finite state machine (FSM) 130924.doc -15- 200900951 Control block 16G' This block l6G is used to control continuous communication and to introduce automatic wait cycles in the communication of information. These wait cycles are implemented during the continuation procedure and - directly (4) have received a response from the addressed master or slave. The number of automatic wait cycles inserted depends on the ratio between the continuous clock and the hclk frequency. If the ratio of the continuous clock to the HCLK frequency is increased by 'the number of automatic wait cycles is reduced. In an exemplary concrete case (4), the following relationship can be used to approximate the number of automatic HCLK wait cycles: Waiting loop = Tsyne 1 + Treq + Pr + D (4) + Tsync2 where Treq requires 8 consecutive clock transmission requests, The Tres system requires 8 consecutive clock transmission responses. Pr has a variable number of clock-dependent peripheral responses depending on the particular peripheral device, while Tsync1 and Tsync2 systems synchronize the continuous clock with HCLK-left and HCLK-right, respectively. Time (which is typically a HCLK cycle). For example, if the continuous clock has a frequency of 200 MHz and the HCLK has a frequency of 50 MHz, and the peripheral response pr is i Hclk cycles, the Treq is equal to 8/(200/50) (which is ugjHCLK) Loop), and Tres is equal to 8/(200/50) (which is 2 11 (:1^ loops). Therefore, the total wait loop will be 1 + 2 + 1 + 2 + 1 or 7 HCLK cycles. The FSM control block 160 provides parallel information to a shifter ι 62 and receives parallel information from the shifter 1 62. The shifter is used to offset the parallel information into a continuous form for transmission, or to continuously transmit information. The offset is in parallel for reception. The transmitted continuous information or received continuous information is via 130924.doc -16* 200900951 a bidirectional I/O block 1 64 (which is connected to the communication bus 1 56) The shifter 162 communicates or communicates to the shifter 162. The FSM control block 160 can also transmit and receive certain signals directly via the bidirectional I/O block 164. Crossing the busbar 1 56 will lend The information that is continuous by the continuator 1 52 is passed to the continuator 1 5 4 (which in this example acts as a de-continuator). The 154 receives the information in a bidirectional 1/〇 block 166 and provides the continuously synchronized information to a shifter 168 (and/or provides & FSM control no).

The shifter 168 provides decomposed (parallel) information to the FSM control block 170. The FSM control block 170 provides the information to the successive rear AHB or APB bus (and on the continuous front end of the transmission) The type of bus protocol used is the same). The bus provides the information to the peripherals connected to the bus. Similarly, the information from the peripheral devices on the wafer 1〇3 is continuously transmitted on the wafer 1〇2, and the information is transmitted and de-continuated. In addition to the continuator component such as 忒, the present invention enhances one of the AHB/ApB bridges 116 to allow the bridge to support a wait cycle on the side of the system. Modifications to the AHB/ApB bridge 116 are described in detail below in conjunction with FIG. Each of the contigators 152 and 154 has a specific interface and an FSM control block to control the appropriate timing for its application. For example, the main serializer 126 can be designed to be hosted to the AHB main serializer with the AHB (or AHB_Lhe). The money is captured before all signals from the master arrive at the bus matrix, and the continuator state machine inserts an automatic wait loop to allow the master to wait until it is set from the addressed A. . The slave continuator (3) can be designed to continually harmonize the piano with the AHB (or AHB_Lite) interfaced with the AHB (or AHB_Lite). The signals are captured before all signals from the busbar matrix 1〇6 arrive at the fun slave device' and the continuator state machine inserts an automatic wait loop to allow the matrix to wait until a correct appearance occurs from the addressed slave device Respond. The MPBS continuator 13 is designed to interface with the APB slaves. The signal is captured before the slave AHB/APB qualifier 116 has a signal to reach the narration device, and the continuator state machine is inserted into the automatic f, cycle to allow the bridge to wait until the slave The slave device of the address has a correct response. The details of each particular type of continuator associated with different applications are described below, wherein the main continuators are described with reference to Figures 5 through 12, which are described with reference to Figures 13A through 19, and reference figures 20A to 28B illustrate the APBs from the continuator. Figure 5A illustrates a block diagram of a standard prior art ahb master device 14 and its interface. An AHB-Lite master device is shown as the master device 14 in Fig. 5A. The AHB master device 14 begins all transmissions to the AHB matrix 12. The interface required by the ^AHB-Lite master includes an HCLK signal 180 and an HRESETN signal 182. The master device provides the signals 184 to the AHB-Lite bus and is thereby provided to the matrix 12. The signals 184 include one of the addresses on the bus HADDR and the data on the bus HWDATA. The AHB-Lite master device 14 receives input signals 1 86' from the AHB-Lite busbar including data from a slave device or other peripheral device on a busbar HRD. Figure 5 is a timing diagram showing the timing of the signals provided in the main device interface of Figure 5. Figure 6 is a block diagram showing a standard wafer layout 200 for one of the primary devices in one of the prior art SoCs 130924.doc -18-200900951. A first wafer 202 includes one of the AHB matrix 12 and AHB and APB peripherals 206 in communication with the matrix. A second wafer 204 includes a number of AHB masters 2〇8. As shown, the prior art configuration requires 113 communication lines in each busbar 46 to connect a single AHB master between wafer 204 and wafer 202. If multiple masters are connected in this manner (as shown and are generally the case), the total number of required pass lines is greatly increased, thereby increasing the complexity and cost of the s〇c. Figure 7 is a block diagram of a wafer layout system 220 for one of the inter-wafer ahb master devices in one of the present inventions. For example, the wafer layout system 22 can be provided on a board 222 or other suitable substrate or platform. The board 222 includes a first wafer 102 and a second wafer 103 in communication with the first wafer 112. The first wafer 1〇2 includes a matrix 1〇6 and an AHB and ApB peripheral device 228. Peripheral device 228 may include any components that use such AHB and APB protocols, including AHB/APB bridge 116, master and slave devices on wafer 102, one or more suitable controllers (microprocessors, application specific products) Body circuit (ASIC), digital signal processor (DSp), etc. and other suitable components. In accordance with the present invention, each busbar system provided via a matrix 106 to be connected to a master device provided on a different wafer is coupled to a main serializer (MS) 126. As explained above, the main serializer 126 continually synchronizes the information transmitted from the wafer and de-interleaves the information received from the different wafers, as appropriate. The wafer 103 is also provided on the board 222 and includes N main unit buckets for use in conjunction with the busbar architecture and the matrix 〇6 of the wafer 102. The main unit μ# 130924.doc -19- 200900951 may be an additional main step device as shown in Fig. 3 above, or a main unit required for the system, as appropriate. Each of the main master devices 144 has a busbar 145 to be connected to another wafer 102. In the system of the present invention, the mother-bus I45 is connected to a main serializer 138 (which is similar to the main serializer 126 provided on the wafer 102). Each of the main violations of the main serializer 13 8 is coupled to an associated main body by a communication bus 132. In the example shown, 'because of the continuation, only 12 lines are required for each echo, which is significantly less than the other f" systems and methods. In the illustrated embodiment, the one channel of the communication channels is bidirectional, and thus the number of lines between the wafers 102 and 103 is allowed to be minimized. The method of the present invention is based on the observation of AA. 裯 等 等 等 等 等 在 在 在 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 AA AA AA AA AA AA AA AA. These continuators use a simple meta-synchronous rain speed shift temporarily crying also yftfe u. The continuity between the master device 144 and the matrix 106 is continued. For Jie 4 4, ▲ this, Ma violated the continuation and maintained a ΑΗΒ - 1 ^ 6 main device 144 and the moment Chen 1 〇 6 > called from 1: 1:: 11 _ early 6 synchronization, use A state machine focuses on the capture and reproduction of all master transmissions combined with the correct control and wait states. The state machine in the -continuator 138 will insert an automatic wait loop to read the master device 144 - directly to the connection bus 13 through the appropriate #2 from the address of the dream agency 罝 ^ ^ 罝 a correct response . These operations are explained in more detail below in conjunction with FIG. Figure 8 is a block diagram showing an exemplary embodiment 24 of one of the main serializers 126 and 138 of the present invention in an interface between a host device 144 and a matrix 〇6. In the illustrated example, the continuator 138 includes a left finite state machine (FSM) 242, two 32-bit shift registers 244 and 246, and a 130924.doc -20-200900951 16-bit shift register. 248. The FSM: controls the operation of the serializer and introduces a wait state to the master device 144. This will be explained in more detail below in conjunction with FIG. In other embodiments, other controllers than a limited core stack may also be used. The two 32-bit shift registers 244 and 246 are used to enable continuous and de-continuation of information for the address bus and data bus. The 16-bit shift register 2 is used to continualize and de-continue the control signals used in the protocol. (There is no buffer for shift register 244 (and other similar shift registers in the examples described below) because this shift register is unidirectional in the particular embodiment illustrated. Other bit width shift registers may be used in other embodiments, as appropriate. The components and operation of shift registers 244, 246, and 248 are described in greater detail in conjunction with FIG. Similarly, the contigator 126 includes a right finite state machine (FSM) 25A, two 32 bit shift registers 252 and 254, and a 16 bit shift register 256. The FSM 250 controls the operation of the continuator 126 as described in greater detail below in conjunction with FIG. The two 32-bit shift registers 252 and 254 are used to de-continue and continually decode the information for the address bus and the data bus, and the 16-bit shift register 256 is used. The continuation and continuation of the control signals used in the agreement. Other bit width shift registers may be used in other embodiments, as appropriate. The components and operations of shift registers 252, 254, and 256 are described in greater detail in conjunction with FIG. The shift register 244 is coupled to the shift buffer 252 by the address bus 260. The address bus 26 is 4 bits 130924.doc • 21 - 200900951 in the illustrated embodiment. The width may be unidirectional to allow the master device 144 to address a slave device (the master device 144 does not have to receive an address). Shift register 246 is coupled to shift register 254 by a bidirectional data bus 262 (which is 4 bits wide in the illustrated embodiment), and the shift register (10) is - Bidirectional control bus 264 (which is 2 bits wide in the illustrated embodiment) is coupled to shift temporary hack 256. In addition, a start_left_transfer signal 266 is used by the left FSM 242 to select the transmission of information from the primary device to the matrix, and the right FSM 25 uses the -start_right-transfer signal 268 to select information from the matrix to the primary device. transmission. These signals can be transmitted between the contigators via a dedicated line. The left W can also optionally set a hedge signal 269 that is transmitted back to the host device 144. | People wait for status. Continuous clock signal 124 is provided to the continuators 138 and ! 26 both to coordinate the function of their continuous communication. The use of these signals is described in more detail in conjunction with Figures 9 and 11. HCLK signals 272 and 274 are provided to the successiveizers 138 and (3), respectively, and a wafer clock (10) or wafer clock is provided for the serializers provided thereon. The HCLK_left and HCLK_dght signals can be different or the same frequency' which is determined by the desired frequency for the chip. In the specific embodiment of the description, it is considered to have the same frequency. Since the control for the shift registers is provided by the cafes 242 and 25(), the resynchronized clock HCLK is required to perform all operations. (The continuous clock manages the offset and continuous communication of the shift register, and the signals manage communication to the master device 'slave or matrix.) The frequency of the continuous clock 124 must be greater than Each of the HCLK signals is larger in order to maintain a better synchronization between the HCLK and the continuous clock domain of 130924.doc -22-200900951. 9 is a flow chart illustrating one exemplary method 3 or state of operation of the left side FSM 242 of the main continuator 138 provided on the wafer 103 of the master device 144. The left FSM 242 controls the continuation and de-continuation of the information, and also inserts an automatic wait loop, allowing the continuous program to be executed while complying with the bus protocol. The FSM controls all timings and makes

Continuous clock domain HCLK_Left information and use

"sedaljk" resynchronization. This synchronization will occur on both sides (left and right) of the continuous communication bus to provide a synchronous high speed continuous transmission. As shown in step 302, the FSM 242 waits until it appears from One of the master devices 144 is effectively transmitting. If there is no effective transmission, the fsm continues to wait. If an external source (eg, one of the controllers on the wafer resets the controller or one source outside the wafer), the decision is made against The primary system reset signal HRESETN of the master device 144 forces the FSM 242 to enter the wait state step 302. The hedge signal 269 is set high by the FSM in this state. By the HTRANS signal is not idle or busy. Indicating a valid transmission. Once this condition occurs and a valid transmission is provided from the primary device 144, the FSM proceeds to step 304 where the address and control # number from the primary device is captured. The primary device will also be targeted to the primary device. Signal 269 of i 44 is set low to introduce a wait loop for the master device 144. This HREADYk number is initiated by the FSM and simulated from a slave device or matrix. a regular HREADY signal (which causes the master to wait for the δH device to respond to a request). If the hwrite signal is low, 130924.doc -23- 200900951 the master has initiated a read operation The data signal is not transmitted, so the FSM proceeds to step 308 as explained below. If the HWRITE signal is 1 ', it is a write operation, and in step 306 the FSM captures the information information that the host device wishes to write, and then Continuing to step 308. At step 308, the FSM 242 causes the retransmission of the continuous information in accordance with the continuous clock signal 124 to be resynchronized, loading the appropriate shift register depending on the type of operation (read or write). 244, 246, and 248, and the transmission of information is initiated through appropriate busses 260, 262, and/or 264. The left FSM 242 also sets the signal 266 (start_left_transfer) high, thereby allowing the right FSM 250 to begin capturing. The incoming information is synchronized. The left FSM 242 also keeps the HREADY signal 269 low, causing the master 144 to wait, in this manner, the FSM 242 inserts an automatic wait loop. Once the offset is complete The program proceeds to step 3 10, in which the start_left_transfer signal 266 is set to zero. The FSM then waits for a response from the matrix 106 in a hold state in step 3 12 while the start_right_transfer signal 268 Zero. The right FSM sets the start_right_transfer signal 268 high when it wishes to transmit a response signal to the left FSM. When signal 268 goes high, the process continues to step 314 where the left FSM 242 offsets the continuous information received from the continuous bus into a parallel form and continues the offset until all information is received. The FSM 242 resynchronizes incoming information from the high speed shift registers with the HCLK_left clock domain. The FSM 242 also analyzes the HRESP signal from the matrix 106 to determine if the operation was successful or if an error occurred. If the HRESP signal indicates success 130924.doc -24- 200900951, the HREADY signal 269 is set high in step 316 to notify the host device 144 that the operation is complete and exit the wait cycle. The program then returns to step 302 to await another valid transmission from the primary device. If the HRESP signal indicates a fault in the received information in step 314, the situation is indicated in step 317 (eg, a standard error procedure can be initiated), and in step 318 the FSM 242 is directed to the The master device 144 issues the HREADY signal, similar to that in step 3-6, thereby causing the master device to exit the wait loop. The program then proceeds back to step 3〇2 to wait for another valid transmission from the δ 主 master. Therefore, when the continuation is in progress (e.g., steps 3〇4 to 314), j HREADYh number 269 is kept low, thereby introducing a wait state to the master device 144. After the response, the HREADY signal is issued to go high, thereby providing a response from the matrix 106 back to the host device. (If the addressed slave device requires more time to respond to the master device, the heardy signal 269 (or a separate HREADY signal) may be asserted by the addressed slave device during the request operation. The mode is implemented again to be low or to keep it low.) Figure ίο is a diagram illustrating one of the exemplary embodiments 33 of 246, 246, 248, 252, 254, and 256 of the synchronous shift registers. The synchronizer shift register of the contigs includes a flip flop array and a plurality of multiplexers to determine the flow of information therebetween. To support two-way communication, the shifts are 246, 248, 25, and 256 (not 244 and 252, as they are unidirectional in the illustrated embodiment) to support continuous information removal, continuous information shifting 130924. Doc -25- 200900951 Incoming and parallel information loading and features of the flip-flop with enable (to stop the offset) function. The FSM 242 or 250 provides all control and timing to achieve continuation and de-continuation of the AHB-Lite master information. An exemplary 32-bit shift register 33A includes a flip-flop 332 and a multiplexer 334. In the particular embodiment illustrated in the figures, the "bit shift registers 244, 246, 252, and 254 each have a tap 334 in the bits 7, 15, 23, and 31 ( That is, the f-bit position affecting the next state of the shift register is as shown in the figure. The 16-bit shift registers 248 and 256 have each of the bits 7 and 15 - Taps. Each tap in the shift register includes a bidirectional buffer 336, and a similar buffer is transmitted through one of the communication channels on the board (for an exemplary 32-bit shift register) 330, the channel 338 is shown as 4 bits) and connected to the other end of the bus (10), 262 or 264. In the example shown, since the taps are said to be in the group of 8 registers Therefore, only 8 consecutive clock cycles are needed to transmit all the tfi, and the shift to the (four)-bit register is as follows: ^The parallel bus 34 has been connected from the load in the parallel mode. 〇Loading information, all information will be removed in a continuous form in the next 8 cycles. For example, the line s bit 〇 shifts out the bit [7:0], s bit 】 remove the bit [15:8], s bit 3 moves out of the bit [23:16] and s bit 4 moves out of the bit [31:24]. For a move-in procedure, when starting to receive and capture information, the line The s-bit 〇 feeds the bit 〇 and shifts until the bit 70 7 is received, the S bit reads the bit 8 and shifts until the bit 1 is received, the 5' s bit 2 feeds the bit 16 and is offset until received The bit is supplied to the bit 23, and the s bit 3 is shifted by the bit 24 until the bit 31 is received, and the offset bit is provided on the read parallel sink 130924.doc -26·200900951 stream 3 4 2 . The 6-bit shift register operates in the same manner, except that only two s-bit lines are used. Figure 11 illustrates the FSM 250 on the right side of the main contigator 1 26 provided on the wafer 102 of the matrix 106. One of the exemplary methods 350 or one of the flow charts. The right side FS Μ 250 is a supplement to the system and controls all timing and signals that are in conversation with the matrix 106. As shown in step 352 'When the start_ieft_transfer When the signal 266 is zero, the right FSM 250 is reserved. If the HRESETN signal is determined by an external source, the action forces the FSM 250 to enter. The wait state step 352. When the FSM 250 detects that the startjeftjransfer signal 266 has been set to 1 by the left fsm 242, the FSM 250 proceeds to step 354 where the right FSM uses the shifts. The memory is moved into the received continuousd information until the offset is complete and the information is in parallel. In the next step 356, the received address and control signals are issued to the matrix 1-6. If the HWRITE signal from the matrix 106 is high, then the write operation is for one of the data, and the FSM issues the captured data to the matrix 106 in step 358 and proceeds to step 36. If the HWRITE signal from the matrix is zero, then it does not have any read operation of the data signal, and the program continues directly from step 356 to step 36. In step 360, the brain 25 is in a hold-and-go wait when the occlusion signal from the addressed peripheral device (here from the matrix (10) is zero). When the occlusion signal becomes high, the addressed peripheral device is ready to transmit its response, and the program captures the response of the slave device (via the matrix 106 for routing) in step 362. Left ^ t t ) In the next step 364, the FSM sets 130924.doc -27- 200900951 ^ start_right_transfer signal 268 to 1 to indicate to the left fsm 242 that a response is about to come and move the response back to another consecutive The coder 138 is such that the master device will receive the response. (The high HREADY signal from the matrix/slave device can also be transmitted to the serializer 138 via the continuous communication bus in the control bit, and (4) the serializer transmits the HREADY>f§ number to the master device. To indicate that the slave device is ready to transmit its response, for example, if a low HREADY signal has been previously transmitted to the master device 144 by the addressed slave device.) The program then returns to step 352 to set start_right_transfer 268 It is low and waits for another transmission (only the inserted automatic waiting loop is provided to, for example, the master device 44 on the left side of the continuous communication.) Figure 12 shows the matrix for the -AHB_Lhe master device 44 The timing diagram of one of the timings between the transmissions and the transmissions, the transmission includes the continuation of the present invention. In this figure, time u is used for the time of a standard transmission. Time t2 is the time taken to capture the continuously streamed information and transfer it to the matrix. Time t3 is the time t4 at which the continuous information is restored and the operation is repeated on the matrix side to transmit and recover the response from the matrix to the host device. Time t5 is used to reproduce the time of the response to be submitted to the host device. During the time t6, the time of waiting for the loop can be automatically inserted. The number of automatic insertion wait cycles depends on the ratio of the continuous clock 124 to the HCLKk numbers 272 and 274 (HCLK_Jeft and CLK-right are assumed to be the same frequency in the examples described herein). As the ratio increases, the number of wait cycles required decreases. Figure I3A illustrates a standard AHB slave device 16 and its interface block 130924.doc -28. 200900951. In the example of Fig. i3A, a gamma juror is displayed as a slave device 16. The master 16 responds to the transmission initiated by the bus connection to the AHB matrix 12. The interface required by the slave device 16 includes control signals 382 provided from the thin-(four) bus bar 32, which are produced by the matrix following the fiber protocol, which differs from the wrap-around timing. The __hsel signal is used by the slave device 16 as a -select signal to determine when it should respond to the bus transmission. The

The AHB Lite slave device 16 provides an output signal 384 back to the AHRite busbar where it is provided to the AHB matrix 12. Figure 13B is a timing diagram showing the timing of a signal for a basic transmission of the slave device 16. Figure 14 is a block diagram showing a standard wafer layout 390 of one of the ahb slave devices in one of the prior art. In a development board state, a first wafer 392 includes an AHB matrix 12 and is The arm communication arm processing 393. A second wafer 394 includes a number of AHB_Ute slave devices 396. As shown, the prior art configuration requires 109 communication lines in each ahb bus bar 46 (excluding 1111 £1) And a single AHB slave device connected between the wafer 392 and the wafer 394. If a plurality of slave devices are connected in this manner (as shown and generally in practice), then the required The total number of communication lines is greatly increased, thereby increasing the complexity and cost of the sc. Figure 15 is a block diagram of a wafer layout system 400 for an inter-wafer ahb slave device in one of the embodiments of the present invention. The wafer layout system can be provided on a board 4 or 2 or other suitable substrate or platform. 130924.doc -29- 200900951 The board 402 includes a first wafer 102 and a first communication with the first wafer 1 — wafer 1〇 3. The first wafer 1〇2 includes The processor 1〇4 and the matrix. The processor 1〇4 can be coupled to any suitable controller as illustrated in Figure 3. The processor 104 is coupled to a matrix 106, which is connected to the slave device of the system. Master device (as explained above) allowing the AHB_Lite& devices to communicate with one or more master devices in the system. The matrix 产生 can generate a selection signal for the slave device and select which signals from the device are transmitted to the The master device, and also the option to transfer to a slave device. According to the present invention, each bus bar system provided via the matrix 1〇6 is connected to a text continuity device (SS) 128, which is intended to be Connected to a slave device provided on a different wafer. As explained above, the slave continuator relays information transmitted off the wafer or continually decomposes information received from a different wafer, as appropriate. 3 is also provided on the board 4〇2 and includes a plurality of slave devices 146 for use in conjunction with the busbar architecture and the matrix 106 of the wafers 12. The slave device 146 may be an additional slave device as shown in Figure 3 above. Or the system The required slave device 'as appropriate. Each slave device 146 has a busbar 14 to be connected to another U 1 〇 2 7 ° In the system of the invention, each bus system is connected to a slave continuator 4〇 (which is similar to the slave continuator 128 provided on the wafer 102). Each—from the continuator (4) is coupled to the associated slave continuator 128 by a communication busbar U4. In the example shown, 'because of the continuation', therefore only 12 lines are required per busbar, which significantly reduces the required busbars compared to other systems and methods. In the particular embodiment illustrated, certain communication channels of the communication channels are bidirectional, while = 130924.doc • 30-200900951 this allows the number of lines between the wafers 102 and 103 to be minimized. The method of the present invention is based on capturing signals that are desired to be transmitted to the AHB slave device and inserting a wait state to comply with the AHB protocol until the signals are received by the slave device 146 at the other end. An appropriate response is then sent from the slave device to send back an answer. The continuators use a fully synchronous high speed shift register to synchronize the information between the slave device 46 and the matrix 〇6. To achieve this continuation and maintain synchronization between the AHB slave and the matrix, a blame is used to focus on the capture and replay of all slave communications in conjunction with the correct control and wait states. This operation will be described in more detail below with reference to the drawings. Figure 16 illustrates the continuation of the present invention in an interface between the AHB slave device 146 and the matrix 〇6!!] 28 and 14() - A block diagram of an exemplary embodiment 410. In the illustrated example, the continuator 128 includes a left finite state machine (FSMM 12, a solid 32 bit shift register, and a 16 bit shift). Bit register 418. The FSM 412 controls the operation of the continuator and introduces a wait state to the matrix 106. This is described in more detail below in connection with Figure 17. In other embodiments, one may be used. Other control (four) devices of the finite state machine. The solid 32-bit shift registers 414 and 416 are used to continuously and de-continuate the information for the address bus and the data bus. The bit shift register 418 is used to continue and de-continue the control signals used in the protocol. Other bit width shift registers may be used in other embodiments, as appropriate. Similarly, the continuator 140 includes a right finite state machine (FSM) 422, Two 32-bit shift registers 424 and 420 and a 1-bit shift register 130924.doc -31 - 200900951 428. The FSM 422 controls the serializer as described in more detail below in connection with FIG. Operation of 140. The two 32-bit shift registers 4^4 and 426 are used to de-continue and continually decode information for the address bus and data bus, and the 16-bit shift The register 428 is used to de-continue and continually control the control signals used in the protocol. The synchronous shift register of the serializer includes a flip-flop array and a plurality of multiplexers to determine a stream of bellows between them, and a buffer on the busbars. Specific embodiments of the shift shift registers of the shift registers 414, 416, 418, 424, 426, and 428 include Components and operations similar to those of the shift registers 244, 246, 248, 252, 254, and 256 described above with reference to Figures 8 and 3. There are no outputs and inputs provided to the registers 414 and 424. The upper buffer, because the registers are unidirectional 0 shift register 414 in the illustrated embodiment. Address bus 432 is coupled to shift register 424, which is 4 bits wide in the illustrated example and may be unidirectional to allow the matrix 106 to address the slave device M6 (the slave device does not have to The transfer register 416 is coupled to the shift register 426 by a bidirectional data bus 434 (which is 4 bits wide in the illustrated example), and the shift register 41 8 It is coupled to shift register 428 by a bidirectional control bus 436 (which is 2 bits wide in the illustrated example). The left side fsm uses a start-left-transfer signal 438 to select from matrix to slave. The transmission of information from one of the devices, and the right-side FSM 422 uses the -start-right-transfer signal 44〇 to select the transmission of information from the slave to the matrix. This equalization can be transmitted between the continuators via a dedicated line 130924.doc 32· 200900951 a. The continuous clock signal i 24 is provided to the continuators i28 and 14 以 to coordinate the function of its continuous communication. The left FSM 4 丨 2 can also selectively transmit δ to the matrix 1 〇. The Havey signal 439 of 6 introduces a wait state. The use of such signals is described in more detail in conjunction with Figures 17 and 18.

HCLK signals 442 and 444 are provided to the successiveizers 128 and 140', respectively, and provide wafer clocks for wafers 1 and 2 on which the successiveizers are provided. Since the control for the shift registers is provided by the FSMs 412 and 422, the resynchronized clock hclK is required to perform all operations. The frequency of the continuous clock 124 must be greater than each of the HCLK signals to maintain better synchronization between the HCLK and the continuous clock domain. Figure 17 is a flow diagram illustrating one exemplary method 450 or state of operation of the FSM 412 from the left side of the continuator 128 provided on the wafer 〇2 of the matrix ι6. The left FSM 412 controls and synchronizes all incoming information from the AHB bus and inserts an automatic wait state such that the AHB agreement is not corrupted while the continuation program is in progress. The left FSM 412 controls all timing and causes the information passed in from HCLK_left to be resynchronized with the domain of the continuous clock 124. This allows both sides (left and right) to have a synchronous high speed continuous transfer. At step 452, the left FSM 412 is idle, waiting for transmission from one of the matrices 106. The HREADY signal is set to high in this state. If the reset signal HRESETN is asserted by an external source (e.g., a controller on the wafer or a source external to the wafer), then the FSM 412 is forced into the idle state 452. Once the HSEL letter 130924.doc -33 - 200900951 is determined to be 1 (this selection of the slave device 146 for transmission by a master device), then the process continues to step 454 where the FSM 412 capture is from The address and control information of the matrix. The HREADY signal 43 9 (starting by the FSM) transmitted to the matrix 1 〇 6 is also set low to introduce an automatic wait loop into the matrix. If the HWRITE signal is set high, it is a write operation and the process continues to step 456 to capture the data signal from the matrix. If HWRITE is low, it is a read operation and does not capture any data signals from the matrix, and the process continues from step 454 to 'step 45 8'. At step 458, the FSM 412 causes the retransformation of the continuous clock signal 124 to be reloaded 'loaded into the appropriate shift registers 414, 416, and 418 and the information is shifted out to the appropriate continuous stream in a continuous form. Another continuator 14 上 on rows 432, 434, and 436. The left FSM 412 also sets the start-left-transfer signal 43 8 high, thereby allowing the right FSM 422 to begin capturing synchronized incoming incoming information. The left FSM 412 I also keeps the hready signal low, thereby causing an automatic wait loop to be inserted into the matrix 106. When the removal is completed, the program proceeds to step 46, in which the start_left_transfer signal 43 8 is set to zero. In step 462 _, the FSM 412 waits for a response from the slave device and the right side, and the right setting start-dghtjransfer will indicate the response as 丨, thereby indicating that the right side of the side wishes to transmit a slave device response back to the FSM 412 on the left. Once this occurs, the program proceeds to step 464 where the FSM 4丨2 moves the continuous information received from the continuous bus into the form of parallel 130924.doc 34-200900951 and continues the offset. To receive all the information. The fsm 4i2 resynchronizes the pass-through information from the high-speed shift registers with the hclk-(iv) clock domain. The FSM 412 also analyzes the HRESP signal from the slave device 146 to determine if the operation was successful or not - an error. If the HRESP signal indicates successful transmission of information, then the HREADY number 439 s is exempted high in step 466 to notify the matrix i 〇 6 that the operation is complete and exit the wait loop. The program then returns to step 302 to wait for another valid transmission from the matrix. If the HRESP signal indicates in step 464 that one of the received messages indicates the situation in v 468 (the routine can be initiated, the error procedure can be initiated) and the FSM 412 proceeds in step 470. The master device 144 issues the HREADY number, similar to that in step 316, thereby causing the master device to exit the wait loop. The program then proceeds back to step 452 to wait for another valid transmission from the matrix. Thus, while the continuation is in progress (e.g., steps 454 through 464), the left FSM 412 to the matrix 1 〇 6i HREADY signal 439 remain low' thereby introducing the -wait state to the matrix 1G6. After this response, the HREADY signal is sent high, providing the answer from the slave to the matrix. (If the addressed slave device requires more time to respond to the master device' then the hrEADY signal 439 may be asserted by the addressed slave device during the request operation (or - separate tear-off signal 'premise (4) Implementation) set again to low or hold the money low.). . Figure 18 is a flow diagram showing one of the exemplary methods 48 924.doc - 35 - 200900951 of the operation of the side FSM 422 from the continuous time 140 provided on the wafer 1G3 of the slave device 146. The right FSM 422 is complementary to the system and controls all timing and signals to talk to the slave device 146. The operating system is similar to the operation of the right side FSM 126 described above with reference to FIG. As shown in step 482, the FSM 442 waits until the start_left_transfer signal 440 is one. The HRESETN signal also forces the FSM 442 to enter the wait state step 482. When the start_left_transfer signal is set to 1 by the left FSM 412, the right FSM 422 proceeds to step 484, in which the FSM 422 uses the shift temporary / '« ' registers to move from the continuous bus. The information has been continuous until the completion and the information is in parallel. In the next step 486, the received address and control signals are issued to the slave. If the HWRITE signal from the slave device 146 is high, the ij has a write operation to the data, and the FSM 422 issues the data signal to the slave device 146 in step 488, and the process continues to step 490. . If the HWRITE signal from the slave device is zero, then it does not have any read operation of any of the data signals, and the process proceeds directly from step 486 to step 490. In step 490, the FSM 422 waits in a hold state when the HREADY signal from the slave device is zero. When the HREADY signal goes high, the slave device is ready to transmit its response, and the program captures the response from the slave device in step 492. In a next step 494, the FSM 422 sets the start_right_transfer signal 438 to 1 to indicate that a response from one of the slaves is imminent, and moves the response back to another contigator 128 such that the matrix will receive the Respond (and then transfer it to the originating host). The program then returns to step 482 to set start_right_transfer 130924.doc -36 - 200900951 low and wait for another transmission. (Similar to the above diagram, the high HREADY signal from the slave device is also transmitted to the continuator U8 through the continuous communication busbar in the control bits, and the continuator 128 The HREADY signal is also transmitted to the matrix and the master device is instructed to indicate that the slave device is ready to transmit its response.) Figure 19 is a timing diagram 496 showing a timing for a transmission between the matrix 〇6 and an AHB_Ute slave device 146. The transmission includes the continuation of the present invention. In this figure, time U is used for the time of a standard double loop transmission. Time t2 is the time taken to capture the continuously streamed information and transmit it to the slave device. Time t3 is the time to recover continuous information and provide it to the slave device by appropriate transmission. Time 14 is used to receive the time the slave responds and transmits it back to another chip in continuous mode. Time t5 is used to reproduce the response from the slave device and give it to the matrix in the other-continuator. The time to wait for the loop is automatically inserted during time 16 series. The number of automatically inserted wait cycles depends on the ratio of the continuous clock 124 to the HCLK signals 442 and 444. As the ratio increases, the number of waiting cycles decreases. Figure 20A illustrates a block diagram of a standard APB slave device and its interface. The APB slave device 2G responds to the originator from the _master device by means of a ΑΗΒ/ΑΡΒ bridge connected to the ahb matrix ^||! The interface required by the slave device 20 includes a control signal 5 提供 provided from the ΑΗΒ/ΑΡΒ bridge 18 by the Β Β bus bar, and the control device number 5 is controlled by the bridge 18 The ΑΗβ protocol timing is generated, and the port differs from the 130924.doc 37·200900951 AHB protocol timing by the slave device 20 as a selection signal to determine when it should respond to a bus transmission with a PSEL signal 502. The APB slave device 2 provides an output signal 5 〇 4 (HRdata) back to the APB bus bar, which is provided to the AHB/ApB bridge 18 at the APB bus bar. 20B and 20C are timing diagrams 506 and 508 showing timing for a basic transfer of the ApB slave device 2, wherein the timing chart 5〇6 shows the timing for a write transfer, and the timing chart is shown in FIG. Displays the timing for a read transfer. Figure 21 is a block diagram showing a standard wafer layout 510 for an ApB slave device in one of the prior art s〇c. A first-wafer 512 includes an AHB matrix 12, one of which can communicate with the matrix, an ARM processor 393, and one of the interfaces between the AHB and the APB-associated peripheral device, the AHB/ApB bridge state 18. A second wafer 514 includes a number of ApB slave devices 516. As shown, a prior art configuration requires 99 communication lines (excluding PRESETN and PCLK signals) in each bus 48 to connect a single APB slave between wafer 512 and wafer 514. If a plurality of APB slave devices are connected in this manner (as shown and generally in practice), the total number of communication lines required is greatly increased, thereby increasing the complexity and cost of the s〇c. Figure 22 is a block diagram of an exemplary aa slice layout system 520 for an inter-wafer slave device in one of the present inventions, wherein the slave device is used in accordance with one of the different matrices of the muscle busbar system. For example, the wafer layout system 52 can be provided on a board 522 or other suitable substrate or platform. The board 522 includes a first wafer 102 and a second wafer 103 in communication with the first wafer 102. The first wafer 〇2 includes a processor 〇4, an ahb matrix 1〇6 130924.doc-38-200900951, and an enhanced AHB/APB bridge. Processor 1〇4 can be any suitable controller as described above in connection with FIG. The processor 104 is coupled to a matrix 106 which is coupled to the slave and master of the system (as described above). The APB slave devices are allowed to communicate with - or a plurality of master devices in the system. The matrix (10) can generate a selection signal for the slave device and select which inputs from the device to transmit to a master device in the future, and also select information to be transmitted to a slave device. The AHB/APB bridge 116 interfaces the ApB peripheral device (e.g., the APB slave device of the present embodiment) with the AHB matrix 1〇6. The ΑΜΒΑ·ΑρΒ agreement does not specify a wait loop in the bus, but if the continuous clock is not fast enough to complete a transmission in a single PCLK cycle, then a wait loop is required for proper continuation in the present invention. Therefore, the (four) connector is boosted to allow the continuator to stop the bus transmissions, with the result that the ΑΗΒ/ΑΡΒ bridge n 116 is allowed to wait for a loop in the ΒρΒ bus transmission. Other embodiments may use different types of bridges to interface a peripheral device using a protocol with a matrix using a different protocol. In accordance with the present invention, each busbar provided via the bridge 116 is coupled to a slave continuator 13 that is to be connected to a slave device provided on a different wafer. The VIII>3 continually streams information transmitted from the wafer from the continuator 13 or decompresses information received from a different wafer, as appropriate. The wafer 103 is also provided on the board 52 and includes a plurality of slave devices 148 for use in conjunction with the bus bar architecture of the wafer. The slave device 148 may be an additional slave device as shown in Figure 3 above, or a slave device as required by the system, as appropriate, 130724.doc -39-200900951. Each APB slave device 148 has a busbar 149 to be connected to another wafer 102. In the system of the present invention, each bus bar 149 is coupled to an APB slave continuator 42 (which is similar to the slave continuator 13 provided on wafer 102). Each APB is coupled from the continuator 142 to a associated APB slave continuator 130 via a bus 136. In the illustrated example, 'continuation' therefore requires only 11 lines per busbar', which significantly reduces the required busbars compared to other systems and methods. In the illustrated embodiment, certain communication channels of the communication channels are bidirectional, thus allowing the number of lines between the wafers 102 and 103 to be minimized. The method of the present invention is based on capturing an APB slave device signal from the AHB/APB bridge and inserting an automatic wait state to comply with the APB protocol and allowing the continuation procedure to complete transmissions to a particular slave device. The continuator method allows the use of a simple fully synchronous high speed shift register to continually synchronize the information between the device 148 and the bridge 116 to reduce the number of signals required across the board. grade. To achieve continuation, a state machine is used to provide the control and the APB protocol. These operations are explained in more detail below in conjunction with FIG. Figure 23 is a block diagram showing an exemplary embodiment 530 of the present invention from continuators no and 142 in an interface between device 148 and enhanced AHB/APB bridge 116. In the illustrated example, the continuator 130 includes a left finite state machine (FSM) 532, two 32-bit shift registers 534 and 536, and an 8-bit shift register 538. The left FSM 532 controls the operation of the continuator and introduces a wait state into the bridge 130924.doc • 40- 200900951 t§ 116. This will be explained in more detail below in conjunction with FIG. In other embodiments, other controllers than the finite state machine may also be used. The two 32-bit shift registers 5 3 4 and 5 3 6 are used to continuously and de-continuate information for the address bus and data bus. The 8-bit shift temporary state 538 is used to continuously/de-continue the control signals used in the protocol. Other bit width shift registers may be used in other embodiments, as appropriate. Similarly, the contigator 142 includes a right finite state machine (FSM) 54A, two 32-bit shift registers 542 and M4, and an 8-bit shift register 546. As explained in more detail below in connection with Figure 27, the fsm controls the operation of the continuator I42. The two 32-bit shift registers 542 and 54 are used to de-continuation and continuity of information for the address bus and the data bus, and the 8-bit shift register 546 is Used to de-continue and continually control the control signals used in the protocol. The synchronizer shift register of the serializer includes a flip-flop array and a plurality of multiplexers to determine the flow of information between them, and a buffer on the bus bars. One embodiment of the synchronous shift registers of the shift registers 534, 536, 542, and 544 includes shift registers 244, 246, 252, 254, respectively, as described above with reference to FIG. Operate similar components and operations. The 8-bit registers 538 and 546 operate in a similar manner, except that they use only one s bit line. There are no buffers provided on the outputs and inputs of registers 534 and 542, as such registers are unidirectional in the particular embodiment illustrated. The shift register 534 is coupled to the shift register 542 by an address bus 550. The address bus 550 is 4 bits wide in the illustrated example and can be 130924.doc -41 · 200900951 One way to allow the bridge u6 to address the APB slave device 148 (the APB slave device I48 does not have to transmit the address). The shift register 536 is coupled to the shift register 544 by a bidirectional data bus 552 (which is 4 bits wide in the illustrated example), and the shift register 538 is controlled by a bidirectional control. Bus bar 554, which is one bit wide in the illustrated example, is coupled to shift register 546. A start Jeft-transfer signal 556 is used by the left side FSM 532 to select the transmission of information from the bridge to the APB slave device, and the right side fsm 54〇 makes /: use a Start_right_transfer signal 558 to select the slave from the ApB slave device. The transmission of information to one of the bridges. These signals can be transmitted between the serializers via dedicated lines. A wait signal from the continuator 13() to the bridge ι6 is used to introduce a wait loop for the bridge 116. The continuous clock signal 124 is provided to both of the successiveizers 13G and 142 to coordinate the function of its continuous communication. The use of such signals is described in more detail in connection with Figures 24, 26 and 27. PCLK signals 560 and 562 are provided to the successive 142s, respectively, and provide a bus schedule for the wafer on which the contigs are provided. Here, the PCLK (five) PCLK-right signals are assumed to be the same frequency, but in other embodiments, different frequencies may be used. Since the control for the shift registers is provided by the equal FSMs 532 and 540, the smog tongues are resynchronized with the clock PCL] to perform all operations. The frequency of the continuous clock 124 must be greater than each of the signals of the pcu signals to maintain better synchronization between the HCUC and the continuous clock domain translator. Figure 24 is a flow diagram illustrating an exemplary method 570 or state of operation of the FSM 532 from the left side of the continuous interface 130924.doc • 42-200900951 130 provided on the wafer (10) of the bridge 116. The FSM 532 controls and synchronizes all incoming information from the enhanced AHB/APB bridge 116 and transmits a wait signal back to the bridge to insert a wait loop and allow the continuation procedure to be performed. The left FSM 532 controls all timings and re-synchronizes the incoming traffic from pcLK_left with the domain of the continuous clock 124. This allows both sides (left and right) to have a synchronous high speed continuous transmission. At step 572, the left FSM 532 is idle, waiting for transmission from one of the bridges 116. The wait signal 563 is set to zero in this state. If the PRESETN signal is asserted by an external source (e.g., a controller on the wafer or a source external to the wafer), then the FSM 532 is forced to enter the idle state 572. Once the pSEL signal is asserted to one (this selection of the APB slave device for transmission from one of the bridges), the process continues to step 574 where the FSM 532 captures the bit from the bridge 116. Address and control information. The wait signal is also set to ! to introduce an automatic wait loop. If the PWRITE signal is set high, it is a write operation and the process continues to step 576 to capture the negative number from the indirect 116 and continue to step 578. If pwrite is low then it is a read operation without capturing any data signals from the bridge, and the process continues from step 574 to step 578. At step 578, the FSM 532 causes the synchronization of the continuous clock signal 124 to be resynchronized, loads the appropriate shift registers 534, 536, and 538 and moves the information out in a continuous form to the appropriate continuous stream. Another continuousizer 142 on rows 550, 552, and 554. The left FSM 532 is also 130924.doc -43- 200900951 sets the stan-left-transfer signal 556 high, thereby allowing the right FSM 540 to begin capturing synchronized incoming incoming information. The wait signal 563 is maintained to 'allowing the enhanced bridge 1 丨 6 to insert the automatic Ahb wait loop. When the removal is complete, the program is in step 58, in which the stan_left-transfer signal 5S6 is set to zero. If the PWRITE signal is detected to be zero, it is a write operation and no data from the slave device is expected, and the program returns to step 572 to cause the FSM 532 to enter an idle state and wait for the signal. 563 is set to zero. If the number is non-zero, it is a read operation, and in step 582, the fsm waits for a response from the right side, and the right side set staruight_transfer will indicate this response as 1. Once this happens, the program proceeds to step 584 where the left FSM 532 resynchronizes the information received from the continuous bus and moves it into a parallel form, and continues the offset - straight To receive all the information. The FSM 532

The incoming information of the shift register is re-converted with the PCLK-left clock domain. In step 586, the received information is transmitted to the enhanced bridge 116 and the wait signal is set to zero. The program then returns to step ^ to wait for another operation from the bridge 116. Thus, while the continuation is in progress (e.g., steps 574 through 586), the wait signal from the enhanced bridge m remains low, thereby introducing an APB wait state. After the left FSM 532 issues the wait signal, the bridge 116 transmits an answer from the APB from the device back to the bridge 116. 130924.doc -44- 200900951 Figure 25 is a flow diagram illustrating one of the standard finite state machines included in one of the prior art AHB/APB bridges 18. In a step 592, the bridge FSM is in an interposed state in which the PSEL and PENABLE signals are zero. When a transmission occurs, the set state 594 sets the PSEL signal high to select the addressed slave device to respond. In the next enabled state 596, PENABLE is set high to enable the slave device for communication, and then communication can occur. If there is another transmission, the FSM returns to state 594, and if there are no transmissions, the FSM returns to state 592. The standard specifications for the AHB/APB bridge include support for the AHB side of the bridge, but does not include support for the waiting loop on the APB side. Figure 26 is a flow diagram illustrating one of the methods 600 or states for operation of the enhanced AHB/APB bridge 116 of the present invention. The enhancement of the bridge 116 allows the APB to be continued, as explained above. The enhancement includes an additional state in one of the AHB/APB active peripheral bus machines. In a step 602, the active peripheral busbar of the bridge 116 is in an idle state, and the PSEL and PENABLE signals are set low. This idle state continues when no transmission is received by the bridge. When a transmission is received, the setting step 604 is executed to set the PSEL signal to 1 to select the addressed slave device. In the enable step 606, PENABLE is set high to enable the slave device for communication and then begins. The wait step 608 of the present invention causes the machine of the bridge 116 to wait (as indicated by the wait signal 563 from the left FSM 532 in the continuator) 'to continue communication to the slave during this wait time 130924 .doc •45- 200900951 and transmitted, and any response is continually returned. After the wait signal 563 is asserted high by the left FSM, when the continuous communication completes the day, the machine returns to the step if another transmission is received, or returns to step 6 if no additional transmission occurs. 2. Figure 27 is a flow diagram illustrating one exemplary method 62 or state of operation of the right FSM 540 of the ApB 攸 Continuator 142 provided on the wafer 1 〇 3 of the APB slave device 148. The right FSM 54 is complementary to the system and controls all timing and signals to talk to the APB slave 148. As shown in step 622, the FSM 54 一直 waits until the start_left_transferk number 556 is -. (The presetn signal forces the FSM 540 to enter the idle state step 622.) When the start-left-transfer signal is set to ??? by the left FSM 532, the right fsm 540 proceeds to step 624 where the FSM is 540 moves the continuous information up to the element 'to provide the information in parallel. In the next step 626, the parallel address and control information is issued to the APB slave. If the PWRITE signal from the bridge 116 is high and the write-write operation, the FSM 540 also issues the received profile information to the APB slave device 148 in step 628 and the program returns to step 622 to Like 1'1: -1^1^ - plus 1^6]: Signal 5 58 is set low and enters an idle state (because it is expected that no APB will respond to the device for a write operation). If the PWRITE signal from the slave device is zero, then there is no read operation for any of the data information, and the program continues from step 626 to step 630. In step 630, the program waits as needed and captures the APB slave response. In the next step 632, the FSM 540 sets the 130924.doc -46-200900951 start-nght-transfer signal to $i, and moves back and forth through the communication bus and shifts from the response to another-continuous The coder is such that the bridge 116 will receive the response. The program then returns to the step milk to set the start_right_transfer signal low and wait for another transmission. Figure 28A shows a timing diagram for the timing of the read-to-read transfer between the enhanced bridge (1) and the ApB slave peripheral 148, including the continuation of the present invention. In this figure, 胄mi is used for the time of the standard-fetch transmission. The daytime t2 is used to capture the continuous information and transmit it to the APB slave device. The daytime (10) is used to restore continuous information and at the time when the operation is performed. The time m4 is used to recover the response information and transmit it back to the enhanced bridge 116. The time of the wait loop can be automatically inserted. The number of wait cycles for automatic insertion depends on the ratio of the continuous clock 124 to the HCLK signals 560 and 562. As the ratio increases, the number of wait cycles decreases. In the timing diagram (4) of the timing of the transfer between the enhanced bridge 116 and the APB from the peripheral device H8, the transmission includes the continuation of the present invention. In the figure, the inter-turn u is used for A standard write transfer time. Time t2 is used to capture the continuously streamed information and transmit it to the APB slave device. The Japanese temple system is used to restore the continuous information on the other chip and at the APB. Figure 29 is a block diagram of a different embodiment 650 of the multi-chip busbar architecture system of the present invention. The system 65 includes four different wafers, namely, wafers 652, 654, 656 and 658. The additional master of the system is deployed on the plurality of wafers from the device 130924.doc -47.200900951. Due to the nature of the continuators, the system can be divided into several clock domains. The AHB clock HCLK on the chip is independent of the HCLK signal on other wafers of the system. Because of &, there is no need to balance all HCLK signals, and the frequency does not need to be mutually compatible. The main requirement is the continuous time. Pulse: This should be balanced between two continuators at the end of the -communication busbar. In the specific embodiment illustrated in Figure 29, one. Eight old hills + related 'and continuous clocks 660, 662 And 664 are also mutually unrelated. For example, continuous clock 660 may differ from continuous clock 662 and continuous clock 664. However, 'every-continuous clock system is balanced between its own continuators; otherwise, the continuous communication The information may be lost and the information may be lost. The present invention has been described in terms of the specific embodiments shown, but those skilled in the art will readily appreciate that there may be modifications to the specific embodiments, and the changes will In the spirit and scope of the present invention, many modifications may be made by those skilled in the art without departing from the spirit of the scope of the accompanying claims. [Fig. 1 is a prior art - standard system single chip and s stream FIG. 2 is a block diagram of a multi-wafer system of the prior art. FIG. 3 is a block diagram of a multi-wafer system of the present invention; FIG. 4 is a diagram showing a continuous system of the present invention. Figure 5A is a block diagram of a standard prior art AHB master device and its interface, and is shown in Figure 5A. A timing diagram of the timing of the signal; FIG. 6 is a block diagram showing one of the standard wafer layouts of the ahb master device in one of the prior art; FIG. 7 is directed to the _S(C) in the present invention. a block diagram of the wafer layout system in the middle of the wafer;

Figure 8 is a block diagram showing an exemplary embodiment of the main continuator of the present invention in the interface between the main device and the matrix; X Figure 9 is a diagram illustrating the main on the wafer of the main device One of the exemplary methods or states of operation of the left finite state machine of the continuator; FIG. 10 is a schematic diagram of one exemplary embodiment of a synchronous shift register of the continuator; FIG. A flowchart of one exemplary method or state of operation of a right finite state machine of a primary continuator on a wafer of the matrix; FIG. 12 is a diagram showing transmission between the master device and the matrix a timing diagram of timing, the transmission including the continuity of the present invention; FIG. 13A is a block diagram of a standard AHB slave device and its interface; FIG. 13B is a timing diagram of a standard entanglement device and its interface; 14 is a block diagram of a standard wafer layout for one of the fine-grain devices of the prior art-standard SqC towel; FIG. 15 is a wafer layout system for a ahb slave device between day and day in the SqC of the present invention. One square Figure 16 is a block diagram of an exemplary embodiment of the present invention from the interface between the _AHB slave device and the matrix. Figure η is a diagram One of the exemplary methods or states of operation of the finite state machine from the left side of the continuator on the wafer of the matrix; FIG. 18 is a diagram illustrating the finite state from the right side of the continuator on the wafer of the slave device Operation of the machine - an exemplary method or state - a flow chart; Figure 19 is a timing diagram showing the timing of a transmission between the matrix and an AHB slave device. The transmission includes the continuation of the present invention;

Figure 20A is a block diagram of a standard APB slave device and its interface; Figure 20B is a timing diagram illustrating a standard ApB slave device and its interface for a write transfer; ^ Figure 20C is a diagram for reading A timing diagram of a standard ApB slave device and its interface is taken; FIG. 21 is a block diagram showing one of the standard wafer layouts of the slave device in one of the prior art SoCs; FIG. 22 is directed to the present invention. The inter-wafer slave device in the SqC - the exemplary wafer layout system - the block device, the slave device uses one of the different matrices from the busbar system; Figure 23 illustrates an APB slave device and enhanced A block diagram of an exemplary embodiment of a continuousizer of the present invention in an interface between ahB/APb bridges; FIG. 24 is a diagram of a slave continuator on a wafer of the enhanced bridge One of the exemplary methods or states of operation of the left finite state machine; FIG. 25 is a flowchart illustrating one of the 130924.doc -50-200900951 standard finite state machines included in one of the prior art ahb/APB bridges. Figure; Figure 26 A flowchart illustrating one of the methods or states for operation of the enhanced AHB/APB bridge of the present invention; FIG. 27 is a diagram illustrating the APB provided on the wafer of the APB slave device from the right finite state machine of the continuator One of the exemplary methods or states of operation is a flowchart; FIG. 28A is a timing diagram showing timing for a read transfer between the enhanced bridge and the APB slave, the transmission including the continuation of the present invention Figure 28B is a timing diagram showing timing for a write transfer between the enhanced bridge and the APB slave device, the transfer including the continuation of the present invention; and Figure 29 illustrates one of the present inventions A block diagram of one of the different embodiments of the multi-chip busbar architecture system. [Main component symbol description] 10 AMBA system 12 AHB matrix 14 AHB-Lite master device / AHB master device 16 AHB-Lite slave device / AHB slave device 18 AHB / APB bridge 20 APB slave device 40 AMBA bus bar system 42 Wafer 44 Wafer 130924.doc -51 - 200900951 46 AHB busbar 48 APB busbar 100 Multi-chip system single-chip (SoC) 102-one-wafer 103 second wafer 104 processor 106 matrix 110 AHB master 112 AHB busbar 114 AHB slave Device 116 AHB/APB Bridge 118 APB Slave 120 APB Bus 124 Continuous Clock/Continuous Clock Signal 126 Main Continuator (MS) 128 From Continuator (SS) 130 APB From Continuator (APBS) 132 Busbar 134 Busbar 136 Busbar 138 Main Continuator 140 From Continuator 142 From Continuator 144 Additional AHB Master/AHB-Lite Master 130924.doc -52- 200900951 145 Bus 146 Additional AHB From Device/AHB-Lite Slave 147 Busbar 148 Additional APB Slave/APB from Peripheral Equipment 149 Busbar 150 Continuator System 152 Continuator 154 Continuator 156 Communication sink Row 158 "Continuous Front" " AHB or APB Busbar 160 Finite State Machine (FSM) Control Block 162 Shifter 164 Bidirectional I/O Block 166 Bidirectional I/O Block 168 Shifter 170 FSM Control / FSM Control Block 180 HCLK signal 182 HRESETN signal 184 signal 186 input signal 200 standard wafer layout 202 弟 · one wafer 204 second wafer 206 AHB and APB peripheral device 130924.doc -53- 200900951 208 AHB master device 220 wafer layout system 222 board 228 AHB and APB Peripherals 242 Left Finite State Machine (FSM) 244 32 Bit Shift Register 246 32 Bit Shift Register 248 16 Bit Shift Register 250 Right Finite State Machine (FSM) 252 32-bit shift register 254 32-bit shift register 256 16-bit shift register 260 address bus 262 bidirectional data bus 264 bidirectional control bus 266 start_left_transfer signal 268 start_right__transfer signal 269 HREADY signal 272 HCLK Signal 274 HCLK Signal 330 Exemplary 32-Bit Shift Register 332 Forward/Reactor 334 Multiplexer/Match 336 Bidirectional Buffer 130924.doc -54- 200900951 338 340 372 370 392 382 384 400 402 412 414 416 418 422 424 426 428 432 434 Channel parallel bus parallel bus timing diagram HSEL signal control signal output signal timing diagram Standard wafer layout First chip ARM processing弟弟二芯片DRAMLayout 左侧 Board left finite state machine (FSM) 32-bit shift register 32-bit shift register 16-bit shift register right finite state machine (FSM) 32-bit Shift register 32-bit shift register 16-bit shift register address bus two-way data bus 130924.doc -55- 200900951 436 438 439 440 442 444 496 500 502 504 506 508 510 512 514 516 520 522 532 534 536 538 540 542 I30924.doc bidirectional control bus start_left_transfer signal HREADY signal start_right_transfer signal HCLK signal HCLK signal timing diagram control signal PSEL signal output signal timing diagram timing diagram standard wafer layout first wafer second wafer APB slave Device wafer layout system board left finite state machine (FSM) 32-bit shift register 32-bit shift register 8-bit Shift register right finite state machine (FSM) 32-bit shift register -56- 200900951 544 546 550 552 554 556 558 560 562 563 640 642 650 654 654 658 660 660 662 664 32-bit shift temporary Byte 8-bit shift register address bus two-way data bus two-way control bus start-left one transfer signal start_right_transfer signal PCLK signal PCLK signal wait signal timing diagram timing diagram system wafer wafer wafer wafer continuous clock continuous time Pulse continuous clock 130924.doc -57-

Claims (1)

200900951 Patent application scope: 1. A system comprising busbar communication, the system comprising: - a matrix 'which is operable to select a destination for information on a busbar connected to the matrix; - a - contigator, The system is coupled to the matrix and provided on a first device, the first-continuator is operable to continuously feed the received data from the matrix through a 1 焉〆 确 、, 古 4彳5 busbar for transmitting the continuously streamed information; and '-a second continuator, which is provided on the second device and engaged to the communication busbar', the second continuator is operable to Receiving the continuously streamed information and de-continuing the continuously streamed information, wherein the de-continuated information is provided to the device provided on the second device. σ 2. The system of claim 2, further comprising a bridge operative to interface a first bus bar with a bus bar matrix using a bus bar protocol, wherein the first contiguous A system is coupled to the bridge. 3) The system of claim 2, further comprising: a slave device that uses the first protocol and is lightly coupled to the second continuator, wherein the de-continuation=information is provided to the slave device, wherein The slave device is operative to provide a response to one of the information from the bridge. 4. The system of any one of claims 3 to 3, wherein the first device is a first integrated circuit chip and the second device is a second integrated circuit chip. 5) The system of claim 1, wherein the peripheral 130924.doc 200900951 device is operable to read information from the device and write to the slave device from one of the systems Enter the main device of the information. 6. A system as claimed in claim 1, wherein the peripheral circuitry provided on the second device is a slave device operable to read information from a primary device of the system and to provide information to the primary device. 1 'A system as claimed in claim 6, wherein the slave device is an advanced high performance bus (AHB) slave device that is via an AHB protocol. The body of the system of claim 6 wherein the slave device is an advanced peripheral bus (ΑΡΒ) slave device via an APB protocol. The system of claim 2, wherein the bridge is a ΑΗΒ/ΑΡΒ bridge provided on the first device, and the ΑΗΒ/ΑΡΒ bridge is enhanced to be in communication through the communication bus Wait for the loop to allow the information to be continuous. 1 〇· 如明求! The system, wherein the first and second contigators each package = a 2 structure 'the mechanism is operable to be used in the communication bus Automatically wait for a loop to allow this continuation of this information. 11. The system of claim 1 (), wherein the automatic waiting cycles are based at least in part on a ratio between a continuous clock and a system clock frequency. 12-item 10 system in which it is operable to introduce an automatic wait loop: the constitutive includes a finite state machine, wherein each of the continuators moves: the register 'the one or more shifts are temporarily stored The device is operable: :: Continuously " is transmitted through the communication bus and the information received from the 4 仏 bus is de-continued. 13. The system of claim 1 wherein the step further comprises an additional device comprising - peripheral device to 130924.doc 200900951, wherein a continuator coupled to the matrix is provided on the first device The continuator coupled to the peripheral device on the additional device by a communication bus is coupled to the peripheral device. 14. The system of claim 2, wherein the first continuator receives the continuous information received from the continuous clock provided during the continuous transfer and manages the One of the operations of the bridge is resynchronized. The system of claim 1, wherein the second contigator re-transmits continuous information received from a continuous clock provided during a continuous pass and a clock that manages the operation of the slave using the second agreement Synchronization. A method for & bus communication, the method comprising: using a first-continuator provided on the -th device to continuously stream the bus information received from the matrix, and through the communication bus Communicating the bus information that has been continuous; and: receiving and disconnecting the streamed bus from the communication® stream by using a second serializer provided on the second device A information in which 5 hai has been de-continuated is provided to a peripheral device provided on the second device. The method of the long item 16 wherein the continuation includes receiving the 匚 排 来自 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛 汛The row protocol is interfaced with a bus bar matrix that is different from the second bus bar protocol of one of the first agreements of the δH, and wherein the slave device uses the first bus bar protocol. The method of claim 17, wherein the continuation, the continuation, and the continuous information of the parallel bus and the continuous information are waiting for a loop. Inserting a method for the bridge according to any one of claims 17 to 18, wherein the received continuous information from the communication bus is derived from information provided by the slave device, The slave device is provided on a device other than the device on which the bridge is provided. 2. The method of claim 19, wherein the step of retrieving the received continuous information from the continuous clock provided during the continuous transmission is resynchronized with one of the operations managing the bus matrix. 21. The method of claim 20, wherein the peripheral device provided on the second device is a host device operable to read information from the device and write information to the slave device. 22. The method of claim 20, wherein the peripheral device provided on the second device is a slave device operable to read information from one of the primary devices of the system and to provide information to the primary device. 23. The method of claim 22, wherein the slave device is a slave device that communicates via a protocol. 24. The method of claim 22, wherein the slave device is a slave device that communicates via a protocol. 25. The method of claim π to 18, wherein the bridge is an enhanced ΑΗΒ/APB bridge provided on the first device, the ΑΗΒ/ΑΡΒ bridge permitting communication in the communication through the communication bus Wait for a loop to allow this continuation of this information. 130924.doc 200900951 The second continuator will be self-communicating to allow 26. The method of claim 16, wherein the first and the first special-purpose loops introduce the continuation of the information for the communication bus. 27. The method of claim 26, wherein the automatic waiting cycles are based at least in part on a ratio between a continuous clock and a system clock frequency. 28. A system comprising bus communication, the system comprising: a matrix operable to connect to a plurality of confluences of the topology v information selection destination on the row, wherein the matrix is provided on a first wafer; '% a first-continuator, which is coupled to the matrix and provided on the first wafer, the first-continuous The processor is operable to continuously transmit information received from the matrix and transmit the continuous information through a communication bus; a second serializer is provided on a third wafer and is The communication bus, the second continuator is operable to receive the: continuous information and to de-continue the continuous information; and a peripheral device is coupled to the (four) two-continuator and provided On the second wafer, wherein the peripheral device receives the de-continued information from the second continuator, wherein the first and second contigators will automatically wait for the loop to be introduced. The communication protocol of the communication bus to allow this continuation of the information. The system of claim 28 wherein the peripheral device is a host device operable to read information from, and write to, the slave device from one of the systems. 30. The system of claim 28 wherein the peripheral device is a slave device operable to receive information from one of the primary devices of the system and to provide information to the primary device. 3 1 • The system of claim 3, wherein the slave device is an agricultural device that communicates via an AHB protocol. 32. The system of claim 30, wherein the slave device communicates with the APB slave device via an alpha-ρβ protocol, and further comprising an AHB/APB bridge provided on the first device, the AHB/APB bridge system Enhanced to permit a wait loop in the communication through the communication bus to allow for the continuation of the information. 33. A computer readable medium comprising: program instructions to be implemented by a computer and for providing bus communication, the program instructions being used to: use a first continuous provided on a first device The Continuator contiguously receives bus information received from a matrix and transmits the contiguous bus information through a communication bus; and receives from the second contigator provided on a second device The continuous bus information of the communication bus is de-continuated, and the de-continuated information is provided to a peripheral device provided on the second device. 34. The computer readable medium of claim 33, wherein the program instructions for continuation include receiving parallel busbar information from a bridge, the parallel busbar information addressing (4) "setting" wherein the bridge is configurable The operation is to use a bust-collection agreement and a pass-through confession to use a busbar matrix technique that is not inconsistent with the second busbar agreement of the first agreement, and wherein The slave device uses the first bus bar protocol. 130924.doc 200900951 35 36 37. The computer readable medium of claim 33, wherein the program instructions for continuation include insertion during the continuous and continuous transmission of the information One of the bridges waits for a loop. • A computer-readable medium that includes program instructions to be implemented by an electric device and used to interface with a slave device in a bus system, such as “U·排通#, shai, etc. The command is configured to: receive parallel bus bar information from a bridge, the parallel bus bar is addressed to the slave device, wherein the bridge system is operable to different from a first bus bar protocol One of the first agreements, the second bus bar protocol, the bus bar barrier is pulled, & Gan Iϋ ' early, 1 followed by the slave device using the first bus bar protocol; the parallel bus bar information i 钵U contiguously transmits the continuous information on the -communication® stream; and inserts a wait loop for the bridge between the continuous and continuous transmission of the parallel bus header F. : a type of brain-readable medium, comprising a program to be implemented by a computer and used to interface bus-to-slave communication, the program instructions are used to: provide a selection to the slave device a ^ sign and an enable signal to enable communication with the slave device, the split select enable and enable signals are provided for use; and the bridges of the two different bus bar protocols to the = Causing a wait state in the bridge until the continuous communication with the slave device. 130924.doc