TW200845313A - Shield plates for reduced field coupling in nonvolatile memory - Google Patents

Abstract

Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates. Each shield plate can be deposited and etched without complex masking to connect the control gates and shield plates. In one embodiment, the shield plates are at a floating potential.

Description

200845313 IX. Description of the Invention: [Technical Field of the Invention] The A relationship of the present invention is directed to a high density semiconductor device such as a non-volatile memory, and a system and method for isolating components in a high density semiconductor device. Cross-referencing the following application fortunately, the light is determined by Gan Renyu, and the full text is incorporated by reference herein:

Jack H. Yuan's name is "In the non-volatile memory used to reduce the field. Mahe's barrier board manufacturing method (Meth〇ds 〇f Yangxian

Plates for Reduced Field Coup, in in Non.v〇latUe Mem〇ry)j US Patent Application No. ",,, ------[Agent File Number SAND- 01079US0] 'This case is on the same day Apply. [Prior technology]

Lj semiconductor memory devices are already popular in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. T-erasable and programmable-only read-only (eepr〇m) (including flash (4)) and electronically programmable read-only memory (epr〇m) are the most popular non-volatile semiconductor memories. The flash memory is stored in the 7-depletion region by a floating gate or other charge that is positioned above and 盥 and insulated in the channel region of the conductor substrate. Position the floating gate between the source and drain regions. >& Gates are provided on the floating gate and insulated from the floating gate. The threshold voltage of the transistor is controlled by maintaining the amount of charge on the % / pre-action gate. That is, the stalk is controlled by the level of the charge on the + gate to turn on the transistor. Between the source and the drain of the 127821.doc 200845313 The minimum amount of uranium must be applied to the control gate. When programming an EEPROM or flash memory device (such as a ΝΑΝβ flash device), a stylized voltage is normally applied to the control gate: the source is grounded. The electrons from the channel are in the floating gate. When the electrons accumulate in the oceanic gate, the floating pole becomes negatively charged, and the threshold voltage of the sensation rises so that the thrift _ ' S 兀 圮 圮 圮 兀 兀 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The title of the US Patent Application No. 1G/379, 6G8 and July 29, which was filed on March 5, 2003, entitled "Self-B_Ung Technique", is entitled

Detecting 〇ver pr〇grammed _ ry ry's US patent Shen Gu main security secret number 29, 068 found more information about stylization; both applications are incorporated by reference in full text. Some EEPROM and flash memory devices have floating gates for storing two (four), and therefore, can be programmed/erased in two states (erased state). Sometimes it will be 誃) 石 石 fe fe fe fe fe fe fe fe ^ ^ ^ ^ ^ ^ 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施

The voltage limit range corresponds to a predetermined value of the data I encoded in the memory device. ^ The shift of the apparent charge of a floating closed pole or other charge storage area. The electric field of the electric charge in the adjacent floating gate is merged into this article. (4) = The phenomenon of the lightness of the pole is described in the full-text gate and the adjacent floating 閙 斯 ^ ^ ^ ^ ^ Floating gates of adjacent floating gates, adjacent floating gates or adjacent bit lines and word lines on the same bit line 127821.doc 200845313 (and thus diagonally adjacent to each other). The transition between the floating gate and the floating pole is most pronounced. The time is stylized by the neighboring memory. Flat and confused between the wooden mouth. For example, the second: Bean:: is programmed to add a charge level corresponding to the data to its floating gate. Subsequently, - or a plurality of adjacent memory cells are privateized to add a level corresponding to the second set of f materials to their floating gates. After the process of the adjacent memory cells is performed, the charge level read from the first memory cell is converted to the program on the adjacent memory cell of the first memory cell. The effect of the μ is now different from the original stylized charge level. From adjacent memory, the sum of the apparent charge levels read from the target unit can be offset by a sufficient amount to cause an erroneous reading of the data stored therein. The effect of the net-moving gate and the floating gate is significant for multi-state devices: because in multi-state devices, the allowable threshold voltage range and the need to make a difference in the binary device? . Therefore, floating gates and floating questions

The U-polarization can cause the memory cell to be within the forbidden range of the allowable threshold voltage range. As the memory cell continues to shrink in size, the natural stylization and erase distribution of the threshold voltage is expected to be due to short channel effects, larger oxide thickness/turn: ratio change, and larger channel dopant fluctuations. Increased to reduce the available separation between adjacent evils. This effect is much more pronounced for multi-state memory than using only two states of memory (binary memory). The reduction in space between the outer word lines and the reduction in space between the bit lines will also increase the coupling between adjacent floating gates. Therefore, there is a need to reduce the effect of charge coupling between a floating gate in a non-volatile semiconductor memory and other charge storage regions of 127821.doc 200845313.

1; The present invention provides a technique for reducing barrier between a charge storage region and a phase for forming a barrier in a non-volatile semiconductor memory device. A barrier panel may be formed adjacent to the bit line side of the floating closed pole facing the opposite bit read side of the adjacent floating interpole. An insulating layer can be formed between each barrier plate and its corresponding adjacent charge storage region. The insulating layer may extend to the horizontal surface mu formed in the upper surface of the control (four) pole above the charge storage region to form an insulating member and a barrier plate. Each barrier panel can be a deposition sidewall formed without the complex masking operations used to connect the control panel. In an embodiment, the barrier panel is at a floating potential. In a method, a method of fabricating a non-volatile memory is provided, comprising forming a plurality of adjacent charge storage regions along a substrate in a first direction, and forming a plurality of adjacent control terminals above the charge storage region, And a side of the charge storage region facing the adjacent charge storage region in the first direction: and a side surface of the control electrode facing the adjacent control electrode in the first direction. The insulating member is from at least the lower surface of the floating gate: to at least the surface level above the control electrode. Conducting conduction along the insulating member ^,,,, electrical storage area and control gate insulation. In one embodiment, the isolation component is in the floating f-bit _ component is electrically connected to the corresponding word line at the word line beyond the individual storage of each - corresponding column::: = = hex. " Number::: In the example, a non-volatile memory system is provided, which includes: a charge storage _ of a plurality of materials, which is disposed on the substrate in the direction of the bit line 127821.doc 200845313 side: a plurality of control poles Formed above the adjacent charge storage region, the mother-control idler has two bit line sides substantially coplanar with the bit line side of the corresponding charge storage region; an insulating member adjacent to the adjacent electronic region Each of the 70-line sides; and a floating conductive isolation member "15 close to the mother-insulated member, each spacer member shielded - corresponding adjacent charge storage region. In a case, the conductive isolation member may be The word line connection formed above the charge storage area corresponding to the isolation member y must be extended from the surface level below the surface of the electric storage area to the upper surface level of the control idler. According to the inspection specification, drawings and patent application Other features, aspects and objects of the present invention are obtained in the scope of the invention. [Embodiment] Fig. 1 is a plan view showing a NAND string. Fig. 2 is an equivalent circuit diagram thereof.

L. For the purpose of elaboration, regarding shielding non-volatile flash memory (specifically, NAND type flash memory), shielding and isolation techniques according to embodiments are proposed. However, those skilled in the art should understand that the stated The technology is not so limited and can be utilized in many manufacturing processes to fabricate various types of integrated circuits. For example, such techniques can be used to fabricate NOR-type memories or other devices that require shielding between adjacent charge storage regions. The NAND string depicted in Figures 1 and 2 includes four transistors (10), ^1 (8), and _ connected in series and sandwiched between a first selectable closed pole 120 and a second selected gate 122. The select pole 12 is connected to the bit line via the bit line contact 126. Selecting the interpole 122 connects the D string to the common source line via the source line contact 128. Each of the transistors (10), (10), the old and _ 127821.doc -10- 200845313 includes a control gate and a floating gate. For example, the transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. Note that although Figures 1 and 2 show four memory cells in the N AND string, only the use of four transistors is provided as an example. The NAND string can have four or fewer memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, or more than 32 memory cells. A typical architecture for a flash memory system using a NAND structure would include many NAND strings. For example, Figure 3 shows three NAND strings 202, 204, and 206 of a memory array with more NAND strings. Each of the NAND strings of Figure 3 includes two select transistors and four memory cells. Each string is connected to the source line by its selection transistor (e.g., select transistor 230 and select transistor 250). Use the select line SGS to control the source side select gate. The individual NAND strings are connected to respective bit lines by select transistors 220, 240, etc., controlled by selected line SGD. Each word line (WL3, WL2, WL1, and WL0) is coupled to a control gate of one of the memory cells of each NAND string (which forms a column of cells). For example, word line WL2 is coupled to the control gates of memory cells 224, 244, and 252. As can be seen, each bit line and each NAND string constitutes a row of arrays of memory cells. 0 127821.doc 200845313 FIG. 4 is a flash that can be fabricated according to an embodiment, such as that depicted in FIGS. 1 through 3. A two-dimensional block diagram of one embodiment of a memory unit of a memory unit. The memory cell of Figure 4 includes a triple well comprising a germanium substrate, a well and a well. The crucible substrate and the crucible are not depicted in Figure 4 to simplify the drawing. Within the 32-well ρ well is the Ν + doped region 324, which acts as the source/drain region of the memory cell. Marking the Ν+ doped region 324 as a source region or a drain region is somewhat arbitrary. The 'source/drain region 324' in the NAND string will act as the source of a sensible unit and the drain of a neighboring memory unit. Thus, the Ν + swap source/drain region 324 can be considered a source region, a drain region, or both. Between the Ν + doped regions 324 is a channel 322. Above the channel 322 is a first dielectric region or dielectric layer 330. Above the dielectric layer 330 is a conductive or conductive layer 332 which forms the floating gate of the memory cell. The floating gate is electrically insulated/isolated from the channel 322 by the first dielectric 330 under low voltage operating conditions associated with the read or bypass operation. Above the floating gate μ] is a dielectric region or dielectric layer 334. Above the dielectric layer 334 is a second conductive layer ϋ 336, which forms the control gate of the memory cell. In other embodiments: various: may be interspersed within the layers described or added to the layers described. An additional layer can be placed over the control gate 336, such as: =6 dielectric f33G, floating gate, dielectric 332, and control interface to form a stack. Array of memory cells I: Rear: As used herein, the term stacking may refer to the manufacturing order ρ of the visual elements of the memory cells at different times after the manufacture of " " and the cups are backed up or Less layers. In the case of the memory-like unit, the 127821.doc 200845313 replaces the conductive floating gate with a non-conductive dielectric material to make it non-volatile. The way to store charge. This unit is described in the article by Chan et al. "A True Single (Trans) Oist-Oitide-Oxide EEPROM Device,, IEEE Electron Device Letters, Volume EDL-8, No. 3, March 1987, On pages 93-95, a three-layer dielectric formed of hafnium oxide, tantalum nitride, and hafnium oxide ("ΟΝΟ" is sandwiched between the conduction control gate and the surface of the semiconductor substrate. The cell is programmed by injecting electrons into the nitride from the cell channel, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the channel of the unit in a detectable manner. The cell is erased by injecting a thermal hole into the nitride. See also Nozaki et al., ''Α 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application》, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, It describes a similar unit employing a split gate configuration in which a doped polysilicon gate extends over a portion of a memory cell channel to form a separate select transistor. The foregoing two articles are incorporated herein by reference in their entirety. The stylized techniques mentioned in Section 1.2 of William D. Brown and Joe E. Brewer, "Nonvolatile Semiconductor Memory Technology", IEEE Press, 1998 (which is incorporated herein by reference) are also incorporated by reference in Described as applicable to dielectric charge trapping devices. The memory unit described in this paragraph can also be used in conjunction with embodiments of the present disclosure. Another method of storing two bits in each cell has been made by Eitan et al., fNROM: A Novel Localized Trapping, 2-Bit Nonvolatile 127821.doc -13- 200845313

Memory Cell, IEEE Electron Device Letters, Vol. 21, No. 11, 2000, pp. 543-545. The 〇N〇 dielectric layer extends across the channel between the source diffusion region and the drain diffusion region. The charge of a data bit is regionalized in a dielectric layer adjacent to the drain, and the charge about the other data bit is localized in a dielectric layer adjacent to the source. By separately reading the dielectric Two of the charge storage regions separated by the internal space

ϋ Carry status to obtain multi-state data storage. The memory unit described in this paragraph can also be used in conjunction with embodiments of the present disclosure. When based on the wearable, the programmable voltage is programmed to read the memory (EEPR0M) and the bit line is grounded. As the electron tunnels across the dielectric, electrons from the channel are injected into the floating gate. For this reason, dielectric 330 is often referred to as an intervening dielectric f or a channel oxide. When the electrons accumulate in the floating gate 332, the main and the private M ^ ^ ^ ^, the pre-action gate becomes negatively charged, and the threshold voltage of the memory unit rises to the virtual state. Within one of the threshold voltage ranges that are scheduled to be stored in one or more data bits, one of the sturdy nails. Typically, the stylized voltage applied to the control gate is applied as a burst of pulses. The magnitude of the pulse increases with a predetermined step size with each successive pulse. Figure 5 is a two-dimensional block diagram of two typical NAND strings 3〇2 and 304, which can be fabricated as part of a larger 恤 乂 陕 陕 陕 陕 陕 记忆 记忆 memory array. Although Figure 5 depicts four memory cells on strings 312 and 304, four or more memory cells can be used. Each of the NAND strings has a stack as described above with respect to Figure 4.冈止止以* and Figure 5 further depicts the N-well 326 below the P-well 320, along the NAND string; the gentleman △ 疋 line direction and perpendicular to the NAND string or bit 127821.doc -14- 200845313 The direction of the word line. Same as - P-type substrate below N-well 336 is not shown in Figure 5. In one embodiment, the batch 丨丨 闸 gate forms a sub-line. The conductive layer 336 is formed to be crossed across the word line to provide a common sub-line or control gate for each device on the word line. An individual control gate layer 336 is depicted in FIG. 5, which forms a single word line for a plurality of memory cells in a column, which may be at a point where the layer overlaps the corresponding floating gate layer 332. This layer is considered to form a control idle for each memory cell. At f

In other embodiments, individual gates may be formed and then interconnected by separate formed word lines. In fabricating a NAND-based non-volatile memory system including a NAND string as depicted in Figure 5, it is important to provide electrical isolation in the word line direction between adjacent strings such as NAND strings 302 and 3o4. In the example depicted in Figure 5, NAND string 302 is separated from NAND string 3〇4 by an open region or gap 3〇6. In a typical sNAND configuration, a dielectric material is formed between adjacent NAND strings and will be present at the open area 3〇6. There are numerous techniques for isolating devices in the word line direction for NAND flash memory and other types of semiconductor devices. In the local oxidation of ruthenium (LOCOS) technique, an oxide is grown or deposited on the surface of the substrate, followed by deposition of a nitride layer on the oxide layer. After patterning the layers to expose the desired isolation regions and covering the desired active regions, the trenches are etched into the layers and a portion of the substrate. The oxide is then grown on the exposed area. Improvements to the LOCOS process have been accomplished by using techniques such as sidewall mask isolation (SWAMI) to reduce erosion of the active area. In SWAMI, the formation of nitride on the sidewalls of the trench prior to oxide formation reduces the erosion of oxides and the formation of bird's beaks by 127821.doc -15 - 200845313. For more details on these and other isolation techniques, see U.S. Patent Application Serial No. 10/ filed on November 23, 2004, entitled "SELF-ALIGNED TRENCH FILLING WITH HIGH COUPLING RATIO" U.S. Patent Application Serial No. 11/251,386, the entire disclosure of which is hereby incorporated by reference in its entirety by reference in its entirety in the entire entire entire entire entire entire entire entire entire content The manner is incorporated herein. Figure 6 is a plan view of a portion of an array of NAND flash memory cells in accordance with an embodiment. Parallel word lines 336 are horizontally displayed overlying and across a set of charge storage regions 332 to form a column of control gates for the memory cells. Word line 336 is shown transparent to show underlying charge storage region 332, trench isolation region 350, and the like. It should be understood that the word lines are continuous and formed over trench isolation regions 350 and charge storage regions 332. Each charge storage region 332 is formed between adjacent trench isolation regions 350 (which are shown vertically in Figure 6 or in the direction of the bit line). The isolation in the horizontal or wordline direction provided by trenches 350 allows the fabrication of rows or strings of charge storage regions. Each row is connected to an individual bit line 362 at one end (eg, immersed) and to a common source line (not shown) at the other end via a contact point as shown in FIG. 1, thereby defining a flash memory element NAND string or row. For the sake of simplicity of explanation, only one bit line 362 (contactless connection) will be described. A typical memory array will include thousands or thousands of NAND strings and may include any number of memory cells, not just four as illustrated. According to an embodiment, the isolation features 340 are provided between the adjacent charge storage regions 332 in the bit line direction 127821.doc 200845313. The isolation features reduce charge coupling between adjacent charge storage regions. The electric field is associated with charge storage region 332, which depends on the amount of charge stored in the region. These electric fields can have components in either direction, thereby affecting the apparent threshold voltage of adjacent storage elements. Isolation component 340 can provide termination points for such electric fields to reduce the amount of charge coupling between adjacent charge storage regions, and thus reduce the occurrence of offsets in the apparent threshold voltage of the memory cells. In one embodiment, the isolation features 340 are isolated sidewalls or barrier panels formed by the use of sidewall fabrication techniques as described hereinafter. Although not so limited, the barrier plate 340 is particularly adapted to reduce charge coupling between charge storage regions 340 that are adjacent to each other in the direction of the bit line. The barrier provides termination for the electric field having components in the direction of the bit line and in other directions. Although the board 340 is provided between the charge storage areas adjacent in the bit line direction, it may be in other adjacent charge storage areas (such as charge storage areas on adjacent bit lines and word lines and thus diagonally adjacent). Provide shielding between ). A barrier plate 340 is formed between the adjacent stacks in the direction of the bit line. Each plate is separated from its nearest charge storage area 332 by an insulating member 338. Insulating member 338 can be a dielectric spacer formed along each stack to provide insulation between the respective barrier and charge storage regions in the direction of the bit line. Like the barrier panel 340, the spacers extend in the word line direction along the side of the bit line adjacent to the stack in the direction of the bit line. In one embodiment, the insulating member is an insulating sidewall formed by using sidewall fabrication techniques. Although not shown, the insulating member 338 and the spacer member 340 may be formed along the bit line side of the charge storage region 12782l.doc -17-200845313 facing the selection gate of the nAND string. In an embodiment, the barrier panel 34G is floating and has no electrical connections. A per-floating barrier such as a polycrystalline or metallic conductive material is electrically coupled to its nearest word line 336 by an insulating region 338. Its power will rise and fall with the voltage of its nearest control gate. The voltage will vary depending on the ratio of its coupling to the control gate. The ratio depends on

C

The dielectric constant and size of the insulating region and the size and material of the barrier, charge storage region and/or word line 336. The technique according to an embodiment of the present disclosure can simplify the manufacture of the isolation member. In one embodiment, the floating barrier panel 340 is formed by simply depositing a barrier sheet material and etching it back to form a sheet barrier as illustrated with respect to Figures 8A through 8 (in other embodiments, in other embodiments, The board is not floating, but is made away from the individual memory cells to make a connection to the word line (eg, before or after the first memory cell in a column) to avoid the size of the device between the devices. Complex masking operations. For example, electrical connections may be provided prior to a column of first memory cells, after the last memory cell of the column, or at openings or discontinuities within the memory array. A flowchart depicting a method for forming a memory array in accordance with an embodiment is depicted. Figure 8 through Figure 8G illustrate a memory array at various points during a fabrication process such as the fabrication process depicted in Figure 7. Note that For the sake of clarity, many steps of the manufacturing process that should be understood by those skilled in the art are not illustrated. Figure 7 is described with reference to Figures 8A-8G to emphasize and illustrate selected steps of the process, but is not limited thereto. Fabrication of the device. Thus, while Figures 7 and 8 127821.doc • 18-200845313 to Figure 8G depict a particular NAND flash memory example, the disclosed principles can be used in accordance with other manufacturing processes to form other types of devices. Figure 8A is a cross-sectional view of the memory array taken along line A of Figure 6, depicting a substrate 300 on which a plurality of non-volatile flash memory devices are fabricated and in which a substrate 3 is typically used. The substrate is shown, but it may also include p-wells and wells formed therein, as appropriate for various implementations. For example, wells and wells may be formed in the substrate 3〇〇 as depicted in Figure 5. f The implantation of the triple well including the substrate 300 and the associated annealing are performed at step 402 of Figure 7. After implantation and annealing of the triple well, a dielectric layer 33 is formed over the substrate 300. 33〇 forms a tunnel dielectric region of a plurality of storage elements and may comprise an oxide or other suitable dielectric material in various embodiments. The dielectric layer 330 may be formed by using a known chemical vapor deposition (CVD) process, metal organic CVD process, physical gas Deposited by a deposition (pVD) process, an atomic layer deposition (ALD) process, by growth using a thermal oxidation process Q or by using another suitable process. In one embodiment, the dielectric 330 is approximately in thickness. It is from 70 Angstroms to 100 Angstroms. However, thicker or thinner layers may be used in accordance with various embodiments. In addition (and as the case may be), other materials may be deposited on the dielectric and deposited under the dielectric. Or incorporated into a dielectric to form a dielectric layer 330. At step 406, a charge storage layer is deposited on top of the tunnel oxide layer. In Figure 8A, the charge storage layer is a first conductive layer 332, The floating gate of the memory device that will constitute the string being fabricated. In one embodiment, the conductive layer 332 is a polycrystalline layer 127821.doc -19-200845313 沉积 deposited by using a known process as described above. In other embodiments, other conductive materials can be used. In one embodiment, the conductive layer 332 is approximately 500 angstroms in thickness. However, a conductive layer thicker or thinner than 500 angstroms may be used depending on the embodiment. The charge storage layer deposited at step 406 can include a conductive floating gate material (e.g., polysilicon) or a dielectric charge storage material (e.g., tantalum nitride). If a three-layer dielectric is used, step 404 can include depositing a first hafnium oxide layer and step 406 can include depositing a nitride charge storage layer. The second hafnium oxide layer may be deposited in a later step to form an inter-gate dielectric (which will be discussed later). In one embodiment, a tailored dielectric layer is used and a charge storage region is formed therein. For example, a special layer of germanium-rich germanium dioxide can be used to capture and store electrons. This material is described in the following two articles incorporated herein by reference: DiMaria et al. "Electrically-alterable read-only-memory using Si-rich SI02 injectors and a floating polycrystalline silicon storage layer 11 5 J. Appl. Phys. 52(7), July 1981, pp. 4825-4842; H〇fi et al. "A MOSFET with Si-implanted Gate-Si02 Insulator for Nonvolatile Memory Applications", IEDM 92, 1992 4 Month, pp. 469-472. As an example, the thickness of the layer can be about 500 angstroms. Steps 404 and 406 can be combined because the tailored dielectric layer will form a tunnel dielectric layer, a charge storage layer, and (as appropriate) a gate. Inter-dielectric layer. After depositing a floating gate or other charge storage layer, a nitride sacrificial layer 342 is deposited at step 408. The nitride layer may be about 400 angstroms thick. However, the thickness may be comparable to the exemplary dimensions provided herein. Large or small, and can vary depending on the implementation of layers 127821.doc -20- 200845313. Layers 330, 332, and 342 are preliminary NAND string stack layers used to form a plurality of devices. A plurality of NAND_s are constructed. After forming layers 330, 332, and 342, a hard mask can be deposited on nitride layer 342 at step 41 to begin defining individual nand strings of devices. Light lithography can be used in the regions. A strip of photoresist is formed to form a NAND string. After forming a strip of photoresist, it can be etched, for example, by using an anisotropic plasma p (for etching and chemical etching of the object for each flat layer encountered) The exposed mask layer is etched by reactive ion etching between the proper balance. After the mask is etched, the photoresist can be removed. At step 412, the nitride layer is etched by using a mask. And floating gate layers to form individual NAND string stack regions. These will be individual NAND strings of memory devices. The three NAND string stacked regions are adjacent to each other in the word line direction. At step 414, the substrate 3 is etched to An isolation trench 350 is formed between the stacks. The trenches isolate adjacent rows of memory cells from their substrate active regions to define individual NAND strings. In step 416, isolation is filled with a dielectric such as cerium oxide. Trench 35 〇 to provide effective isolation. At step 418, excess oxygen and any remaining portions of the nitride layer 342 are ground by using, for example, chemical mechanical polishing to planarize the upper surface of each floating gate 332. Figure 8B is a cross-sectional view of the memory array taken along line A of Figure 6 after step 41 8 . Various techniques for forming the isolation trench 35 can be used in accordance with an embodiment. For example, trench 350 can be a deeper self-aligned trench formed by etching through a pre-deposited floating gate and tunnel dielectric layer as described. 127821.doc • 21 · 200845313 In one embodiment, the trenches may be filled by growing a dielectric such that subsequently deposited control gate layers may extend in the word line direction between the floating gates for increased coupling. . For more information on the technique of utilizing one of the deeper self-aligned trenches, see US Patent Application entitled "SELF-ALIGNED TRENCH FILLING WITH HIGH COUPLING RATIO" by Jack H. Yuan, filed on November 23, 2004. No. 10/996,030, the disclosure of which is incorporated herein in its entirety by reference in its entirety in its entirety in the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all allally all The upper portion of the groove is described in U.S. Patent Application Serial No. 11/251,386, the entire disclosure of which is incorporated herein in This application is hereby incorporated by reference in its entirety. Other techniques such as LOCOS or SWAMI as previously described may be used in other embodiments. In some embodiments, isolation trenches may be formed prior to the floating gate and/or tunnel dielectric, as currently described. A dielectric is deposited at step 420 for the inter-gate dielectric region 334. In one embodiment, the inter-gate dielectric is a multilayer germanium (oxide-nitride oxide) having a first oxide layer thickness of 50 angstroms, a nitride layer thickness of 70 angstroms, and a thickness of 70 angstroms. The thickness of the dioxide layer. The effective thickness of this configuration is around 140 angstroms. Other sizes and other types of materials can be used. One or more layers for controlling the gate 336 are formed in step 422. In one embodiment, control gate 336 has a thickness of about 2000 angstroms. In one embodiment, a polysilicon layer 344, a tungsten germanium (WSi) layer 346, and a tantalum nitride (SiN) 3 48 are deposited to form a 127821.doc -22-200845313 control gate 336. WSi 346 is a lower resistance layer and siN is an insulator. Figure 8C depicts a cross-sectional view of the memory array along line a of Figure 6 after step 422. At step 424, a photoresist pattern is formed over a hard mask (such as a deposited oxide over SiN 348) to define individual control gates or word lines 336 of the array. The layers 348, 346, 344, 334, 332, and 330 are in the step 42 6 in a direction substantially perpendicular to the bit line direction (vertical in FIGS. 8A to 8C) (in FIGS. 8A to 8C Word lines are formed on the horizontal). The sub-wires can be formed at step 426 using plasma etching, ion milling, pure physical ion etching, or another suitable technique. In one embodiment, the dielectric layer 330 is not tunneled at step 426 to maintain a continuous strip of dielectric material (directly below and between the parent-charge storage regions) over the substrate in the direction of the bit line. Figure 8D is a cross-sectional view of the memory array taken along line B of Figure 6, illustrating the cutting of three stacked arrays adjacent one another in the direction of the bit line as depicted horizontally in Figure 8D. At step 428, sidewall oxidation, sidewall deposition, or a combination of the two is performed. The apparatus can be placed in a furnace having a certain percentage of ambient oxygen at ambient temperature for oxidation through the exposed surface, which provides a protective layer. Sidewall oxidation can also be used to round the floating gate and control the edges of the gate. An alternative to oxide growth at elevated temperatures (e.g., above 1000 degrees Celsius) is low temperature (e.g., 400 degrees Celsius) oxide growth in high density tantalum plasma. Available, New Paradigm of Silicon Technology-, 〇hmi Λ K〇tani ^ Hirayama and Morimoto, Proceedings of the IEEE, Vol. 89, No. 3, March 2001; "L〇w_Temperature Growth of High 127821. Doc -23 - 200845313

Silicon Oxide Films by Oxygen Radical Generated in High Density Krypton Plasma", Hirayama, Sekine, Saito and

Ohmi, Dept· of Electronic Engineering, Tohoku University, Japan, 1999 IEEE; and "Highly Reliable Ultra thin Silicon

Oxide Film Formation at Low Temperature by Oxygen Radical Generated in High-Density Krypton Plasma", Sekine, Saito, Hirayama, and Ohmi, Tohoku University, Japan, 2001 IEEE (all of which are incorporated herein by reference) More information on sidewall oxidation. An N+ source/drain region 324 is formed during implantation in step 430. For example, arsenic or phosphorous implantation may be used. Halogen implantation may be used, and in some embodiments The annealing process is performed. Figure 8E depicts a cross-sectional view of the memory array along line B of Figure 6 after the N+ region is formed between the active regions in the substrate below the charge storage region 332. At steps 432 and 434, An insulating member 338 is formed between the stacks adjacent to each other in the direction of the bit line. Each layer of the stack has an upper surface and a lower surface, two sides substantially parallel in the direction of the word line, and two substantially in the direction of the bit line The side of the parallel (the first bit line side is depicted in Figures 8A to 8C). As depicted in Figure 8E, the insulating member is adjacent to the charge storage region 332, the inter-gate dielectric region 3 3 4 and a plurality of control gate layers 3 3 6 are formed on the bit line side. In an embodiment, the insulating member is formed only along the conductive portion of the control gate 336 (eg, polysilicon 344) without being along, for example, wSi 346. Or a layer of SiN 348. In one embodiment, insulating member 338 is a dielectric sidewall spacer (eg, oxide, nitride, etc.) which can be used by using ALD, CVD, etc. 127821.doc -24· 200845313 The oxide is deposited (step 432) and subjected to (d) (step 434) to form an insulating sidewall. In step 436, a conductive material is formed, for example, by depositing polycrystalline, metal or other material for isolation. The component 34() beta polycrystalline is very conformal and is deposited in an embodiment to form an isolation barrier plate 34. The material deposited in step 438 may be used to form a sidewall plate along each of the insulating sidewalls 338. In one embodiment, the barrier ribs 34 have a thickness of (10) angstroms or less in the direction of the bit line. Other thicknesses greater than or less than 5 angstroms may be used. For example, 'in the embodiment - 20 angstroms may be used or 1 〇 之 barrier plate. It can be used by this amount A very thin conductive layer to provide adequate termination. Please depict a cross-sectional view of the array of traces along the line of Figure 6, in which a barrier plate 340 is formed along the insulating region 338. Adjacent charge storage regions in the direction of the bit field Two plates are provided (between the opposite bit line sides adjacent the floating gates). Each of the barrier plates can provide termination of an electric field generated by charges stored on or in adjacent charge storage regions. Therefore, the offset of the apparent threshold voltage of the memory cell can be reduced. An interlayer dielectric f 352 is formed at step 440 to fill the array. The milk is a cross-sectional view of the memory array along line B of Figure 6 after step 440. At step 442, various backend processing can be performed. By way of example, various contacts can be etched, metal interconnects, etc. can be formed to complete the fabrication of the array. Various modifications to the barrier panel 34 can be made in accordance with an embodiment. Figure 8G depicts a barrier panel formed between stacks in the direction of the bit line and extending in the direction of the word line. The plates are formed from approximately the horizontal surface of the surface below the charge storage region to approximately the middle of the WSi layer 346. In an embodiment, the barrier 127821.doc • 25- 200845313 may not extend all the way to the lower surface of the charge storage region 332. In another embodiment, the barrier panel is formed almost to the upper portion of the substrate 300. The barrier panel may also extend to approximately the horizontal surface of the upper surface of the SiN layer 348 or only the upper surface of the 2 charge storage region 332. In an embodiment, the insulating member 338 does not extend to a layer (four) plane such as the portion of the WSi 346 or SiN 348 that forms the control gate. In each case, the floating barrier panels are electrically insulated from the control cores 336 (344 to 348). f, because the barrier plate is floating and made of a conductive material, it couples capacitance to its nearest floating gate and control gate. This can increase the effect of control gate 336 on its corresponding charge storage region. The control gate couples the capacitance to the barrier plate and the barrier plate capacitively couples to the charge storage region. Therefore, the control gate will exhibit a strong influence on the charge storage area. FIG. 9 depicts an alternate embodiment in which a single floating barrier 340 is included adjacent the charge storage region 332. A single plate between adjacent wordline stacks still provides a final U-stop for the electric field generated by the charge stored in the adjacent storage region. A single barrier panel 340 couples the capacitance to each of its nearest neighbors. It will not follow the voltage of the adjacent word line so closely when compared to the two plates as shown in Figures 8F and 8G. However, this configuration still provides shielding between adjacent-near charge storage regions. Because a single barrier plate is provided between the two control gates and the charge storage region, in one embodiment the plate is not electrically connected to any of the adjacent word lines. In this manner, the barrier panel provides independent electrical isolation for both adjacent electrical storage areas. The single barrier panel as illustrated in Figure 9 is particularly suitable for implementations with reduced equipment dimensions. When the memory cells of the array are scaled, the distance between the adjacent stacks 127821.doc -26- 200845313 in the direction of the bit line decreases. In order to form two isolation barrier sheets having independent electrical characteristics as illustrated in Figure 8G and Figure 8G, deposition or other processes must form two plates with sufficient isolation therebetween. If a single plate is formed as illustrated in Figure 9, the manufacturing requirements of this process level can be relaxed. Steps 436 and 438 (Fig. 7) only need to deposit a conductive layer and etch it to form a single barrier plate 340. Therefore, there is less demand for deposition and etching in a narrow space between adjacent stacked regions. f, in embodiments where two barrier plates are utilized between adjacent charge storage regions, the barrier plates can be electrically connected to their nearest word line 336. For example, referring to FIG. 6, the right portion of the word line 336! is depicted in its normal configuration, with one or more layers on the volts and thus preventing viewing of the inter-gate dielectric region 334, the floating gate 332, and Trench 350. A contact point 354 is provided between the end of the word line 336i and the two barrier plates 340 to which the word line is in close proximity. The contacts can be etched contacts or simple metal interconnects formed as part of the back end processing at step 442 of FIG. Since the connections are not formed along the entire length of each word line (including where each control gate overlies the corresponding floating gate), precise alignment at the device spacing is not necessary. The connection can be provided at a portion of the memory array that is remote from any of the individual memory arrays. Hunting by direct electrical connection 'the barrier board will be at the same potential as the word line and as described to provide termination and increased coupling. The position of the electrical connection 354 is more fully described with reference to Figures 10 and 11 . FIG. 10 depicts an exemplary structure of a memory cell array 502. As an example, a NAND flash EEPROM that is divided into 1,024 blocks is described. The data stored in each block can be erased at the same time. In one embodiment, block 127821.doc -27- 200845313 is the smallest unit of unit that is simultaneously erased. In this example, there are $ ‘ 5 12 rows in each block, which are divided into even and odd rows. The bit line is also divided into an even bit line (BLE) and an odd bit line (BL〇). Figure ι shows the four memory cells connected in series to form a NAND string. Although not four cells are included in each NAND string, more than four or four or less cells (e.g., 16, 32, or another number) may be used. One terminal of the NAND string is connected (to the corresponding bit line via the first selection transistor (also referred to as select gate) sqd, and the other terminal is connected to the C-source via the second selection transistor SGS. In an embodiment, a corresponding point in the memory cell provides a contact or electrical connection 354 between the word line and the one or more barrier plates. As depicted, the word line is external to the individual memory cells of the block or Connections are provided at portions of individual memory cells that extend beyond the block. For example, Figure 1A shows contact points 354 beyond the last memory cell of each column of memory cells. Simple to form between the sub-line and the barrier plate Contact points, vias, or other interconnects. In another embodiment, contact points 354 may be formed at locations beyond the first memory cells of a column outside the block of memory cells. For example, may be at word line WL3 An i-contact is formed between the i and its corresponding barrier plate at a portion of the WL3J that is in front of the memory cell connected to the ble〇 column. This connection may be after the word line of the column control circuit 5〇6 and at the a memory The portion before the cell (connected to BLE〇). In many array implementations, periodic breaks are often provided after a specified number of bit lines in the memory array. For example, after every 1 bit line, the array Portions may be open and do not include any memory cells prior to forming another bank bit line. These individual portions of the memory array may be referred to as sub-arrays 127821.doc -28- 200845313 columns. Figure 11 depicts A detailed view of the array and blocks in the configuration is utilized. The illustrated block includes individual portions that are part of different sub-arrays. The sub-array includes a number m of odd and even bit lines. The block includes a first portion formed by bit lines BLE〇, BLO〇 to bit lines BLem, BL〇m. The number of bit lines before each-opening in the array can vary from embodiment to embodiment. In various implementations, m can be equal to 5〇 or (10) f

U or hundreds of digits. The blocks in Figure i i have been simplified to show only one of the discontinuities in the array but may provide periodic discontinuities in the array after each odd and even bit lines until reaching the end of the array. A connection 354 between the barrier panel and the adjacent word line can be provided at each opening or discontinuity in the array or only at the portion of the opening. The periodic opening in the memory array is particularly suitable for the formation of contact points between the isolation member and its corresponding prewire. Figure] shows the contact point W between the isolation part and the corresponding word line at the opening between BL04 BLEm+i. Because the openings in the array are large, the degree of precision required to form the contacts between the isolation features and the word lines is not as great as the precision required to attempt to achieve the connection along the length of the word line. It is not necessary to form a contact at the device level pitch. The right δ and the pitch are, for example, 5 〇 nm, and the contact point can be formed, for example, by a larger size of 丨(9)(10) or 1〇0(10) or more. This greatly improves the fa ^ & and the improved yield of the isolated component. It is expected that less residual darkness attributable to short circuits or open circuits is due to the lesser degree of precision required in the system. Although it is not clarified that it can be split between the isolation part and the corresponding word line at each port (or some part thereof) in the memory array in a case of 127821.doc -29- 200845313 Contact point. Thus, after another m odd and even bit lines, additional contact points 3 54 can be formed between the isolation features and the word lines. During the reading and stylizing operations of the memory cells of one embodiment, 4,256 § memory cells are simultaneously selected. The selected memory cells have the same word line (e.g., WL2-i) and the same type of bit line (e.g., even bit lines). Therefore, the data of 532 bytes can be read or programmed at the same time. On the same day, the material of this special 5 3 2 byte is formed into a logical page. Thus, in this example, a block can store at least 8 pages. When the parent-memory unit stores two-dimensional data (for example, a multi-digit unit), one block stores 16 pages. In the continuation and verification operations, the selected gates (SGd and SGS) of the selected block are raised to one or more select voltages and the unselected word lines (eg, WL0, WL1, and WL3) of the selected block are raised to The transfer voltage (eg, 4·5 volts) is read to operate the transistor as a transfer gate. The selected word line (eg, WL2) of the selected block is connected to the reference voltage, and its level is specified for each read and verify operation to determine whether the threshold voltage of the memory cell of interest is above or below the threshold level. . For example, in a read operation of a meta-memory cell, the selected word line WL2 is grounded to detect if the threshold voltage is higher than 0 V. In the verify operation of a meta-memory unit, the selected word line WL2 is connected to, for example, 2.4 V, thereby verifying that the threshold voltage has reached 2.4 V as programmed. The source and p wells are at zero volts during reading and verification. The selected bit line (BLe) is precharged to, for example, 〇·7 ^ level. If the threshold voltage is higher than the read or verify level, the potential level of the bit line (BLe) of interest is maintained at 127821.doc -30-200845313 due to the associated non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the bit line (BLe) of interest is lowered to a low level due to the conduction of the memory, for example, less than 〇·5 v . The state of the memory cell is measured by a sense amplifier connected to the bit line to sense the voltage of the 70 line. The difference between stylizing or erasing a memory cell depends on whether the net negative charge is stored in the floating gate. For example, #negative charge storage

When the 于 is in the /pre-drive gate, the threshold voltage becomes higher and the transistor can be in the enhanced mode of operation. When the field is programmed in the example of the memory cell, the drain and the well receive the volts, and the control gate receives a series of programmed pulses with increasing magnitudes. In one embodiment the magnitude of the pulses in the series varies between 7 volts and !0 volts. In other embodiments, the pulses in the series may be different, e.g., having an initial level above 7 volts. During the privateization of the body unit, the test is also performed during the period between the stylized pulses. That is, the programmed level of each of the units of the sequenced group is read between each of the stylized pulses to determine if it has reached or exceeded the verification level to which it was programmed. Verify that one of the stylized factors is to test conductivity at a particular comparison point. The bit line voltage is ramped up to Vdd by all subsequent stylized pulses (eg, 2.5 volts)

For example, ΝΑΜη 丄-丄 v J out ) 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除 排除In some cases, the limit = number (e.g., 2 () pulses) will be limited and if the last - pulse is not fully programmed to the memory unit, an error is assumed. In some implementations, the memory cells are erased (in blocks or other units) prior to programming. 127821.doc • 31- 200845313 FIG. 12 is a block diagram of one embodiment of a flash memory system that can be used to implement one or more embodiments of the present disclosure. Other systems and implementations can be used. The fine line control circuit 504, the column control circuit 5 〇 6, the c source control circuit 5 1 〇 and the P well control circuit 508 control the memory cell array 5 〇 2 . A row control circuit 504 is coupled to the bit line of the memory cell array 502 for reading data stored in the memory cell for determining the state of the memory cell during the stylizing operation and for controlling the bit The potential level of the line is promoted or suppressed (programmed and erased. The column control circuit 506 is connected to the word line to select one of the word lines, the read voltage is applied, in conjunction with the bit controlled by the row control circuit 5〇4 The program potential is applied to the line potential level and an erase voltage is applied. The source control circuit 5 10 controls the common source line (labeled ''C source' in Figure 9) connected to the memory cell. The control circuit 5〇8 controls the p-well voltage. The data stored in the memory unit is read by the row control circuit 504 and output to the external 1/〇 line via the data input/output buffer 512. Via external I/ The O line inputs the stylized data remaining in the memory unit to the data input/output buffer 512 and transfers it to the row control circuit 504. The external I/O line is connected to the controller 518. Command data for controlling flash memory devices Enter the controller. (1) The command data informs the flash memory which operation is requested. The input - 7 is transferred to the state machine that is part of the control circuit 515. The state machine 5i6 controls the row control circuit 5〇4, column The control circuit 5〇6, the c-source controller 510, the p-well control circuit 5〇8, and the data input/output buffer (1) can also output the status data of the flash memory, such as ready/busy ^ 127821. Doc -32- 200845313 The controller 518 is connected to or can be connected to a host system such as a personal computer, a digital camera or a personal digital assistant, etc. It communicates with the host that initiated the command (9) such as to store data to the memory array 5 〇 2 or coughing the bait from the memory array and providing or receiving the data. The controller 5 converts the commands into command signals that can be interpreted and executed by the command circuit 514 that is part of the control circuit 515. The command circuit 514 is in communication with state machine 516. The controller jaws typically include buffer memory for writing to or reading user data from the memory array. An exemplary memory system includes an System 518 of the integrated circuit

Each s has a beta It P train and associated control, input/output and state machine circuits - or a plurality of integrated circuit chips. There is a tendency to integrate the memory array of the system and the controller circuitry - on one or more integrated circuit wafers. The memory system can be part of the host system or can be included in a memory card (or other package) that can be detachably inserted into the host system. The card may include the entire memory system (e.g., including the controller) or only a memory array with associated peripheral circuitry (where the controller or control functions are embedded in the host). Thus, the controller can be embedded in the host or included in the removable memory system. Figure 13 is a flow chart depicting a method for programming a non-volatile memory system. It is still within the scope and spirit of the present disclosure to modify, add, or remove various steps, which are obvious to those skilled in the art. In various implementations, the memory cells are erased (in blocks or other units) prior to programming. At step 650 of FIG. 13, the data load command is issued by the controller 518 and its input 127821.doc - 33 - 200845313 is input to the command circuit 514, thereby allowing data to be input to the data input/output buffer 512. The rounded data is treated as a command and is locked by state machine 516 via an unillustrated command latch signal input to command circuit 514. In step 652, the address information representing the page address is input from controller 518 to column controller 506. The input data is treated as a page address and latched by state machine 516 (by the address latch signal input to command circuit 514). At step 654, the 532-byte stylized data is input to the data input/rounding buffer 512. It should be noted that the 532-bit tuple of the modular bedding is specific to the particular implementation described, and other implementations will require or utilize various other sizes of stylized material. The data can be locked to the scratchpad for the selected bit line. In some embodiments, the data is also latched in a second register for the selected bit line for verification operations. At step 656, the programmatic command is issued by controller 318 and input to data input/output buffer 512. The command is latched by state machine 316 via a command latch signal input to command circuit 514. At step 658, the programmed pulse voltage level Vpgm applied to the selected word line is initialized to a start pulse (e.g., 12 volts), and the programmed count of the guard is initialized (4). A stylized voltage (Vpgm) pulse is applied to the selected word line at step 1. The bit lines including the memory cells to be programmed are grounded to enable stylization, while the other bit lines are connected to Vdd to suppress stylization during the application of the stylized pulses. At step 662, the status of the selected memory unit is verified. If it is detected that the target threshold voltage of the selected unit has reached the appropriate level (for example, 'the logical state of the programmed level or the specific state of the multi-state unit), the selected unit is tested 127821.doc -34 « 200845313 Second, to the target state. If it is detected that the threshold voltage has not reached the j level, the selected unit is not verified as being stylized to its target state. Those units that have been verified to be stylized to their target state at step 362 will be excluded. Beyond further stylization. At step 664, it is determined whether all of the units to be programmed are verified to have been programmed to their respective states (such as by checking the appropriate data storage registers designed to detect and signal the status). If so, the stylization process is complete and successful because all selected memory cells are programmed and verified to their target state. The status of the pass is reported in step 666. If at step 664 it is determined that not all of the memory elements have been verified successfully, the stylization process continues. At step 668, the stylized counter pc is checked against the stylized limit value. An example of a stylized limit is 2〇. If the stylized counter C is not at 20, the stylization process is marked as failed and the status of the failure is reported at step 67. If the stylized counter pc is less than 2 〇, then at step 672, the Vpgm level is incremented by the step size and the stylized counter pc is incremented. After step 672, the process returns to step 66 to apply the next pulse to program the pulse. At the end of the successful stylization process, the threshold voltage of the memory cell should be within one or more distributions of the threshold voltage of the programmed memory cell or within the distribution of the threshold voltage of the erased memory cell. . The flowchart of Figure 13 depicts a single-pass stylized method as can be applied to binary storage. For example, in a secondary process (tw〇_pass) stylized method that can be applied to multi-level storage, multiple stylization or verification steps can be used in a single iteration of the flow diagram. Steps 650 through 677 can be performed for each process of the stylized operation. In the first pass 127821.doc -35- 200845313, one or more stylized pulses can be applied and the result verified to determine if the cell is in the proper intermediate state. In the second process, one or more stylized pulses can be applied and the results verified to determine if the unit is in the proper final state. Figure 14 is a flow chart depicting one embodiment of a process for reading memory cells in array 512. In step 702, a read command is received from the host and stored in the state machine. In step 7〇4, the bit address is received and stored. The process of Figure 14 assumes a four state memory cell with an erased state and three stylized states. Thus, in one embodiment, three read operations are performed to read the data stored in the memory unit. If the memory has eight states, seven read operations are performed; if the memory has sixteen states, fifteen read operations and the like are performed. In step 7〇6, the first fetch operation is performed. Applying a first read comparison point equivalent to the threshold voltage between the state 〇 and the state 向 to the selected word line, and the sense amplification on each bit line is aligned with respect to the selected word line and the corresponding bit line The unit at the intersection is a binary decision to turn on Lj and turn off. If the detected unit is on, it is read as being in state 0, otherwise the unit is in state i, 2 or 3. In other words, if the threshold voltage of the memory cell is greater than the first read comparison point, then the memory cell is in the erased state. In step 708, a second read operation is performed. Applying a second read comparison point equivalent to the threshold voltage between state 2 and state 1 to the selected word line, and the sense amplifier on the mother bit line performs the father of the selected word line and the corresponding bit line The unit at the point is a binary decision of whether to turn on or off. "Disconnect, bit line ‘ indicates that the corresponding memory cell is in state 0 or state 1. "ON,, bit 127821.doc • 36 - 200845313 兀 line means that the corresponding memory unit is not in state 2 or state 3. f

^ In step: 71〇: Perform a third read operation. Applying a third read comparison point equivalent to the threshold voltage between state 3 and state 2 to the selected word line, and the sense amplifier on each bit line intersects the selected word line with the corresponding bit line The unit at the point is a binary judgment of whether to turn on or off. The "Disconnect" bit line will indicate that the corresponding unit is in state 〇, in state i, or in state 2. The "on" bit line will indicate that the corresponding memory cell is in state 3\store the information obtained during the three sequential steps set forth above in the latch. Use the decoder to combine the three read operations For example, the state 丨 will be the following three readings = fruit: in step 706 is on, in step 7 〇 8 is off and in step 710 is off. The above sequence of invertible read operations corresponds to the sequence of verify waveforms depicted in Figure 5. Note that other read processes may also be used in conjunction with the present invention. The present invention has been presented for purposes of illustration and description. The detailed description is not intended to be exhaustive or to limit the scope of the invention. It is a matter of practice to enable the skilled person to make the best use of the present invention in various embodiments and in various modifications suitable to the particular application contemplated. The scope of the present invention is defined. [Simplified Schematic] Figure 1 is a top view of a NAND string. Figure 2 is an equivalent circuit diagram of the nanD string depicted in Figure 1. 127821.doc -37- 200845313 Figure 3 depicts three NAND strings Figure 4 is a two-dimensional block diagram of one embodiment of a flash memory cell that can be fabricated in accordance with an embodiment. Figure 5 is a diagram of one of four NAND strings that can be fabricated in accordance with an embodiment. Figure 3 is a plan view of a portion of a NAND flash memory array in an embodiment. Figure 7 is a flow diagram of a method for fabricating a flash memory in accordance with an embodiment. Figure 8A-FIG. 8G depicts a portion of a memory array fabricated in accordance with an embodiment. Figure 9 depicts a portion of a memory array fabricated in accordance with an embodiment. Figure 1 depicts an exemplary organization of a memory array in accordance with an embodiment. An exemplary organization of a memory array in accordance with an embodiment is depicted in Figure 12. Figure 12 is a block diagram of an exemplary memory system that can be implemented in accordance with an embodiment. Figure 13 is a diagram for describing a program for non-volatile memory devices. Flowchart of one embodiment of the process. Figure 14 is a flow chart depicting one embodiment of a process for reading a non-volatile memory device. [Major component symbol description] 100 transistor 100CG control gate 100FG floating gate 127821.doc -38- 200845313

102 transistor 102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 106FG floating gate 120 first selection gate 122 second selection gate 126 bit line contact Point 128 source line contact point 202 NAND string 204 NAND- 206 NAND string 220 select transistor 224 memory unit 230 select transistor 240 select transistor 244 memory cell 250 select transistor 252 memory cell 300 substrate 127821.doc - 39- 200845313

Ο 302 NAND string 304 NAND_ 306 open area or gap 320 p well 322 channel 324 N+ doped region / source / drain region / N + doped source / drain region 326 N well 330 苐 a dielectric region or dielectric Layer/dielectric 332 conductive or conductive layer/floating gate/floating gate layer/charge storage region/first conductive layer 334 second dielectric region or dielectric layer/inter-gate dielectric region 336 second conduction Layer/Control Gate/Control Gate Layer/Word Line 336ί Word Line '338 Insulation/Insulation Area 340 Isolation Part/Barrier Plate 342 Nitride Sacrificial Layer 344 Polycrystalline Second Layer 346 Tungsten Antimonide (WSi) Layer 348 Tantalum Nitride (SiN) 350 trench isolation region/isolation trench 352 interlayer dielectric 354 contact point/electrical connection 362 bit line 502 memory cell array 127821.doc 200845313 504 row control circuit 506 column control circuit 508 P-well control circuit 510 c source control circuit 512 data input/output buffer 514 command circuit 515 control circuit 516 state machine 518 controller A line B line BLE even bit line BLE 〇 bit line BLEm bit line BLO odd bit line BLO 〇 Line BLOm bit line select line SGD / first select line selection transistor SGS / second select transistor Source source WLO word line WL1 word line WL2 word line WL3 WL3 word line "word line 127821.doc -41 ·

Claims (1)

200845313 X. Patent Application Range: 1. A method for manufacturing a non-volatile memory, comprising: forming a plurality of regions along a substrate in a first direction, the charge storage regions having a lower surface level: electrical storage Forming a plurality of adjacent poles above the charge storage regions, the control gates having an upper surface level; the control of the intervening charge storage region on the side adjacent to the charge storage region in the first direction and along the control In the first direction adjacent to the first direction, the side of the open pole forms an insulating member extending from at least the lower surface level of the sub-gates of the sub-gates to at least the upper surface level of the pole; and the control room Conductive isolation features are formed along the insulating members, the isolation members being insulated from the charge storage regions and the control terminals by the insulating members. 2. The method of claim </ RTI> wherein the conductive isolation members are floating. 3) The method of claim 1, wherein: each of the plurality of charge storage regions is a portion of a charge storage region of a further column extending in a second direction substantially perpendicular to/in the first direction; a spacer member extending along the one of the column charge storage regions closest to the first direction and providing shielding for the column of charge storage regions; forming the plurality of adjacent control gates including extending in the second direction a plurality of word lines, wherein each word line is formed over a corresponding column of charge storage regions extending in the second direction; and 127821.doc 200845313 χ method further comprising forming at each of the isolation members The isolation &quot; element provides an electrical connection between the word lines above the column of charge storage regions that are closest in the first direction. The method of claim 3, wherein: the electrical connection, the second &amp; the first charge of the charge storage region of the word line of the word line and the corresponding column of the word line of the word line Store a portion of the £ field between them. 5. The method of claim 3, wherein: the electrical connection is provided by a portion of a last portion of the charge storage region of the charge storage region of the corresponding column of the word line that extends beyond the word line. The storage area is one of the charge storage areas farthest from the control circuit of the word line. 6. The method of claim 3, wherein: the non-volatile $comprising body comprises a first plurality of bit lines having substantially equal intervals therebetween and a brother having substantially equal intervals therebetween a plurality of bit lines; a last bit line of one of the first plurality of bit lines is adjacent to a first bit line of the second plurality of bit lines, the last bit line and the first bit line The bit line has an interval between the substantially equal interval between the bit line of the first plurality of bit lines and the bit lines of the second plurality of bit lines; and The electrical connection is provided by the larger spacing between the last bit line of the first plurality of bit lines and the first bit line of the second plurality of bit lines. 127821.doc -2- 200845313 7 - The method of claim 1, wherein the first direction corresponds to a flash memory device formed by the plurality of charge storage areas and the plurality of control gates The string-conducting member includes: for each pair of charge storage regions and control gates adjacent in the first direction, along the m-line side of the storage region and the pair - - (d) one of the interpoles of the first bit line side to form a -first insulating member, along the pair - the first bit line side of one of the second charge storage regions and one of the pair of second control gates Forming a second insulating member on a first bit line side; and: forming the conductive isolation member includes, for each pair, "L the secret member forming a ---isolation member and along the second insulation; ;;: a brother and two isolation components. Wind 8 · The method of claim 1, wherein: the first direction corresponds to one of the flash memory devices formed by the plurality of charge storage regions a digital spool; a medium I-position-insulated component, For every ten electrical storage regions and control gates adjacent in the first direction, along the pair of - the first-bit line side and one of the pair of _ control gates =: electricity =::: a first insulating member, and forming a second insulation along a first line of the pair of the first product line and a pair of the pair of gates 坌And the forming the conductive isolating member comprises, for each of the pair, forming a single insulating member between the insulating member and the second insulating member in the first - 127821.doc 200845313. The plurality of charge storage regions and the plurality of control gates form a storage element of a NAND string. 1 A non-volatile memory system comprising a plurality of adjacent charge storage regions along a substrate Formed in a first direction, the charge storage regions having a lower surface level and an upper surface level; a plurality of adjacent control gates formed over the plurality of charge storage regions in the first direction; the control gates having an upper surface level; and an insulating member along the charge storage regions a direction from the side of the adjacent charge storage region and along the side of the control gates in the first direction to the adjacent control gates, the insulating members from at least the other storage regions a horizontal plane between the surface level and the upper surface level extends to the upper surface level of the control gate; and a conductive isolation member along the side of the insulating member facing the first direction The components are insulated from the charge storage regions and the control gates by the insulating members. 11. The non-volatile memory system of claim 10, wherein the dedicated conductive isolation component is floating. 12. The non-volatile memory system of claim 10, further comprising: a column of charge storage regions formed in a direction of a line substantially perpendicular to the _3 direction of 127821.doc 200845313, the plurality of Each charge storage region of the charge storage region is a portion of the respective columns in the column, the _ direction is a bit line direction; and a μ sub-line extending in the direction of the word line, wherein each word The lines extend across a corresponding column of charge storage regions; wherein each of the insulating members is along a - bit line side of each of the charge storage regions of each of the respective columns and a bit line side of the corresponding word line of the respective column Extending in the direction of the sub-line; wherein each of the conductive isolation members extends in the second direction along one of the insulating members; wherein each of the isolation members includes an electrical connection to one of the word lines, the word line forming Each of the isolation members is above a column of electrical storage regions that are closest in the direction of the bit line. 1 3 - The non-volatile memory system of claim 12, wherein each word line is formed by a corresponding column of control gates in the second direction. 14. The non-volatile memory system of claim 12, wherein: each of the sub-lines are formed in a second direction above a control gate of a respective column and includes one of the control gates to their respective columns . 1. The non-volatile memory system of claim 12, wherein the electrical connection is provided at a portion of the word charge line extending beyond a last charge storage region of one of the charge storage regions of the respective column, the last The charge storage area is one of the charge storage areas farthest from the control circuit of the word line. The non-volatile memory system of claim 12, wherein: the electrical connection is provided by a charge storage region of the word line between the control circuit of the word line and the corresponding column of the word line. At a portion between one of the first charge storage regions. 1 7. The non-volatile memory system of claim 12, wherein: The non-volatile memory system includes a first plurality of bit lines having substantially equal intervals therebetween and a second plurality of bit lines having substantially equal intervals therebetween; One of the last bit lines of the bit line is adjacent to the first bit line of one of the second plurality of bit lines, and the last bit line and the first line 70 have a ratio therebetween The substantially equal interval between the bit line of the first plurality of bit lines and the bit line of the second plurality of bit lines; and the last of the first plurality of bit lines The electrical connection is provided by the larger spacing between the bit line and the first bit line of the second plurality of bit lines. 18. The non-volatile memory system of claim 1, wherein: the first direction corresponds to one of nAND strings of one of flash memory devices formed by the plurality of charge storage regions and the plurality of control gates a bit line axis; the insulating members include, for each pair of charge storage regions and control gates adjacent in the first direction, along a first bit of the first one of the pair a first insulating member on the line side and one of the pair of first control gates on the first bit line side, and along one of the pair _ ★ 柯 127821.doc -6 - 200845313 storage area - first a bit line side and a pair of second insulating members on the first bit line side of the second control closed end, and the conductive isolating members include, for the per-pair, along the first insulating member One of the first isolation member and the second isolation member along one of the second insulation members. 19. The non-volatile memory system of claim 1, wherein the fourth direction corresponds to one of the NAND strings of the flash memory device formed by the plurality of charge storage regions and the plurality of control gates a bit line axis; the insulating members include, for each of the pair of charge storage regions adjacent to the first direction, and (4) a gate, a region along the -bit line side of the region and the pair of a first one insulating member on one side of the one line, and a first bit line side along a first charge storage region of the pair and a first bit line of the second control idler of the pair a second insulating member on the side; and The conductive isolation members include, for each pair, a "single-isolation member" between the first insulation member and the second insulation member. 20. The non-volatile memory system of 1G, wherein the step further comprises: 1 NAND# of the volatile storage element, each of the non-volatile storage elements comprising (4) the charge storage area and the One of the controls. 127821.doc