200844462 九、發明說明 【發明所屬之技術領域】 本發明係關於半導體晶片（以下，簡稱爲「晶片」） 之動作時之電路塊之電流測定技術。 【先前技術】 近年來’因爲半導體處理技術之提升，最小加工尺寸 進一步朝微細化發展。結果，配載於1個晶片之電晶體數 增加，將電腦之主要機能塡埋於1個晶片埋之S 〇 C ( System On a Chip )已是一般的情形。SoC，係將微處理 器、界面控制器、多媒體信號處理器、記憶體等之機能塊 (電路塊）層積於1晶片者，縮小安裝必要面積，成本亦 遠低於具有同等機能之複數晶片之系統。進化成高積體化 之SoC，一方面，隨著電晶體數之增加，而發生消耗電流 增大之問題。消耗電流之增加，導致晶片之熱發生量增加 ，而降低晶片之信賴性。此外，攜帶型機器等時，會減少 電池驅動時間。層積於晶片之電晶體數增加、及電晶體之 漏電流隨著微細化而增大，成爲消耗電流增大的主要原因 。消耗電流之種類，可以分成DC電流及AC電流之2種 。DC電流係所謂漏電流，電路未動作之狀態時，係供給 電源電壓就會流過之電流。另一.方面，AC電流係電晶體 之充放電電流，係電路動作時所消耗之電流（動作時電流 )。傳統上，爲了減少消耗電流，將注意力集中於如何減 少漏電流。以下，以 S 〇 C之漏電流之降低手法爲例進行 200844462 說明。 S〇C，係分割成各機能之電路塊之集合體。觀察某一 瞬間之SoC之動作狀態，並非全部電路都在執行動作。 因爲，只要滿足要求之機能之電路塊執行動作即可。所以 ，藉由切斷對未使用之電路的電源供給，可以避免該電路 塊之漏電流。本手法如專利文獻1所述。 此外，以對分析、測試、或控制之回饋爲目的，必須 應用到任一電路塊流過多少電流之測定技術。該等技術如 專利文獻2、3所述。專利文獻2所記載之手法，係於電 源線與各電路間及接地線之各電路間之至少其中一^方配設 開關手段，測定各電路之消耗電流時，使上述開關手段處 於切斷狀態，將測定機器連結至配設於開關手段之兩端之 墊間來測定消耗電流之手法。專利文獻3所記載者，係具 有用以切斷配設於各分支電路之電流之開關手段、用以檢 測該分支電路之電源電流之檢測手段、及對應該檢測手段 之輸出來控制上述開關手段之測試手段。 最近，對SoC所要求之機能擴大，某一瞬間進行觀 察時，執行動作之電晶體數增加，結果，動作時之電流也 變大成無法忽視的程度。尤其是，攜帶型機器等時，因爲 至少要降低消耗電流之要求，與漏電流相同，動作時電流 之降低也變得更爲重要。此外，測定某一電路塊消費多少 動作時電流的手法也同樣變得更爲重要。 [專利文獻1]日本特開2003-218682號公報 [專利文獻2]日本特開昭63 -93 1 42號公報 -6 - 200844462 [專利文獻3]日本特開平5-288798號公報 【發明內容】 到目前爲止之動作時電流之測定時，通常以外部之測 定器測定流過晶片之電源銷之電流。然而，該手法可以測 定晶片整體之動作時電流，然而，無法測定晶片之測試模 式以外之動作（通常動作）之電路塊之電流（「晶載電流 」）。上述專利文獻1〜3無法解決此問題。 本發明之目的係在提供，以測定晶片爲通常動作狀態 之電路塊之電流爲目的之技術。 本發明之前述及其他目的及新型特徵，可以由本說明 書之記述及添錄圖式獲得了解。 本專利申請之發明當中之具代表性者，簡單說明如下 〇 亦即，含有具有所定機能之電路塊、及可對上述電路 塊提供動作用電源之電源開關時，求取上述電源開關處於 導通狀態之上述電源開關之端子間電壓，依據上述電源開 關之端子間電壓及上述電源開關之導通電阻，計算流過上 述電路塊之電流。 本專利申請之發明當中之具代表性者可得到之效果， 簡單說明如下。 亦即，可以測定晶片爲通常動作狀態之電路塊之電流 200844462 【實施方式】 1.具代表性之實施形態 首先，針對本專利申請之發明之具代表性的實施形態 進行槪要說明。針對具代表性的實施形態之槪要說明中， 附有括弧之參照圖式之參照符號，只是附有該符號之構成 要素之槪念所含有者之例示。 [1 ]本發明之代表性實施形態之晶載電流測定方法， 係含有具有所定機能之電路塊（C 1 )、及可對上述電路塊 提供動作用電源之電源開關（PSW1 )的半導體積體電路 (SoC )，配設著求取上述電源開關處於導通狀態之上述 電源開關之端子間電壓之第1處理；及依據上述電源開關 之端子間電壓及上述電源開關之導通電阻，計算流過上述 電路塊之電流之第2處理。 依據上述之構成，求取上述電源開關處於導通狀態之 上述電源開關之端子間電壓，依據上述電源開關之端子間 電壓及上述電源開關之導通電阻，計算流過上述電路塊之 電流。藉此，可實施晶片爲通常動作狀態之電路塊之電流 測定。 [2]此時，藉由將上述第2處理所得到之電流計算結 果，介由上述半導體積體電路之外部端子輸出至外部，可 以實施上述電流計算結果之外部監視。 [3 ]其他觀點之半導體積體電路之構成，係含有··具 有所定機能之電路塊（C 1 );可對上述電路塊提供動作用 電源之電源開關（PSW1 );及依據上述電源開關處於導 200844462 通狀態之上述電源開關之端子間電壓及上述電源開關之導 通電阻，求取流過上述電路塊之電流之電流測定電路（ 100) ° 依據上述構成之半導體積體電路，電流測定電路，依 據上述電源開關處於導通狀態之上述電源開關之端子間電 壓及上述電源開關之導通電阻，求取流過上述電路塊之電 流。藉此，可實施晶片爲通常動作狀態之電路塊之電流測 定。 [4] 此時，上述電流測定電路之構成，係含有：用以 將上述電源開關處於導通狀態之上述電源開關之端子間電 壓，轉換成相對應之電流之增幅器（Amp 1 );用以將上 述增幅器之輸出信號轉換成數位信號之 AD轉換器（ ADC1);及可依據上述 AD轉換器之轉換輸出，計算流 過上述電路塊之電流之運算電路（DSP1 )。 [5] 配設著複數組之上述電路塊及對應其之上述電源 開關時，上述增幅器，係對應上述電源開關而配置著複數 個。 [6] 對應上述電源開關而配置著複數個上述增幅器時 ，上述電流測定電路，係含有柯選擇性地對上述AD轉換 器輸出上述複數之增幅器之輸出信號之多工器（MUX1 ) 。藉由此種構成，上述複數之增幅器可共有上述AD轉換 器及上述運算電路。 [7] 此外，因爲上述複數之增幅器可共有上述AD轉 換器及上述運算電路，上述電流測定電路，含有可藉由控 200844462 制上述複數之增幅器而選擇性地對上述AD轉換器輸出上 述複數之增幅器之輸出信號之控制器（CTL2 )。 [8] 上述電流測定電路之構成上係含有以下構件所構 成：用以將上述電源開關處於導通狀態之上述電源開關之 端子間電壓，轉換成相對應之振盪頻率之電壓頻率轉換電 路（VFC1 );用以將上述電壓頻率轉換電路之輸出信號 轉換成相對應之電壓之頻率電壓轉換電路（FV C );依據 上述頻率電壓轉換電路之轉換輸出，計算可流過上述電路 塊之電流之運算電路（DSP2)。 [9] 配設著複數組之上述電路塊及對應其之上述電源 開關時，係對應上述電源開關而配置著複數個配置上述電 壓頻率轉換電路。 [10] 另一其他觀點之半導體積體電路之構成，係含 有：具有所定機能之電路塊（C1);具有以電源電壓之降 壓爲目的之電晶體（MP3 )，藉由依據基準電壓控制上述 電晶體之導通電阻，用以形成上述電路塊之動作用電壓之 調整器（Reg 1 )·,以及於介由上述電晶體對上述電路塊供 應上述動作用電壓之狀態，依據上述電晶體之汲·源極間 電壓，求取流過上述電路塊之電流之電流測定電路（1 〇 〇 )° 依據上述構成之半導體積體電路，電流測定電路，於 介由上述電晶體對上述電路塊供應上述動作用電壓之狀態 ’依據上述電晶體之汲•源極間電壓，求取流過上述電路 塊之電流。藉此，可實施晶片爲通常動作狀態之電路塊之 •10- 200844462 電流測定。 [1 1 ]上述電流測定電路之構成上，係含有以下構件 所構成：用以將介由上述電晶體對上述電路塊供應上述動 作用電壓之狀態之上述電晶體之汲•源極間電壓轉換成相 對應之電流之增幅器（Ampnl );用以將上述增幅器之輸 出信號轉換成數位信號之AD轉換器（ADC1 );及依據 上述AD轉換器之轉換輸出，計算可流過上述電路塊之電 流之運算電路（100)。 [1 2]配設著複數組之上述電路塊及對應其之上述調 整器時，對應上述調整器而配置著複數個上述增幅器。 2.實施形態之說明 其次，進一步針對實施形態進行詳細說明。 此外，針對實施形態說明’原則上’同一構件賦予相 同符號，並省略重複說明。此外’構成半導體積體電路裝 置之各構成要素及各信號名稱等，有時只利用賦予之符號 來進行說明。 第15圖係本發明之半導體積體電路之一例之SoC( System On a Chip)。第1圖所示之soc，並無特別限制 ，然而，係利用公知之半導體積體電路製造技術’形成例 如單晶矽基板等之一個半導體基板。該S 〇 C，於使用者系 統，係結合於外部記憶體MEM ’利用SoC之內部邏輯電 路LC，可實施上述外部記憶體MEM之存取。 第1圖係上述內部邏輯電路LC之構成例。 -11 - 200844462 上述內部邏輯電路LC，係含有··複數之電源區域 Areal、Area2、…、AreaN;及用以測定流過上述複數電 源區域Areal、Area2、…、AreaN所含有之電路塊C1之 電流之電流測定電路1〇〇。上述複數電源區域 Areal、[Technical Field] The present invention relates to a current measuring technique for a circuit block in the operation of a semiconductor wafer (hereinafter simply referred to as "wafer"). [Prior Art] In recent years, due to the advancement of semiconductor processing technology, the minimum processing size has further progressed toward miniaturization. As a result, the number of transistors mounted on one wafer has increased, and it has become a general case that the main function of the computer is buried in one chip buried system S 〇 C (System On a Chip). The SoC is a system in which a functional block (circuit block) such as a microprocessor, an interface controller, a multimedia signal processor, and a memory is stacked on one chip, and the necessary area is reduced, and the cost is also much lower than that of a plurality of chips having the same function. The system. The SoC evolved into a highly integrated system. On the one hand, as the number of transistors increases, the current consumption increases. The increase in current consumption leads to an increase in the amount of heat generated by the wafer, which reduces the reliability of the wafer. In addition, when the portable device or the like is used, the battery driving time is reduced. The number of transistors stacked on the wafer increases, and the leakage current of the transistor increases with miniaturization, which is a cause of an increase in current consumption. The type of current consumption can be divided into two types of DC current and AC current. The DC current is a so-called leakage current. When the circuit is not operating, it supplies a current through which the power supply voltage flows. On the other hand, the charge and discharge current of the AC current system transistor is the current consumed during the operation of the circuit (current during operation). Traditionally, in order to reduce current consumption, attention has been focused on how to reduce leakage current. In the following, the method of reducing the leakage current of S 〇 C is taken as an example for 200844462. S〇C is a collection of circuit blocks that are divided into functions. Observing the action state of the SoC at a certain moment, not all circuits are performing the action. Because, as long as the circuit block that satisfies the required function can perform the action. Therefore, the leakage current of the circuit block can be avoided by cutting off the power supply to the unused circuit. This method is as described in Patent Document 1. In addition, for the purpose of feedback for analysis, testing, or control, it is necessary to apply the measurement technique of how much current flows through any of the circuit blocks. These techniques are as described in Patent Documents 2 and 3. In the method described in Patent Document 2, at least one of the switching means is disposed between the power supply line and each of the circuits and the circuits of the grounding line, and when the current consumption of each circuit is measured, the switching means is turned off. The method of measuring the current consumption by connecting the measuring device to the mats disposed at both ends of the switching means. Patent Document 3 includes a switching means for cutting a current disposed in each branch circuit, a detecting means for detecting a power supply current of the branch circuit, and an output corresponding to the detecting means to control the switching means. The means of testing. Recently, the functions required for the SoC have been expanded, and when the observation is performed at a certain moment, the number of transistors that perform the operation increases, and as a result, the current during the operation becomes large and cannot be ignored. In particular, when a portable type of machine or the like is required to reduce the current consumption at least, as with the leakage current, the current reduction during operation becomes more important. In addition, the method of measuring the current consumption of a certain circuit block is also more important. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. In the measurement of the current during the operation so far, the current flowing through the power supply pin of the wafer is usually measured by an external measuring device. However, this method can measure the current during the operation of the entire wafer, however, it is impossible to measure the current of the circuit block ("crystal current") of the operation (normal operation) other than the test mode of the wafer. The above Patent Documents 1 to 3 cannot solve this problem. SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for measuring a current of a circuit block in which a wafer is in a normal operation state. The foregoing and other objects and novel features of the invention will be apparent from the description and appended claims. The representative of the invention of the present patent application briefly describes the following, that is, when a circuit block having a predetermined function and a power switch capable of supplying an operation power supply to the circuit block are provided, the power switch is turned on. The voltage between the terminals of the power switch is calculated according to the voltage between the terminals of the power switch and the on-resistance of the power switch, and the current flowing through the circuit block is calculated. The effects obtainable by the representative of the invention of the present patent application are briefly described below. That is, the current of the circuit block in which the wafer is in the normal operation state can be measured. 200844462 [Embodiment] 1. Representative Embodiment First, a representative embodiment of the invention of the present patent application will be briefly described. In the brief description of the representative embodiments, the reference symbols attached to the reference drawings of the parentheses are merely examples of those in which the constituent elements of the symbols are attached. [1] A method of measuring a crystal carrying current according to a representative embodiment of the present invention includes a semiconductor block having a predetermined function (C1) and a power switch (PSW1) capable of supplying an operating power supply to the circuit block. a circuit (SoC) configured to perform a first process of determining a voltage between terminals of the power switch in which the power switch is in an on state; and calculating a flow rate according to a voltage between terminals of the power switch and an on-resistance of the power switch The second processing of the current of the circuit block. According to the above configuration, the voltage between the terminals of the power switch in which the power switch is turned on is obtained, and the current flowing through the circuit block is calculated based on the voltage between the terminals of the power switch and the on-resistance of the power switch. Thereby, the current measurement of the circuit block in the normal operating state of the wafer can be performed. [2] At this time, by calculating the current obtained by the second processing, the external terminal of the semiconductor integrated circuit is output to the outside, and external monitoring of the current calculation result can be performed. [3] The semiconductor integrated circuit of other points of view includes a circuit block (C 1 ) having a predetermined function; a power switch (PSW1) capable of supplying an operating power supply to the circuit block; and The current measurement circuit (100) for determining the current flowing through the circuit block is determined according to the voltage between the terminals of the power switch and the power supply switch of the above-mentioned power switch. The semiconductor integrated circuit and the current measuring circuit are configured according to the above configuration. And determining a current flowing through the circuit block according to a voltage between terminals of the power switch in which the power switch is in an on state and an on-resistance of the power switch. Thereby, the current measurement of the circuit block in which the wafer is in a normal operation state can be performed. [4] In this case, the current measuring circuit is configured to include an amplifier (Amp 1 ) for converting a voltage between terminals of the power switch for turning on the power switch to a corresponding current; An AD converter (ADC1) for converting an output signal of the amplifier to a digital signal; and an arithmetic circuit (DSP1) for calculating a current flowing through the circuit block according to a conversion output of the AD converter. [5] When the above-mentioned circuit block of the complex array and the above-described power supply switch are disposed, the above-mentioned amplifiers are arranged in plurality corresponding to the power switch. [6] When a plurality of the amplifiers are arranged corresponding to the power switch, the current measuring circuit includes a multiplexer (MUX1) for selectively outputting an output signal of the plurality of amplifiers to the AD converter. With such a configuration, the plurality of amplifiers can share the AD converter and the arithmetic circuit. [7] Further, since the plurality of amplifiers can share the AD converter and the arithmetic circuit, the current measuring circuit includes the above-mentioned plurality of amplifiers capable of selectively outputting the above-mentioned AD converter by controlling the above-mentioned multiple amplifiers of 200844462 A controller (CTL2) for output signals of a plurality of amplifiers. [8] The current measuring circuit is configured to include a voltage frequency conversion circuit (VFC1) for converting a voltage between terminals of the power switch in which the power switch is in an on state to a corresponding oscillation frequency. a frequency-to-voltage conversion circuit (FV C ) for converting an output signal of the voltage-frequency conversion circuit into a corresponding voltage; and an operation circuit for calculating a current that can flow through the circuit block according to a conversion output of the frequency-voltage conversion circuit (DSP2). [9] When the above-mentioned circuit block of the complex array and the power supply switch corresponding thereto are disposed, a plurality of the voltage-frequency conversion circuits are arranged corresponding to the power switch. [10] Another aspect of the semiconductor integrated circuit consists of: a circuit block having a predetermined function (C1); a transistor (MP3) having a voltage drop for power supply voltage, controlled by a reference voltage The on-resistance of the transistor is used to form a regulator (Reg 1 ) of the operating voltage of the circuit block, and a state in which the operating voltage is supplied to the circuit block via the transistor, according to the transistor a current measuring circuit for calculating a current flowing through the circuit block by a voltage between the source and the source (1 〇〇). According to the semiconductor integrated circuit configured as described above, a current measuring circuit supplies the circuit block via the transistor. The state of the above-mentioned operating voltage 'determines the current flowing through the circuit block based on the voltage between the source and the source of the transistor. Thereby, it is possible to carry out the current measurement of the circuit block in the normal operating state of the wafer. [1 1] The current measuring circuit is configured to include a voltage-to-source voltage conversion of the transistor in a state in which the operating voltage is supplied to the circuit block via the transistor. a corresponding current booster (Ampnl); an AD converter (ADC1) for converting the output signal of the booster into a digital signal; and calculating the flow through the circuit block according to the conversion output of the AD converter The current operation circuit (100). [1 2] When the above-described circuit block of the complex array and the above-described adjuster are disposed, a plurality of the above-described amplifiers are disposed corresponding to the adjuster. 2. Description of Embodiments Next, the embodiments will be described in detail. In the embodiment, the same components are denoted by the same reference numerals, and the description thereof will not be repeated. In addition, each component constituting the semiconductor integrated circuit device, each signal name, and the like may be described using only the reference numerals. Fig. 15 is a SoC (System On a Chip) which is an example of the semiconductor integrated circuit of the present invention. The soc shown in Fig. 1 is not particularly limited. However, a semiconductor substrate such as a single crystal germanium substrate is formed by a known semiconductor integrated circuit manufacturing technique. The S 〇 C, in the user system, is coupled to the external memory MEM ’ by the internal logic circuit LC of the SoC to perform access of the external memory MEM. Fig. 1 is a configuration example of the above internal logic circuit LC. -11 - 200844462 The internal logic circuit LC includes a power supply area of Area, Area 2, ..., AreaN; and a circuit block C1 included in the complex power supply areas Area, Area 2, ..., AreaN Current current measuring circuit 1〇〇. The above multiple power supply area Areal,
Area2.....AreaN所含有之電路塊C 1並無特別限制，然 而，係如CPU (中央處理裝置）、基頻處理器、應用處理 機記憶體、或中斷處理控制器等之分別具有所定機能之機 能模組。 電源區域 Area 1、Area2、…、AreaN，高電位側電源 (VDD )及其他電源區域所使用之電源分別供應互相獨立 之不同接地電源VSS。此外，該等電源區域，藉由分別個 別控制配設於各電源區域之電源開關（Areal爲PSW1) ，可實施各電路塊C1之電源切斷。電源開關係η通道型 MOS電晶體，然而，並無特別限制。上述電流測定電路 100含有增幅器Ampl〜AmpN、多工器MUX1、MUX控制 器CTL1、AD (類比•數位）轉換器ADC1、數位信號處 理器DSP1、以及唯讀記憶體ROM1。一般而言，上述增 幅器 Ampl〜AmpN及 A D C 1爲類比電路。上述增幅器 Ampl〜AmpN，在對應之電源區域 Areal、Area2、…、 AreaN之電源開關PS W1爲導通時，具有將因爲流過汲· 源極間之電流1所產生之端子電壓，轉換成相對應之電流 之機能。多工器MUX1，選擇性地將上述增幅器Ampl〜 AmpN之輸出端子連結至後段之AD轉換器ADC1。該動 作係由MUX控制器CTL1所控制。上述Ad轉換器ADC1 •12- 200844462 之輸出信號，被傳送至後段之數位信號處理器DSP1。該 數位信號處理器DSP1，依據上述AD轉換器ADC1之輸 出信號，計算流過上述電源區域 Areal、Area2.....The circuit block C 1 included in Area2.....AreaN is not particularly limited, however, it is respectively such as a CPU (Central Processing Unit), a baseband processor, an application processor memory, or an interrupt processing controller, etc., respectively. The functional module of the function. Power supply area Area 1, Area2, ..., AreaN, high-potential side power supply (VDD) and other power supply areas are supplied with different grounding power supplies VSS. Further, in the power supply areas, the power switches (Areal is PSW1) disposed in the respective power supply areas are individually controlled, and the power supply of each of the circuit blocks C1 can be cut off. The power supply is related to the n-channel type MOS transistor, however, there is no particular limitation. The current measuring circuit 100 includes amplifiers Ampl to AmpN, a multiplexer MUX1, a MUX controller CTL1, an AD (analog digital converter) ADC1, a digital signal processor DSP1, and a read-only memory ROM1. In general, the above-mentioned amplifiers Ampl~AmpN and A D C 1 are analog circuits. The amplifiers Ampl to AmpN have a terminal voltage generated by a current 1 flowing between the 汲 and the source, and are converted into phases when the power switches PS W1 of the corresponding power regions Area, Area 2, ..., Area N are turned on. Corresponding to the function of the current. The multiplexer MUX1 selectively connects the output terminals of the boosters Ampl to AmpN to the AD converter ADC1 of the subsequent stage. This action is controlled by the MUX controller CTL1. The output signals of the above Ad converters ADC1 • 12 - 200844462 are transmitted to the digital signal processor DSP1 of the latter stage. The digital signal processor DSP1 calculates the flow through the power supply area Area1, Area2..... according to the output signal of the AD converter ADC1.
AreaN之電源開關PSW1之電流，亦即，計算流過對應之 電路塊C 1之電流。於ROM 1，記憶著設計時爲已知之電 源開關之導通電阻R、及設計時爲已知之增幅器之增幅係 數α之資訊。其次，計算電流時，可配合需要，參照 ROM 1之記憶資訊。ROM 1，亦可以由遮罩唯讀記憶體等 之唯讀記憶體、或快閃記憶體等之非揮發性記憶體所構成 。數位信號處理器DSP1之輸出信號Doutl，可以藉由 SoC之外部端子Output實施外部輸出。此外，數位信號 處理器DSP1之輸出信號Doiitl，可配合需要，傳送給上 述電源區域 Areal、Area2、…、AreaN，而可被利用於回 饋控制。例如，電源區域AreaN若爲中斷處理控制器，規 格以上之電流値流過時，通知配載於其他電源區域之CPU ，調節晶片整體之電源供給電壓、動作頻率、或處理作業 數等，而以使電流値降低成規格以下之方式進行控制。 本例時，於晶片爲通常動作時，亦可如以所示，測定 流過各電路塊C 1之電流。 流過電路塊C1之電流，會先被電源開關PSW1集中 。所以，利用測定流過電源開關之電流1，可以求取流過 電路塊C1之電流。傳統技術時，測定流過電路塊之電流 也是使用電源開關，然而，其只具有選擇被測定電路塊之 機能。因此’只導通或斷開欲測定之電路塊之電源開關， -13- 200844462 而只驅動該電路塊。亦即，晶片爲通常動作（一般通常動 作時’係驅動複數之電路塊）狀態時，無法實施各個電路 塊之電流測定。然而，依據本例，可一邊對全部或部分電 源區域供給電源，使晶片執行通常動作，一邊實施各個電 路塊C1之電流測定。 此處’參照第6圖之流程圖，針對本例之電流測定步 驟進行說明。 首先’使對應於測定對象之電路塊C 1之電源開關 p s W 1導通（s T 1 )。藉此，使動作電流1流過電源開關 PSW1，藉由電源開關PSW1之導通電阻產生電壓下降（ ST2)。藉由該電壓下降，使電源開關PSW1之電路塊側 之節點（Vd )、及接地電位側之節點（Vs )間之電壓， 傳送至對應之增幅器Ampl，於該增幅器Ampl，實施電 壓電流轉換（ST3 )。其次，藉由多工器MUX1，增幅器 Ampl之輸出信號被選擇性地傳送至AD轉換器ADC1 ( S T 4 )，其係於被轉換成數位信號後（s T 5 )，被傳送至 數位信號處理器D S P 1。數位信號處理器D S P 1，依據電源 開關PSW1之端子電壓、及電源開關PSW1之導通電阻， 計算流過電源開關p s W 1之電流，亦即，計算流過電路塊 C1之電流（ST6)。電源開關PSW1之導通電阻之資訊， 被預先儲存於ROM1，可藉由數位信號處理器DSP1進行 參照。流過電路塊C1之電流，可以將電源開關之電路塊 側之節點（Vd )、及接地電位側之節點（Vs )間之電壓 除以設計時已知之電源開關（PSW1 )之導通電阻來求取 -14- 200844462 。上述之電流測定時，因爲全部電源區域之電源開關可以 爲導通狀態，晶片爲通常動作時可以實施各電路塊之電流 測定。上述數位信號處理器DSP1之運算結果，被回饋至 內部電路、或介由外部端子Output被輸出至外部（ST7 ) 〇 因爲實際晶片之 Vd-Vs間之電壓，小於電源開關 PSW1之導通電阻，預估信號強度會小10mV程度。因此 ，若直接將該信號導入晶片內，可能會有雜訊混入。所以 ，藉由將增幅器Amp 1〜AmpN設置於對應之電路塊之附 近，可儘量縮短電源開關及至對應其之增幅器 Ampl〜 AmpN爲止之信號傳送路徑的長度。藉此，即使有右干雜 訊混入，亦可實施高精度之電流測定。 第2圖係上述增幅器Ampl〜AmpN之構成例。 本增幅器，大致而言，係由實施〇utl所輸入之電壓 之電壓轉換之源極隨耦電路SF 1、及由將電壓轉換成電流 信號之P通道型MOS電晶體MP1、MP2所形成之電流反 射鏡電路CM所構成。該電路之增幅率α，大致可以p通 道型MOS電晶體ΜΡ1與ΜΡ2之元件尺寸比來表示。 Vbiasl係用以驅動SF1之偏壓信號。ΜΝ1係用以將SF1 之輸出電壓信號轉換成電流信號之N通道型MOS電晶體 。本增幅器因爲係類比電路，電源電壓爲高於數位電路之 VDD之電壓的VCC (約3V)。 第3圖係上述SoC之主要部位之配置。 電源區域，係由Areal〜Area5之5個所構成。基本 -15- 200844462 上，電源開關（pswi〜psW5)係存在於各電路塊之兩側 。各電源區域係由所謂數位電路所構成’增幅器Amp 1〜 AmpN (類比電路）被設置於類比電路（Anl〜An55 )附 近。藉此，於晶片內，可縮短導入微弱信號之距離’而可 實現高精度之測定。AD轉換器AD C 1 ’因爲可以由晶片 所共有，故被設置於晶片之某處。DSP1，可配設於電源 區域Areal〜Area5之何一。 第4圖係上述電源開關周邊之配置。 第4圖中，延伸於X方向之配線，係利用第1金屬層 Ml實施之配線，係VDD電源線VDDM1及虛擬接地（ VSSM )電源線 V S S MM 1之配線。V S S Μ，係可藉由後述 之電源開關而與真的接地（V S S )進行切斷之電源線。延 伸於y方向之配線，不同於配線於X方向之第1金屬層， 例如，係利用第2金屬層M2實施之配線。因爲VDD及 V S S Μ係大區域配線於電源區域，藉由連結規則之縱幹線 (VDDM2、VSSMM2)來實現低電阻化。本圖時，只分別 圖示1條，然而，爲了使以內部之邏輯電路之動作速度等 而供應必要量之電流時之電壓下降位於規定値以內，可採 用規則且最佳之配置。於電源區域內，配置著被稱爲標準 電池之反相器電路（1NV )、反及電路（NAND )、非或 電路（NOR )、正反器（FF )等之基本電路。電源開關 PSW係由汲極側擴散層DINV、閘極GATE1、源極側擴散 層SINV所形成。此外，PSW係由通常NMOS所形成。 DINV係以接點連結於VSSMM1，SINV係以接點連結於新 •16- 200844462 的接地V S S。V S S Μ係相當於第1圖之節點，V S S係對應 於V S節點。通常，V S S及V S S Μ，因爲係連結於規則之 縱幹線，阻抗較低。因此，Vd及Vs之探針點，VSS、 VSSM分別爲1點即足夠。另一方面，配置複數點之探針 點之優點，係可吸收電源區域內所產生之些微電壓誤差。 一般而言，電源開關之閘極氧化膜之形成厚度’大於 電源區域內之標準電池。電源開關斷開時，將GATE 1設 定成低電平（0V)，導通時則設定成高電平（約1.5V) 。藉此，控制虛擬接地VSSM及新的接地VSS之連結關 係。 第5圖係，第4圖之A-A，、B-B’之剖面。 第5 ( a)圖係A-A’之剖面。係由形成於P型基板（ Psub )上之N型井（Nwell )、及形成於Nwell上之P型 井（P W1、Pwell )所形成之3重井構成。電源開關係形 成於於P W1之N通道型MO S電晶體。經由元件分離區域 (ST1 )，形成相當於電源區域內之標準電池一部分之 PMOS。GP、DP、SP分別相當於閘極、汲極、源極。 第5(b)圖係第4圖之B-B’之剖面。與前述相同， 係3重井，電源開關之構成亦相同。係介由ST1形成相當 於標準電池一部分之NMOS。GN、DN、SN分別相當於閘 極、汲極、源極。 依據上述之例，可以得到以下之作用效果。 (1 )分割成各機能之電路塊之集合體SoC，晶片爲 通常動作狀態之下，可以實施各電路塊所消耗之電流値之 -17- 200844462 評估、測定、及分析。此外’以測定到之電流値爲基礎’ 藉由回饋至晶片控制，可以提昇晶片之信賴性。 (2 )因爲實際晶片之Vd-Vs間之電壓，小於電源開 關PS W1之導通電阻，預估信號強度會小1 〇mV程度，將 增幅器Ampl〜AmpN設置於對應之電路塊之附近，可儘 量縮短電源開關及至對應其之增幅器Ampl〜AmpN爲止 之信號傳送路徑的長度，即使有若干雜訊混入，亦可實施 高精度之電流測定。 (3 )規格以上之電流持續流過電路塊時，晶片之熱 發生量會增大，而降低晶片之信賴性，故如上面所述，測 定通常動作時之電路塊之電流，有利於提高晶片之信賴性 。此外，因爲可測定通常動作時之各電路塊之電流，可晶 片之評估分析較爲容易。 第7圖係上述SoC之主要部位之其他構成例。 第7圖所示之構成與第1圖所示者之較大差異，係省 略多工器MUX，藉由利用來自控制器CTL2之控制線SIG 來直接控制增幅器Ampcl〜AmpcN，而省略多工器MUX 。例如，欲驅動A m p c 1時，只要使被輸入A m p c 1之S I G 成爲高電平，而其他控制線SIG則爲低電平即可。 第8圖係第7圖之增幅器Ampcl之構成例。此外， 其他增幅器也是相同構成。 電源區域Areal所輸出之Vd、Vs電壓信號之Out 1、 Out2被輸入增幅器係與第2圖所示者相同。此外，增幅 器本體AMP之構成，係第2圖所示者相同。第7圖所示 -18- 200844462 之構成時，於增幅器之電源 vcc、及接地間，新設置電 源開關（PSWAD、PSWAS )、或設置增幅器之開關（SW1 )。例如，選擇Areal時，信號線SIG1爲高電平，n通 道型MOS電晶體PSWAD、PSWAS導通，對增幅器AMP 供給電源。此外，此時，開關SW1導通，增幅器AMP之 輸出信號從輸出端子AoutX被輸出。另一方面，信號線 SIG1爲低電平時，η通道型MOS電晶體PSWAD、PSWAS 被斷開，未對增幅器AMP供給電源。此外，開關SW1亦 被斷開，防止未定義信號被輸出至AoutX。 藉由該構成，可以使只有被連結於被測定電源區域之 增幅器AMP處於動作狀態，並可抑制其他增幅器所消耗 之電流，故可降低SoC之消耗電力。 第9圖係上述S 〇C之主要部位之其他構成例。 第9圖所示之構成與第1圖所示者之較大差異，係配 設電壓頻率轉換電路VFC1、VFC2.....VFCN來取代第 1圖之增幅器，而可削減各電源區域所必要之類比電路區 域。從各電壓頻率轉換電路VFC1、VFC2.....VFCN輸 出信號Aoutfl、Aoutf2，利用後段之多工器MUX2被選擇 性地供應給頻率電壓轉換電路FVC。多工器MUX2之動作 係由控制器CTL3所控制。電壓頻率轉換電路 VFCI、 VFC2.....VFCN係以對應於分別被輸认之電壓之頻率實 施振盪。頻率電壓轉換電路FVC，對應被輸入之信號之頻 率，將其轉換成電壓。頻率電壓轉換電路FVC之輸出電 壓，被供應給後段之DSP2。 200844462 使用電壓頻率轉換電路VFC時，從各電源流域被輸 入之信號分成3個系統。亦即，來自高電位側電源VDD 之電壓電平信號〇ut3、及電源開關PSW1之兩端信號 Out4、Out5。需要電壓電平信號〇ut3之理由，係因爲電 壓頻率轉換電路之特性，以Vd-Vs間程度之小電壓無法執 行動作。本3個系統之信號之處理之手法如下所述。 第10圖係上述電壓頻率轉換電路VFC1之構成例。 此外，其他電源區域之電壓頻率轉換電路亦爲相同構成。 上述電壓頻率轉換電路VFC1，具有2台連結著奇數 個反相器INV之環式振盪器。該環式振盪器，係以與被 供應之電源電壓（P通道型MOS電晶體之源極電位）、 及接地電壓（η通道型MOS電晶體之源極電位）之差大 致成比例之頻率進行振盪係眾所皆知。所以，將高電位側 電源VDD及節點Vd電壓、高電位側電源VDD及節點Vs 電壓當做輸入，將各差分電壓轉換成頻率並輸出。最後， 利用該頻率之差分，計算Vd_ Vs電壓間之差分，來求取流 過電源開關PSW1之電流。 第10圖之上段之環式振盪器之輸入係〇ut3 ( VDD ) 、Out4 (Vd)，第10圖中之下段之環式振盪器之輸入係 Out3 ( VDD ) 、Out5 ( Vs )。以與各電壓差分大致成比例 之頻率振動之波形被輸出至輸出Aoutfl〜Aoutf2。此外， 因爲電壓頻率轉換電路VFC1所輸出之信號係環式振盪器 之振盪信號，即使有若干雜訊混入，對其頻率的影響也較 小，故可實施高精度之電流測定。輸出 Aoutfl〜A〇utf2 -20- 200844462 介由多工器MUX2被輸入至頻率電壓轉換電路FVC° 第1 1圖係上述頻率電壓轉換電路FVC之構成例。 上述頻率電壓轉換電路 FVC時，被輸入之信號 Aoutfl及Aoutf2，於內部之頻率電壓轉換電路FVCC，被 轉換成依據頻率之電壓。此外’該等電壓’於後段之增幅 器AMP被轉換成電流，再於後段之AD轉換器ADC被轉 換成數位信號。亦即，被輸出至 DSPinl之信號’係 VDD-Vd間之電壓資訊，被輸出至DSPin2之資訊，係 V D D - V s間之電壓資訊。依據該等資訊，數位信號處理器 DSP2計算Vd-Vs間之電壓，以下，與第1圖所示者相同 ，計算流過被測定對象之電源開關之電流値。 依據上述之構成，可以標準電池形成倂設於各電源區 域之V F C電路，而減少晶片之面積。此外’因爲v F c所 輸出之資訊爲頻率，故不易受到雜訊之影響’而可實施高 精度之電流測定。 第12圖係上述SoC之主要部之其他構成例。 第12圖所示之構成與第1圖所示者之較大差異，係 利用調整器Reg 1實施對各電源區域之電路塊C1之電源 供給，介由該調整器Re g 1，實施電路塊C 1之電流測定。 使用調整器時，使用高於邏輯電路之高電位側電源電壓 VDD之電源電壓之VCC。 第13圖係電源區域Afeal之調整器之構成例。此外 ，其他電源區域之調整器亦爲相同構成。 調整器Regl係結合著基準電壓發生電路VREFC、運 21 - 200844462 算放大器（運算增幅器）OP Amp、p通道型MOS電晶體 MP3而形成。運算放大器OP Amp以節點Vrs及基準電壓 發生電路VREFC之輸出電壓爲相等之方式執行動作。例 如，Vrs若低於基準値，運算放大器OPAmp輸出低於至 當時爲止之電壓，使節點Vrs之電壓恢復成基準値爲止。 如此，對電路塊C 1供應安定之電源。SoC，於晶片動作 狀態發生激烈變化時（尤其是，重設時），亦可能因爲晶 片內部所發生之電壓下降而導致電路之錯誤動作。相對於 此，若使用調整器Reg 1，可以緩和上述之問題。流過電 路塊C1之電流，只要測定流過p通道型MOS電晶體MP3 之電流即可，與第1圖所示之電源開關時相同，將P通道 型MOS電晶體MP3之汲極側節點電壓（Vrd)、及源極 側節點電壓（Vrs )分別輸出至Out6、Out7。該輸出被傳 送至增幅器Ampnl〜AmpnN，而於該處轉換成電流。 第14圖係上述增幅器Ampnl之構成例。此外，其他 增幅器亦爲相同構成。 第14圖所示之構成與第2圖所示者之較大差異，係 輸入初段之源極隨耦電路SF2之構成。各電源區域所輸出 之信號〇ut6、Out7，因爲係接近高電壓電源之値’如第2 圖之SF1所示，p通道型MOS電晶體之該源極隨耦電路 S F 2以後之電路構成、電路動作等，與第2圖所示者相同 〇 此外，可於各電源區域，配設電源開關p s w 1。此外 ，配設調整器Re g 1、及電源開關P S W 1之雙方時，電路 -22- 200844462 塊C1之電流測定可以使用其中任一。 第16圖係本發明之第2實施例之半導體積體電路之 重要部位。本實施例時，係針對將晶片內所測定到之電流 値當做觸發器而回饋至晶片控制之機構進行記載。回饋之 目的，例如，在將晶片之溫度，亦即，晶片之最大電流抑 制於某特定値以下。半導體積體電路，若溫度上昇至某特 定値以上，機能被破壞的機率甚高。此外，封裝之放熱特 性、及依據使用環境之晶片之發熱量也會受到限制。基於 上述理由，晶片之溫度控制的實施也就變得極爲重要。以 下，針對以測定晶片內之電流將晶片之最大電流抑制於某 特定値以下之機構進行說明。 系統晶載SoC，係由資源管理器RM、CPU1、CPU2 、機能塊FBI、FB2、計時器TMR、RAM、ROM、匯流排 仲裁器ARB、中斷控制器INTA、效能檢測電路14、效能 計數器PPC、時脈頻率控制部CLK、內部匯流排BUS、電 源開關28、增幅器Amp、以及電流測定電路CD所構成。 資源管理器RM係由指令編碼器DEC、控制部CTL、電流 管理部CWM、作業管理部TSKM、以及中斷控制器INTC 所構成。電流測定電路CD係包含如前述實施例之第1圖 所示之多工器MUX1、控制器CTL1、類比數位轉換器 ADC1、唯讀記憶體ROM1、數位信號處理器DSP1之電路 。此外，本實施例時，CPU1、CPU2、FBI、FB2分別配 設於各電源區域。 第1 7圖係本發明之第2實施例之最大電流控制之槪 -23- 200844462 念。橫軸係時間，縱軸係電流値。機能塊 FB0、FBI、 FB2係分別以處理時間及電流之矩形來表示。各處理設定 著截止時間（最後期限）。此處，爲了簡化而爲相同時間 。電流値係以某時間之機能塊之合計値來表示。晶片電流 以矩形之合計面積來表示。（a )係無最大電流管理時。 因爲同時執行機能塊FB0、FB 1、FB2，故最大電流値係 各電流之合計値而較大。（b )係利用遲滯來實施最大電 流控制時，藉由遲滯機能塊FB 1、FB2之開始執行來使該 等不會與機能塊FB0被同時執行，故可降低最大電流値 。其可以藉由配合既定之電流預算、最後期限來控制開始 執行而實現。（c )係控制頻率來執行最大電流控制時， 藉由配合電流預算、最後期限而以低於機能塊FB0、FBI 、FB2之任一之時脈頻率來執行動作，而可降低最大電流 値。（b ) 、（ c )若欲進一步降低電流預算，將無法滿足 最後期限。因此，以滿足於電流預算及最後期限之任一之 方式執行控制。滿足最後期限之處理，因爲於要求時間內 完成處理，亦可稱爲即時處理。 第1 8圖係以降低時脈頻率將晶片之最大電流抑制於 某特定値以下時之流程圖。以下，針對該流程圖進行詳細 說明。以數ms等之定期時間間隔，TMR對資源管理器 RM之INTC通知中斷。接收到中斷之資源管理器RM，從 CD取得流過CPU1、CPU2、FBI、FB2之各電路塊之電流 値。同時，資源管理器RM內之TSKM，更新CPU、機能 塊之作業資訊，掌握那一機能單位正在執行何種作業。此 -24- 200844462 外，從效能計數器PPC取得各電路塊之作業進度。其次 ，資源管理器 RM，計算流過電路塊之電流値之總和 I__Sum。此時，已預先於電流管理部CWM設定著晶片容 許之最大電流値I_max。I_max設定成與晶片容許之最大 電流値相等、或其以下之値。：小於I_max時，再度 等待來自TMR之中斷。I__sum大於I_max時，以從PPC 得到之各電路塊之作業進度、及TSKM管理作業資訊爲基 礎，選擇1個以上之作業進度尙有餘裕且正在執行優先度 較低之作業之電路塊。資源管理器RM對時脈頻率控制部 CLK，傳送降低所選取之電路塊之時脈頻率之信號。其次 ，時脈頻率控制部CLK降低供應給所選取之電路塊之時 脈頻率。結果，流過晶片之電流値降低，而可抑制晶片之 溫度上昇，提昇半導體積體電路之信賴性。此外， 小於I_max時，增加時脈頻率，亦可於短時間內結束作業 之處理。 以上，係針對本發明者之發明進行具體說明，然而， 本發明並未受限於此，只要未背離其要旨之範圍，可以實 施各種變更。 以上之說明，主要係針對以本發明者之發明做爲背景 而應用於利用分野之SoC時進行說明，然而，本發明並 未受限於此，亦可廣泛地應用於各種半導體積體電路。 【圖式簡單說明】 第1圖係本發明之半導體積體電路之一例及SoC之 -25- 200844462 內部邏輯電路之構成例方塊圖。 第2圖係第1圖所示之內部邏輯電路之增幅器之構成 例電路圖。 第3圖係上述SoC之主要部位之配置說明圖。 第4圖係上述SoC之電源開關周邊之配置說明圖。 第5圖係第4圖之主要部位之剖面圖。 第6圖係上述SoC之電流測定之步驟之流程圖。 第7圖係上述SoC之主要部位之其他構成例方塊圖 〇 第8圖係第7圖之增幅器之構成例電路圖。 第9圖係上述SoC之主要部位之其他構成例方塊圖 〇 第1 0圖係第9圖之電壓頻率轉換電路之構成例電路 圖。 第1 1圖係第9圖之頻率電壓轉換電路之構成例電路 圖。 第12圖係上述SoC之主要部位之其他構成例方塊圖 〇 第1 3圖係第1 2圖所示之調整器之構成例電路圖。 第1 4圖係第1 2圖所示之增幅器之構成例電路圖。 第15圖係本發明之半導體積體電路之一例及含有 SoC之使用者系統之構成例方塊圖。 第1 6圖係本發明之第2實施形態之半導體積體電路 之一例之SoC之內部邏輯電路之構成例方塊圖。 -26- 200844462 第1 7圖係本發明之第2實施之形態之最大電力控制 之槪念圖。 第18圖係第16圖之SoC之回饋步驟之流程圖。 【主要元件符號說明】 1 0 0 :電流測定電路 ADC1 :類比數位轉換器The current of the power switch PSW1 of AreaN, that is, the current flowing through the corresponding circuit block C1. In ROM 1, the on-resistance R of the known power supply switch and the amplification factor α of the known amplifier are designed. Secondly, when calculating the current, the memory information of the ROM 1 can be referred to as needed. The ROM 1 may also be composed of a read-only memory such as a mask-reading memory or a non-volatile memory such as a flash memory. The output signal Dout1 of the digital signal processor DSP1 can be externally outputted by the external terminal Output of the SoC. In addition, the output signal Doiitl of the digital signal processor DSP1 can be transmitted to the above power supply areas Area1, Area2, ..., AreaN as needed, and can be utilized for feedback control. For example, if the power supply area AreaN is an interrupt processing controller and the current above the specification flows, the CPU that is loaded in the other power supply area is notified to adjust the power supply voltage, the operating frequency, or the number of processing operations of the entire wafer, so that The current is reduced to a level below the specification for control. In this case, when the wafer is in the normal operation, the current flowing through each of the circuit blocks C1 can be measured as shown. The current flowing through the circuit block C1 is first concentrated by the power switch PSW1. Therefore, by measuring the current 1 flowing through the power switch, the current flowing through the circuit block C1 can be obtained. In the conventional art, the current flowing through the circuit block is also measured using a power switch, however, it only has the function of selecting the circuit block to be measured. Therefore, 'only turn on or off the power switch of the circuit block to be measured, -13- 200844462 and only drive the circuit block. In other words, when the wafer is in a normal operation (generally, a circuit block that drives a plurality of circuit blocks during normal operation), current measurement of each circuit block cannot be performed. However, according to this embodiment, the current can be measured for each of the circuit blocks C1 while supplying power to all or part of the power supply regions and performing normal operations on the wafer. Here, the current measurement step of this example will be described with reference to the flowchart of Fig. 6. First, the power switch p s W 1 corresponding to the circuit block C 1 of the measurement target is turned on (s T 1 ). Thereby, the operating current 1 is caused to flow through the power switch PSW1, and the voltage drop (ST2) is generated by the on-resistance of the power switch PSW1. By the voltage drop, the voltage between the node (Vd) on the circuit block side of the power switch PSW1 and the node (Vs) on the ground potential side is transmitted to the corresponding amplifier Ampl, and the voltage and current are applied to the amplifier Ampl. Conversion (ST3). Secondly, with the multiplexer MUX1, the output signal of the amplifier Ampl is selectively transmitted to the AD converter ADC1 (ST 4 ), which is converted into a digital signal (s T 5 ) and transmitted to the digital signal. Processor DSP 1. The digital signal processor D S P 1, calculates the current flowing through the power switch p s W 1 according to the terminal voltage of the power switch PSW1 and the on-resistance of the power switch PSW1, that is, calculates the current flowing through the circuit block C1 (ST6). The information of the on-resistance of the power switch PSW1 is pre-stored in the ROM 1 and can be referred to by the digital signal processor DSP1. The current flowing through the circuit block C1 can be obtained by dividing the voltage between the node (Vd) on the circuit block side of the power switch and the node (Vs) on the ground potential side by the on-resistance of the power switch (PSW1) known at design time. Take -14- 200844462. In the above current measurement, since the power switches of all the power supply regions can be turned on, the current measurement of each circuit block can be performed when the wafer is normally operated. The operation result of the above-mentioned digital signal processor DSP1 is fed back to the internal circuit or output to the outside through the external terminal Output (ST7). Because the voltage between the Vd-Vs of the actual chip is smaller than the on-resistance of the power switch PSW1, Estimate the signal strength will be 10mV. Therefore, if the signal is directly introduced into the wafer, noise may be mixed in. Therefore, by setting the amplifiers Amp 1 to AmpN in the vicinity of the corresponding circuit blocks, the length of the power transmission switch and the signal transmission path up to the corresponding amplifiers Ampl to AmpN can be shortened as much as possible. This allows high-accuracy current measurement to be performed even if right-handed noise is mixed. Fig. 2 is a configuration example of the above-described amplifiers Ampl to AmpN. The amplifier is substantially formed by a source-converting circuit SF 1 for voltage conversion of a voltage input by 〇utl, and a P-channel MOS transistor MP1 and MP2 for converting a voltage into a current signal. The current mirror circuit CM is constructed. The amplification rate α of the circuit can be expressed roughly by the element size ratio of the p-channel MOS transistors ΜΡ1 and ΜΡ2. Vbiasl is used to drive the bias signal of SF1. ΜΝ1 is an N-channel MOS transistor for converting the output voltage signal of SF1 into a current signal. Since the amplifier is an analog circuit, the power supply voltage is VCC (about 3 V) higher than the voltage of the VDD of the digital circuit. Figure 3 is a diagram showing the configuration of the main parts of the above SoC. The power supply area is composed of five parts of Areal to Area5. On the basic -15-200844462, the power switch (pswi~psW5) is present on both sides of each circuit block. Each of the power supply regions is constituted by a so-called digital circuit. The amplifiers Amp 1 to AmpN (analog circuits) are provided in the vicinity of the analog circuits (An1 to An55). Thereby, the distance at which the weak signal is introduced can be shortened in the wafer, and the measurement with high precision can be realized. The AD converter AD C 1 ' is placed somewhere on the wafer because it can be shared by the wafer. DSP1 can be configured in any of the power areas Areal~Area5. Figure 4 is a configuration of the periphery of the above power switch. In Fig. 4, the wiring extending in the X direction is a wiring formed by the first metal layer M1, and is a wiring of the VDD power supply line VDDM1 and the virtual ground (VSSM) power supply line V S S MM 1 . V S S Μ is a power supply line that can be disconnected from the true ground (V S S ) by a power switch described later. The wiring extending in the y direction is different from the first metal layer wired in the X direction, and is, for example, a wiring implemented by the second metal layer M2. Since VDD and V S S are large-area wiring in the power supply region, the resistance is reduced by connecting the regular vertical rails (VDDM2, VSSMM2). In the figure, only one of the figures is shown. However, in order to make the voltage drop when a necessary amount of current is supplied at the operating speed of the internal logic circuit or the like within a predetermined threshold, a regular and optimal arrangement can be employed. In the power supply area, a basic circuit called an inverter circuit (1NV), a reverse circuit (NAND), a non-circuit (NOR), a flip-flop (FF), or the like, which is called a standard battery, is disposed. The power switch PSW is formed by the drain side diffusion layer DINV, the gate GATE1, and the source side diffusion layer SINV. Further, the PSW is formed by a usual NMOS. DINV is connected to VSSMM1 by a contact, and SINV is connected to the ground V S S of the new 16-200844462 by a contact. The V S S system is equivalent to the node of Figure 1, and the V S S system corresponds to the V S node. Usually, V S S and V S S Μ have lower impedance because they are connected to the regular trunk. Therefore, it is sufficient that the probe points of Vd and Vs are 1 point of VSS and VSSM, respectively. On the other hand, the advantage of configuring the probe points of a plurality of points is to absorb some of the micro voltage errors generated in the power supply region. In general, the gate oxide film of the power switch is formed to have a thickness greater than that of a standard battery in the power supply region. When the power switch is turned off, set GATE 1 to a low level (0V), and when it is turned on, set it to a high level (about 1.5V). Thereby, the connection relationship between the virtual ground VSSM and the new ground VSS is controlled. Fig. 5 is a cross section of A-A, B-B' in Fig. 4. Section 5 (a) is a section of A-A'. It consists of a three-well well formed by an N-type well (Nwell) formed on a P-type substrate (Psub) and a P-type well (P W1, Pwell) formed on Nwell. The power-on relationship is formed in the N-channel type MO S transistor of P W1. Via the element isolation region (ST1), a PMOS corresponding to a part of the standard battery in the power supply region is formed. GP, DP, and SP are equivalent to gate, drain, and source, respectively. Fig. 5(b) is a cross section taken along line B-B' of Fig. 4. As in the above, it is a three-pronged well, and the configuration of the power switch is also the same. An NMOS that is part of a standard battery is formed by ST1. GN, DN, and SN are equivalent to gate, drain, and source, respectively. According to the above examples, the following effects can be obtained. (1) The collective SoC of the circuit blocks divided into functions, the wafers are in the normal operating state, and the currents consumed by the respective circuit blocks can be implemented, -17-200844462 evaluation, measurement, and analysis. In addition, by relying on the measured current ’, the trustworthiness of the wafer can be improved by feeding back to the wafer control. (2) Because the voltage between the Vd-Vs of the actual chip is smaller than the on-resistance of the power switch PS W1, the estimated signal strength will be less than 1 〇mV, and the amplifiers Ampl~AmpN are placed near the corresponding circuit blocks. Minimize the length of the power switch and the signal transmission path up to the amplifiers Ampl~AmpN corresponding to it, and perform high-precision current measurement even if there are some noises mixed in. (3) When the current above the specification continues to flow through the circuit block, the heat generation amount of the wafer increases, and the reliability of the wafer is lowered. Therefore, as described above, the current of the circuit block during the normal operation is measured, which is advantageous for improving the wafer. Trustworthiness. In addition, since the current of each circuit block in the normal operation can be measured, the evaluation and analysis of the wafer can be easily performed. Fig. 7 is another configuration example of the main part of the above SoC. The difference between the configuration shown in FIG. 7 and the one shown in FIG. 1 is that the multiplexer MUX is omitted, and the amplifiers Ampcl to AmpcN are directly controlled by the control line SIG from the controller CTL2, and the multiplex is omitted. MUX. For example, when A m p c 1 is to be driven, it is sufficient that the S I G input to A m p c 1 is at a high level, and the other control line SIG is at a low level. Fig. 8 is a configuration example of the amplifier Ampcl of Fig. 7. In addition, other amplifiers have the same composition. The Outd and Out2 of the Vd and Vs voltage signals output from the power supply area Areal are input to the booster system as shown in Fig. 2. Further, the configuration of the amplifier body AMP is the same as that shown in Fig. 2. In the configuration of -18- 200844462 shown in Figure 7, set the power switch (PSWAD, PSWAS) or the switch (SW1) to set the amplifier between the power supply vcc and the ground of the amplifier. For example, when Areal is selected, the signal line SIG1 is at a high level, and the n-channel MOS transistors PSWAD and PSWAS are turned on to supply power to the amplifier AMP. Further, at this time, the switch SW1 is turned on, and the output signal of the amplifier AMP is output from the output terminal AoutX. On the other hand, when the signal line SIG1 is at a low level, the n-channel type MOS transistors PSWAD and PSWAS are turned off, and the amplifier AMP is not supplied with power. In addition, the switch SW1 is also turned off to prevent an undefined signal from being output to AoutX. According to this configuration, only the amplifier AMP connected to the power supply region to be measured can be operated, and the current consumed by the other amplifiers can be suppressed, so that the power consumption of the SoC can be reduced. Fig. 9 is another configuration example of the main portion of the above S 〇C. The difference between the configuration shown in Fig. 9 and the one shown in Fig. 1 is that the voltage frequency conversion circuits VFC1, VFC2, ..., VFCN are provided instead of the amplifier of Fig. 1, and the power supply regions can be cut. The analogy is necessary for the circuit area. The output signals Aoutfl, Aoutf2 are output from the respective voltage-frequency conversion circuits VFC1, VFC2, ..., VFCN, and are selectively supplied to the frequency-to-voltage conversion circuit FVC by the multiplexer MUX2 in the subsequent stage. The operation of the multiplexer MUX2 is controlled by the controller CTL3. The voltage-to-frequency conversion circuits VFCI, VFC2, ..., VFCN are oscillated at frequencies corresponding to the voltages that are respectively acknowledged. The frequency-to-voltage conversion circuit FVC converts the frequency of the input signal into a voltage. The output voltage of the frequency-to-voltage conversion circuit FVC is supplied to the DSP2 of the latter stage. 200844462 When using the voltage-to-frequency conversion circuit VFC, the signals input from the respective power supply domains are divided into three systems. That is, the voltage level signal 〇ut3 from the high-potential side power supply VDD and the signals Out4 and Out5 at both ends of the power switch PSW1. The reason why the voltage level signal 〇ut3 is required is that the voltage of the voltage frequency conversion circuit cannot be operated with a small voltage between Vd and Vs. The processing of the signals of the three systems is as follows. Fig. 10 is a diagram showing an example of the configuration of the above-described voltage-frequency conversion circuit VFC1. In addition, the voltage frequency conversion circuits of other power supply regions have the same configuration. The voltage-frequency conversion circuit VFC1 has two ring oscillators in which an odd number of inverters INV are connected. The ring oscillator is performed at a frequency substantially proportional to the difference between the supplied power supply voltage (the source potential of the P-channel MOS transistor) and the ground voltage (the source potential of the n-channel MOS transistor). The oscillation system is well known. Therefore, the high-potential side power supply VDD and the node Vd voltage, the high-potential side power supply VDD, and the node Vs voltage are input, and each differential voltage is converted into a frequency and output. Finally, the difference between the Vd_Vs voltages is calculated using the difference of the frequencies to determine the current flowing through the power switch PSW1. The input system of the ring oscillator in the upper part of Figure 10 is 〇ut3 ( VDD ), Out4 (Vd), and the input of the ring oscillator in the lower part of Figure 10 is Out3 ( VDD ) and Out5 ( Vs ). A waveform of a frequency vibration which is substantially proportional to each voltage difference is output to the outputs Aoutfl to Aoutf2. In addition, since the signal output from the voltage-frequency conversion circuit VFC1 is an oscillation signal of the ring oscillator, even if a certain amount of noise is mixed in, the influence on the frequency is small, so that high-accuracy current measurement can be performed. The output Aoutfl~A〇utf2-20-200844462 is input to the frequency-to-voltage conversion circuit FVC through the multiplexer MUX2. Fig. 11 is a configuration example of the above-described frequency-voltage conversion circuit FVC. In the above frequency-to-voltage conversion circuit FVC, the input signals Aoutfl and Aoutf2 are converted into voltages according to the frequency in the internal frequency-to-voltage conversion circuit FVCC. Further, the 'amplitude voltage' is converted into a current in the latter stage, and the AD converter ADC in the latter stage is converted into a digital signal. That is, the voltage information outputted to the DSPin1 signal VDD-Vd is output to the information of DSPin2, which is the voltage information between V D D - V s . Based on the information, the digital signal processor DSP2 calculates the voltage between Vd and Vs. Hereinafter, as shown in Fig. 1, the current 値 flowing through the power switch of the object to be measured is calculated. According to the above configuration, the V F C circuit provided in each power source region can be formed by a standard battery, and the area of the wafer can be reduced. In addition, since the information output from v F c is frequency, it is not susceptible to noise, and high-accuracy current measurement can be performed. Fig. 12 is another configuration example of the main part of the above SoC. The difference between the configuration shown in Fig. 12 and the one shown in Fig. 1 is that the power supply to the circuit block C1 of each power supply region is performed by the adjuster Reg 1, and the circuit block is implemented via the adjuster Re g 1. Current measurement of C 1 . When using the regulator, use VCC of the power supply voltage higher than the high-potential side power supply voltage VDD of the logic circuit. Fig. 13 is a configuration example of a regulator of the power supply area Afeal. In addition, the regulators of other power supply areas are also the same. The regulator Regl is formed by combining a reference voltage generating circuit VREFC, an operating amplifier (operational amplifier) OP Amp, and a p-channel MOS transistor MP3. The operational amplifier OP Amp operates in such a manner that the output voltages of the node Vrs and the reference voltage generating circuit VREFC are equal. For example, if Vrs is lower than the reference 値, the op amp OPAmp output is lower than the voltage until then, and the voltage of the node Vrs is restored to the reference 値. Thus, the circuit block C 1 is supplied with a stable power source. SoC, when the wafer operation state changes drastically (especially during reset), the circuit may malfunction due to the voltage drop occurring inside the wafer. In contrast, if the regulator Reg 1 is used, the above problem can be alleviated. The current flowing through the circuit block C1 can be measured by the current flowing through the p-channel MOS transistor MP3, and the drain-side node voltage of the P-channel MOS transistor MP3 is the same as that of the power switch shown in FIG. The (Vrd) and source side node voltages (Vrs) are output to Out6 and Out7, respectively. This output is passed to amplifiers Ampnl~AmpnN where it is converted to current. Fig. 14 is a view showing an example of the configuration of the above-mentioned amplifier Ampnl. In addition, other amplifiers have the same composition. The difference between the configuration shown in Fig. 14 and the one shown in Fig. 2 is the configuration of the source follower circuit SF2 of the initial stage. The signals 〇ut6 and Out7 outputted from the respective power supply regions are close to the high-voltage power supply. As shown by SF1 in Fig. 2, the source of the p-channel MOS transistor follows the circuit configuration of the SF 2 circuit. The circuit operation and the like are the same as those shown in Fig. 2, and the power switch psw 1 can be disposed in each power supply region. In addition, when both the regulator Re g 1 and the power switch P S W 1 are provided, the current measurement of the circuit -22-200844462 block C1 can be used. Fig. 16 is a view showing an important part of the semiconductor integrated circuit of the second embodiment of the present invention. In the present embodiment, the mechanism for feeding back the current measured in the wafer as a flip-flop to the wafer control is described. The purpose of the feedback is, for example, to suppress the temperature of the wafer, i.e., the maximum current of the wafer, below a certain threshold. In the semiconductor integrated circuit, if the temperature rises above a certain level, the probability of the function being destroyed is very high. In addition, the heat release characteristics of the package and the heat generation of the wafer depending on the environment of use are also limited. For the above reasons, the implementation of temperature control of the wafer becomes extremely important. Hereinafter, a mechanism for suppressing the maximum current of the wafer to a certain level or less by measuring the current in the wafer will be described. The system on-chip SoC is composed of resource manager RM, CPU1, CPU2, function block FBI, FB2, timer TMR, RAM, ROM, bus arbiter ARB, interrupt controller INTA, performance detection circuit 14, performance counter PPC, The clock frequency control unit CLK, the internal bus BUS, the power switch 28, the amplifier Amp, and the current measuring circuit CD are formed. The resource manager RM is composed of an instruction encoder DEC, a control unit CTL, a current management unit CWM, a job management unit TSKM, and an interrupt controller INTC. The current measuring circuit CD includes circuits of a multiplexer MUX1, a controller CTL1, an analog-to-digital converter ADC1, a read-only memory ROM1, and a digital signal processor DSP1 as shown in Fig. 1 of the foregoing embodiment. Further, in the present embodiment, the CPU 1, CPU 2, FBI, and FB2 are respectively disposed in the respective power supply regions. Fig. 17 is a diagram showing the maximum current control of the second embodiment of the present invention -23-200844462. The horizontal axis is time and the vertical axis is current 値. The function blocks FB0, FBI, and FB2 are represented by rectangles of processing time and current, respectively. Each process sets a deadline (deadline). Here, for the sake of simplicity, the same time. The current 値 is expressed in terms of the total number of functional blocks at a certain time. The wafer current is expressed in terms of the total area of the rectangles. (a) When there is no maximum current management. Since the function blocks FB0, FB 1, and FB2 are executed at the same time, the total currents of the maximum currents are larger. (b) When the maximum current control is performed by hysteresis, the execution of the hysteresis blocks FB1 and FB2 is not performed simultaneously with the function block FB0, so that the maximum current 可 can be reduced. It can be achieved by controlling the start of execution with a given current budget and deadline. (c) When the control frequency is used to perform the maximum current control, the maximum current 値 can be reduced by performing the operation at a clock frequency lower than any of the function blocks FB0, FBI, and FB2 in accordance with the current budget and the deadline. (b), (c) If the current budget is to be further reduced, the deadline will not be met. Therefore, control is performed in such a manner as to satisfy either the current budget and the deadline. The processing of the deadline is met, because processing is completed within the required time, which can also be called immediate processing. Figure 18 is a flow chart for suppressing the maximum current of the wafer below a certain chirp by reducing the clock frequency. Hereinafter, the flowchart will be described in detail. At regular intervals of a few ms, the TMR interrupts the INTC notification to the resource manager RM. The resource manager RM that has received the interrupt acquires the current 流 flowing through the respective circuit blocks of the CPU 1, CPU 2, FBI, and FB 2 from the CD. At the same time, the TSKM in the resource manager RM updates the operation information of the CPU and the function block to grasp what kind of operation the functional unit is performing. In addition to -24- 200844462, the progress of each circuit block is obtained from the performance counter PPC. Second, the resource manager RM calculates the sum of the currents flowing through the circuit block, I__Sum. At this time, the maximum current 値I_max allowed by the wafer is set in advance in the current management unit CWM. I_max is set to be equal to or less than the maximum allowable current 晶片 of the wafer. : When it is less than I_max, wait for the interrupt from TMR again. When I__sum is larger than I_max, based on the progress of each circuit block obtained from the PPC and the TSKM management operation information, one or more circuit blocks in which the work progress is sufficient and the lower priority operation is being executed are selected. The resource manager RM transmits a signal for reducing the clock frequency of the selected circuit block to the clock frequency control unit CLK. Next, the clock frequency control section CLK lowers the clock frequency supplied to the selected circuit block. As a result, the current flowing through the wafer is reduced, and the temperature rise of the wafer can be suppressed, and the reliability of the semiconductor integrated circuit can be improved. In addition, when it is less than I_max, the clock frequency is increased, and the processing of the job can be ended in a short time. The present invention has been described in detail with reference to the embodiments of the present invention. However, the invention is not limited thereto, and various modifications may be made without departing from the scope of the invention. The above description is mainly for the case of applying the SoC using the field in the background of the invention of the present invention. However, the present invention is not limited thereto, and can be widely applied to various semiconductor integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an example of a configuration of an internal integrated circuit of an embodiment of the semiconductor integrated circuit of the present invention and a SoC of -25-200844462. Fig. 2 is a circuit diagram showing an example of an amplifier of an internal logic circuit shown in Fig. 1. Fig. 3 is a configuration explanatory diagram of main parts of the above SoC. Fig. 4 is a diagram showing the configuration of the periphery of the power switch of the above SoC. Figure 5 is a cross-sectional view of the main part of Figure 4. Figure 6 is a flow chart showing the steps of current measurement of the above SoC. Fig. 7 is a block diagram showing another configuration example of the main portion of the above SoC. Fig. 8 is a circuit diagram showing a configuration example of the amplifier of Fig. 7. Fig. 9 is a block diagram showing another configuration example of the main portion of the above SoC. Fig. 10 is a circuit diagram showing a configuration example of the voltage-frequency conversion circuit of Fig. 9. Fig. 1 is a circuit diagram showing a configuration example of the frequency-to-voltage conversion circuit of Fig. 9. Fig. 12 is a block diagram showing another configuration example of the main portion of the above SoC. Fig. 13 is a circuit diagram showing a configuration example of the adjuster shown in Fig. 12. Fig. 14 is a circuit diagram showing a configuration example of the amplifier shown in Fig. 12. Fig. 15 is a block diagram showing an example of a configuration of a semiconductor integrated circuit of the present invention and a user system including a SoC. Fig. 16 is a block diagram showing an example of the configuration of an internal logic circuit of an SoC which is an example of a semiconductor integrated circuit according to a second embodiment of the present invention. -26- 200844462 Fig. 17 is a conceptual diagram of maximum power control in the form of the second embodiment of the present invention. Figure 18 is a flow chart of the feedback step of the SoC of Figure 16. [Main component symbol description] 1 0 0 : Current measuring circuit ADC1 : Analog digital converter
Ampl〜AmpN:增幅器Ampl~AmpN: Amplifier
Ampcl〜AmpcN:增幅器Ampcl~AmpcN: Amplifier
Ampnl〜AmpnN:增幅器 Α η 1〜A η 5 · ·:類比電路區域 C 1 :電路塊 CTL1〜CTL3 :控制器 DSP1〜DSP2··:數位信號處理器 FF :正反器 FVC :頻率電壓轉換電路 OPAmp :運算放大器 PAWAS :接地線側電源開關 PSW1〜PS W5 :電源開關 PSWAD :電源線側電源開關 Regl :調整器 ROM1 :唯讀記憶體 SF1〜SF2 :源極隨耦電路 S IG、S IG 1 :信號線 -27- 200844462 RM :資源管理器 D E C :指令編碼器 CTL :控制部 CWM :電流管理部 TSKM :作業管理部 INTC :中斷控制器 PPC :效能計數器 CPU1 〜CPU2 : CPU F B 1 〜F B 2 ·· f幾會 g ϋ C D :電流測定電路 CLK :時脈頻率控制部 B U S :內部匯流排 TMR:計時器 ARB :匯流排仲裁器 RAM :隨機存取記憶體 ROM :唯讀記憶體 INTA :中斷控制器 Amp:增幅器 S 〇 C :系統晶載 1 4 :效能檢測電路 2 8 :電源開關 -28-Ampnl~AmpnN: Amplifier Α η 1~A η 5 · ·: Analog circuit area C 1 : Circuit block CTL1 ～ CTL3 : Controller DSP1~DSP2··: Digital signal processor FF: Forward/reverse device FVC: Frequency voltage conversion Circuit OPAmp : Operational amplifier PAWAS : Ground line side power switch PSW1 ~ PS W5 : Power switch PSWAD : Power line side power switch Regl : Regulator ROM1 : Read only memory SF1 ~ SF2 : Source follower circuit S IG, S IG 1 : Signal line -27- 200844462 RM : Resource manager DEC : Command encoder CTL : Control unit CWM : Current management unit TSKM : Job management unit INTC : Interrupt controller PPC : Performance counter CPU1 to CPU2 : CPU FB 1 to FB 2 ·· f Several meetings g ϋ CD : Current measurement circuit CLK : Clock frequency control unit BUS : Internal bus bar TMR: Timer ARB : Bus arbitrator RAM : Random access memory ROM : Read only memory INTA : Interrupt controller Amp: Amplifier S 〇C : System crystal carrier 1 4: Performance detection circuit 2 8 : Power switch -28-