TW200832403A - Non-volatile memory with dual voltage select gate structure and method for operating the same - Google Patents

Abstract

A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.

Description

200832403 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory. [Prior Art]

Semiconductor memory has become more and more widely used in various electronic devices. For example, non-volatile semiconductor memory is used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and the most common non-volatile semiconductor memory in flash memory systems. Compared to traditional full-featured EEPROMs, flash memory (also known as EEPROM type) can erase the contents of the entire memory array or the contents of a portion of the memory in one step. Both conventional EEPROM and flash memory utilize floating gates that are positioned in the channel region and insulated from the channel region in the semiconductor substrate. The floating questioner is positioned between the source region and the drain region. The control gate is provided on the floating gate and insulated from floating _. The threshold voltage (Vth) of the thus formed transistor is controlled by the Lei 曰 retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before conduction of the transistor to allow conduction between its source and drain potential is controlled by the charge level on the sub-gate. Some EEPROM and flash memory devices have floating gates for storing two ranges of charge and are privately placed between two states (eg, erased and stylized). / Erase memory components. Such a flash memory device is sometimes referred to as - a binary flash memory device 125538.doc 200832403 controls the gate and grounds the bit line to make the electrons from the memory unit or memory element ( For example, the channel of the storage element) is injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes a negatively charged state, and the threshold voltage of the memory component rises, causing the memory component to be considered to be in a programmed state. For more information on stylization, please refer to US Patent No. 6,859,397 entitled "Source Side Self Boosting Technique For Non-Volatile Memory" and published on February 3, 2005.

U.S. Patent Application Serial No. 2/5/24,939, entitled "Essence...Ova Programmed Memory"; the entire contents of which are incorporated herein by reference. The storage elements are adjacent to each other, resulting in various stylized interferences that have been encountered during stylization, including gate induced/Gate Induced Drain Lowering stylized interference. It is expected that this problem will be exacerbated. When V is post-programmed with other non-volatile storage elements, the threshold voltage eccentricity of the previously programmed non-volatile storage element is disturbed. [Invention] The way with other topics is to provide - kind with dual power

The non-volatile memory of the indecent A of the pressure-selective gate structure, and the method of making and patterning such non-volatile memory. In a specific embodiment, a n π π ## species is used for a non-volatile storage system, and a k-gate structure, a twisted-conductor, a conductive portion, for example, a polycrystalline spine layer Formed, the 篦_ your conductive 邛 is carried by a substrate; a 125538.doc 200832403 and other two conductive parts, for example, a portion guided by another layer is formed in the first conductive portion y The first part of the first-eighth t ^ /V ^ electric part is electrically coupled to the first conductive portion of the first-part one of the conductive portion of the first-part one of the conductive portion And a third conductive portion and formed on the dielectric portion. The first pass, the V-knife is electrically isolated from the first conductive portion by the dielectric portion and is spaced apart from and spaced apart from the second conductive portion. In another embodiment, a non-volatile storage system includes: at least a NAND string having a plurality of non-volatile storage elements, and a select gate structure arranged in the at least one NAND string. At the end, the select gate structure is provided as described above. In another embodiment, the non-volatile storage includes: at least one NAND string having a plurality of non-volatile storage elements; and a selective interpole structure located at the end of the NAND string. The pole structure includes a selection gate and a coupling electrode, wherein a portion of the selection gate extends between the coupling electrode and a substrate. In another embodiment, the non-volatile storage system comprises: a plurality of NAND strings Each NAND string includes a plurality of non-volatile storage elements; and a plurality of word lines connected to the NAND strings. Each Nand string includes: a first conductive portion carried by a substrate, the first conductive portions Separating toward a word line; a second conductive portion formed on the first conductive portion of each NAND string and electrically coupled to the first conductive portion, the second conductive portion being successively connected in a word line direction Extending across a plurality of NAND strings, in addition, the second conductive portion and the spaced apart first conductive portions provide a selected gate for the NAND strings; - third conduction 125538.doc 200832403: the knife is formed at (4): The conductive portion is electrically insulated from the second conductive/knife and extends successively across the plurality of NAND strings in the direction of the δ-Hay sub-line, the third conductive portion providing a coupling electrode for the nand strings. One of the non-volatile memory systems used in the present invention is a NAND-type flash memory structure in which a plurality of transistors are arranged in series in two select gates of an N AND string. Figure 会# shows a top view of two NAND strings arranged in sequence. In practice, several such NAND strings can be sequentially arranged in a one-dimensional array (as needed, in a three-dimensional array) across a semiconductor device. The NAND strings shown in Figure 2 are connected in series and sandwiched between four gates, and between the gate structures. For example, NAND string #1 includes a gate-side selection gate structure (not shown) Illustrated as a transistor 1 〇〇, 1 与 between a source side selection gate structure 110 including a source side selection gate (SGS) U2 and a source side coupling electrode (CES) 108 2, 1〇4 and 1〇6. NAND string #2 includes a gate-side selection gate structure 14〇 a drain side select gate (SGD) 142 and a drain side coupled electrode (CED) 146) and a source side select gate structure 16A (including a source side select gate (SGS) 166 and The transistors 150, 152, 154, and 156 between a source side coupling electrode (CES) 162). Note that one end region of the nand string #1 is cut off on the drain side. In NAND string #1, at one end, a selection gate (not shown) connects the NAND string to a bit line contact (not shown in the figure), and at the other end, the selection Gate 112 connects the NAND string to a source line contact 120. Similarly, in NAND string #2, at one end, the idler 125538.doc •10-200832403 142 is connected to the one-bit line contact 130, and at the other end, the select gate 166 is connected. The NAND string is connected to a source line contact 17〇. The select gates are controlled by applying an appropriate voltage. Further, in the NAND string #1, the transistors 100, 1〇2, 1〇4, and 1〇6 each have a control gate and a floating gate. Specifically, the transistor 1 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 1〇6 includes a control gate i〇6CG and a floating gate 106FG. Control gates 1〇〇CG, 102CG,

104CG and 106CG are respectively part of word lines WL3, WL2, WL1 and WLO. In a possible design, the transistors 1〇〇, 1〇2, 1〇4, and 1〇6 are all § memory units or non-volatile storage elements. In other designs, the memory element may comprise a plurality of transistors, or may be different from the memory elements illustrated in Figures i and 2. Select gate 142 is coupled to a gateless select line and select gates 112 and 166 are coupled to associated source select lines. NAND string #2 is arranged in a manner similar to NAND string #1 and includes a contact 130 (which is connected to a bit line on one of the NAND strings), while a contact 170 is connected to the common The source selects the gate voltage. In addition, the source side select electrode 166 is coupled to the associated source select line and the drain side select gate 142 is coupled to the associated drain select line. In NAND string #2, transistors 15A, 152, 154, and 156 each have a control gate and a floating gate. The transistor 15A has a control gate 150CG and a floating gate 150FG. The transistor 152 includes a control gate i52c^ and a floating gate 152FG. The transistor 154 includes a control gate 154CG and a floating 125538.doc • 11-200832403 gate 154FG. The transistor 156 includes a control gate 156CG and a floating gate 156FG. Control gates 150CG, 152CG, 154CG, and 156CG may be provided as part of word lines WL3, WL2, WL1, and WL0, respectively. These word lines differ from the word lines associated with NAND string #1. A select gate structure can be provided at one or both ends of a NAND string. A dual voltage selective gate structure is provided for use with a 'selective gate structure' that can be controlled by one of the different voltage coupling electrodes and a select gate. When operating the NAND string, the dual voltage select gate structure Several advantages are provided, as discussed further below. In a possible implementation, F denotes the word line, the width of the control gate and the floating gate of each memory element, and marks the interval between the memory elements; 3F indicates the source selection gate structure and The drain selects the width of the gate structure; and 3F or 5F indicates the width of the space between the selected gate structures of adjacent NAND strings, which is used to locate the contacts. Selecting the gate structure wider than the memory component design is useful for preventing current leakage by selecting the gate. ® Figure 3 shows a circuit diagram of three NAND strings. A typical architecture for a flash memory system using a NAND structure would include several NAND strings. By way of example, three NAND strings 320, 340, and 3 60 in a memory array having more NAND strings are illustrated. Each of the NAND strings includes, in addition to four storage elements, two select gate structures, each select gate structure having a respective select gate transistor and coupling element. Although four storage elements are illustrated for simplicity, modern NAND strings can have up to, for example, 32 or 64 storage elements. 125538.doc -12- 200832403 The reason is that each memory component can store one bit of data. A multi-state (also known as multi-level) flash memory device is implemented by identifying multiple distinct allowed/effectively programmed threshold voltage ranges. Each of the different power limiting ranges corresponds to a predetermined value for each set of data bits encoded in the memory device. For example, when the memory component is placed in a four-phase* charge band corresponding to the four-section (four) range, each memory element can store two bits of data. ... Eight places, a program voltage VPGM applied to the control gate during the clamp operation is applied as a series of pulses whose magnitude increases with time. In the practice of the factory item, the magnitude of the pulses is incremented by each successive pulse according to a predetermined step size, for example, '0·2 volts to 0.4 volts. The VPGM can be applied to the control gate of the flash memory component. The verification operation is performed during the period between the program pulses. Gp, between successive program pulses = reading the private level of each of the L bodies of 70 pieces of the group memory element being parallelized to determine whether the memory element is equal to or greater than eight The verification level applied to it while it is being programmed. For the avatar-type flash memory device array, a verification step is performed for each state of the memory component to determine whether the memory component has arrived at its data associated with the certificate. For example, an empire-like I-memory component capable of storing data in four states may have to perform verification operations on three comparison points. In addition, when staging a EEPROM or flash memory device (such as a nand flash memory device in a Nand string), typically -u 125538.doc 200832403 For example, NAND string 320 includes a select gate Structures 322 and 327 and storage elements 323-326; NAND string 340 includes select gate structures 342 and 347 and storage elements 343-346; NAND string 360 includes select gate structures 362 and 367 and storage elements 3 63-366. Each NAND string is connected to the source line by its select gate structure (e.g., select gate structure 327, 347, or 367). A select line SGS is used to control the source side select gate of the selected gate structure. The various NAND strings 320, 340, and 360 are connected to respective bit lines 321, 341, and 361 by selecting select transistors in gate structures 322, 342, 362, and the like. They chose the transistor to be controlled by a drain selection line SGD. In other embodiments, the select lines are not necessarily co-linear between the NAND strings; that is, different select lines can be provided for different NAND strings. Word line WL3 is coupled to the control gates of storage elements 323, 343, and 363. Word line WL2 is coupled to the control gates of storage elements 324, 344, and 364. Word line WL1 is coupled to the control gates of storage elements 325, 345, and 365. Word line WL0 is coupled to the control gates of storage elements 326, 346, and 366. As shown, each bit line and its respective NAND string form a bank of storage elements or a collection of storage elements. The word lines (WL3, WL2, WL1, and WL0) constitute a column of storage elements or a collection of storage elements. Each word line connects the control gate of each storage element in the column. Alternatively, the control gate can be provided by the word line itself. For example, word line WL2 provides control gates for storage elements 324, 344, and 364. In practice, there can be thousands of storage elements on a word line. In addition, the coupling electrode of each of the selected gate structures is adjacent to a storage element and a word line. For example, the gate-side coupling electrode of the gate structure 322 is selected 125538.doc • 13- 200832403 is engaged/stored in the storage element 323 and the machine 3, and the source-electrode (CES) of the gate structure 327 is selected. Adjacent to the faulty component seems to be (4). It will be explained in the next = step that the 1 electrode should be close to the storage element to affect the storage element through the grid. Every: storage components can store data. For example, when storing a single yuan, the possible threshold voltage of the storage component (the range is drawn: the wide range of logical data "i" and, 〇" ^: Recalling the body-item example, after the storage element is erased, the meaning is = logical = "r. The Vth after the stylization operation is positive and is defined as logical "〇". Camp V inflammation name ^ 1 When the test is read, the storage component will be turned on and the logic is being stored. When the % is positive and the f test read operation component will not be opened, it indicates the storage logic, 〇, .. storage element = also: to save The main memory is multi-level information. For example, the number of VTH values is divided into several levels of capital. The heart 2° 'If you store four levels of information', there will be Four segments

Types of mind...: "〇1"&"〇〇". In the NAND = body-term example, να after the erase operation is negative and is set to ' ', '. The positive vTH value is used for the state "1〇,"〇1" and "〇〇". Between = the relationship between the data in the storage component and the threshold voltage range of the storage component It depends on the data encoding scheme used for the storage components. Γ^s '4 national patents (4) 6'222,762 and the US special shot please announce ^^ 255 () 9 () (the whole content of the case is cited The method is incorporated into this document.) Various data encoding methods for multi-component flash memory components are described. 0 125538.doc -14- 200832403 The following US patents/special shots provide flash memory And related examples of their operation: 5,386,422, 5,522,58,5,57, 315, 5'774'397, 6'046,935, 6,456,528 and 6,522,580, all of which are incorporated herein by reference. When the flash storage element is configured, a program voltage is applied to the control gate of the storage element, and the bit line associated with the memory element is grounded from the electrons of the channel to the floating gate. When the electrons accumulate in the floating gate, the floating gate becomes a negative load state. And the VTH of the storage element rises. To apply the _program voltage to the control gate of the memory element being programmed, the program voltage is applied to the appropriate word line. As described above, each of the NAND strings The storage element shares the same word line. For example, when the storage element 324 of FIG. 3 is programmed, the program voltage is also applied to the control gates of the storage elements 344 and 364. Shifting can occur when stylizing and retrieving a given storage element and other storage elements are bound to the predetermined storage element to some extent, such as storage elements that share the same word line or bit line. The field coupling between the storage elements: to cause an offset in the stored charge level to occur. The problem is exacerbated by the reduced space between the storage elements due to improvements in integrated circuit technology. Most notably occurs between several groups of adjacent storage elements that have been programmed at different times. A group of storage elements is programmed to join a level of charge corresponding to a set of data. After the two sets of data are programmed into a second group of storage elements, the charge-capacitance coupling due to the second group of storage elements to the first group of storage elements results in reading from the first group 125538.doc -15 · 200832403 The charge level of a group of storage elements appears to be different from the programmed charge level. Therefore, the coupling effect depends on the order in which the storage elements are programmed, and therefore depends on the order in which the word lines travel during stylization. Ground (but not necessarily), the stylized NAND string is from the source side to the immersed side, starting at the source side word line and advancing one word line at a time to the drain side word line. For example, the capacitive coupling effect on a given storage element can result from the same word line and other storage elements in the same NAND string. For example, storage component 344 can be a component of a first group of storage elements including other alternating storage elements along word line WL2 that store a page of material. Storage elements 324 and 364 can be part of a second group of storage elements that store another page of information. When the second group of storage elements are programmed after storage element 344, there will be capacitive coupling to storage element 344. The coupling from the directly adjacent storage elements (storage elements 324 and 364) on the word line is strongest. Similarly, storage elements 344 are affected if the storage elements on the same NAND string 340 are programmed after storage element 344. For storage element 344, the coupling from directly adjacent storage elements (storage elements 343 and/or 345) on the NAND string is strongest. For example, if the order of the storage elements in the stylized NAND string 340 is 346, 345, 344, 343, the coupling from the storage element 343 can affect the storage element 344. In general, storage elements (ie, storage elements 323, 3 63, 325, and 365) that are diagonally aligned relative to storage element 344 can provide about 20% coupling to storage element 344, while on the same word line or NAND string. Upper directly adjacent storage elements 324 and 364 and 343 and 345 provide about 80% coupling. In some cases, the coupling may be sufficient to offset the VTH of the stored 125538.doc -16 - 200832403 component by about 5 volts, which is sufficient to cause read errors and to distribute the vTH of a group of storage elements. Figure 4a depicts a cross-sectional view of a NAND string without a dual voltage selective gate structure. Only a portion of the NAND string is shown and there are various simplifications. In practice, a similar structure is formed across the semiconductor substrate in two dimensions (e.g., bit line direction and word line direction). Similar NAND strings 4 and 450 are shown. Extending in the direction of the bit line or NAND string, the NAND string 4A includes a select gate structure 410 (shown generally in phantom in the figure) and a number of memory elements (such as storage elements 440 and 460). The select gate structure 410 includes a select gate formed by a first conductive portion 42A and a second pass transistor 41. The select gate structure 4A also includes a turn-on electrode formed by a third conductive portion 412. The first conductive portion 420 of φ) φ4 电 is electrically isolated from other NAND strings. In contrast, the first conductive portion 418 and the third conductive portion 412 can extend across the plurality of NAND strings in the word line direction as control lines, such as word lines. In this manner, a control voltage applied to the second conductive portion or the third conductive portion is applied to each of the NAND strings in a group of NAND strings. Likewise, the control gate portion of the storage element can extend across multiple NAND strings as a word line. For example, in NAND string 450, a storage component 452 includes a control gate region 454 (which extends across a plurality of NAND strings) and a floating gate region 456 (which is isolated from other NAND strings). A protective barrier is provided on the selection gate, the coupling electrode and the storage element. For example, a protection barrier 416 is provided on the second conductive portion 418 of the select gate. A dielectric layer 414 is provided between the second conductive portion 412 and the first conductive portion 42's component. 125538.doc -17- 200832403. A NAND string is formed on a substrate 432 that includes a __n well region 43 and a p well region 428. Using shallow trench isolation techniques, in one possible design, p-well 428 includes an upwardly extending portion that is separated by a filler 426, such as Si〇2. The pattern of the upwardly extending portion of the P-well separated by the filler is repeated to the word line. Additionally, an n-source/drain-doped region (e.g., source/drain region 424) spaced apart in the direction of the bit line is provided in the p-well region. Specifically, source/drain regions are provided on both sides of the select gate structure 41A and on both sides of the storage elements 440 and 460. An insulating layer 422 is provided on top of the substrate 432. Figure servant shows the cross-sectional view of the storage component of the drill. This view does not include the selection of the gate structure so that the storage element can be seen more clearly. By way of example, it can be seen that the components of the storage element 440 include a protective barrier 47, a second conductive portion 472, a dielectric 474, a first conductive portion 476, and an absolute (four) 478. FIGS. 5 through (4) are shown for fabrication with The process of selecting a string of closed-pole structures with two voltages. Please note that the manufacturing process described in this article only states one: 仃1 method. Different manufacturing processes can be used to achieve the desired final structure. , moon heart, the drawing is not drawn to scale. Moreover, only one of the parts is shown in the drawings. In practice, a similar structure can be formed across the semiconductor substrate in two dimensions (e.g., bit line direction). A three-dimensional structure is also available. 5, a cross-sectional view of a non-patterned layered semiconductor material 500 (having an insulating layer, a first conductive layer, and a dielectric layer), a non-aligned direction... the substrate layer 51G includes a semiconductor Materials (such as 125538.doc • 18-200832403 Shi Xi). In one embodiment, the n-well and p-well (action) regions are formed in the substrate 510. An insulating layer 520 (which includes an insulating material such as an insulating oxide) is formed on the substrate 510. A first conductive layer 530 (which includes a conductive material such as a polysilicon layer) is formed over the insulating layer 520. A dielectric layer 54 (which includes a dielectric material) is formed on the first conductive layer 530. For example, the dielectric layer 540 can use an inter-polycrystalline (IPD), such as a layer of oxide-nitride-oxide (〇N〇). The semiconductor material of Fig. 5 after the photoresist has been deposited is shown in Fig. 5, and the result is a semiconductor material 600. Specifically, in a practicable practice, a photoresist layer 62 is deposited on the dielectric layer 540, a mask is used to selectively expose the photoresist layer to ultraviolet light, and the photoresist is removed using a developer. The exposed portion is thereby exposed to a portion of the dielectric layer 54. Etching is performed to remove the exposed portion of the dielectric layer 540 (not protected by the photoresist layer 62), and the result is the semiconductor material 7 of Figure 7. Figure 7 depicts the semiconductor material of Figure 6 after a portion of the dielectric layer has been removed, and the results obtained are the semiconductor material 7 of Figure 7. The photoresist layer 62q is removed, and a second conductive layer 810 (which includes a conductive material such as an additional polycrystal) is deposited on the exposed portion of the first conductive layer 53 and over the remaining portion of the dielectric layer 54.矽 layer), the results obtained are the semiconductor material 800 of FIG. Specifically, §, Figure 8 illustrates the semiconductor material of Figure 7 after the second conductive layer 810 has been added. Removing a portion of the dielectric layer 54 allows the first conductive layer and the second conductive layer to be in electrical contact with each other. In another approach, a mask can be used to form a dielectric layer in a desired location such that a portion of the first conductive layer is exposed such that 125538.doc -19-200832403 does not require subsequent removal of a portion of the dielectric layer. Figure 9 illustrates the semiconductor material of Figure 8 after the protective barrier has been added, and the result is a semiconductor material 900. A mask 91 〇 can be used to form a plurality of protective barriers 922, 923, 924, 925, 926 and 927 by transferring the pattern of the mask 910 to the semiconductor material. In a practicable approach, the protective barrier can be made of a dielectric material such as a nitride nitride (SiN). Again, please note that only one part of the semiconductor material is shown in the figure. For example, an additional protective barrier may extend to the right along a subsequently formed NAND string. • Figure 10 illustrates the semiconductor material of Figure 9 after the portion of the second conductive layer has been removed, resulting in a semiconductor material 1000. The mask 91 is removed and an etching process is performed to remove portions of the second conductive layer that are not protected by the barrier. As a result, the second conductive layer portions 1〇22, 1023, 1024, 1025, 1026, and 1027 continue to exist after the etching. In addition, portions of the first conductive layer adjacent to the second conductive layer portion 1022 are exposed, and " between the first conductive layer portion 1023 and 1024, 1024 and 1025, 1025 盥 1026, and 1026 and 1027 Portions of the electrical layer 540 are exposed. ^ etching removes a portion of the second conductive layer (which is between the protective barriers 922 and 923), thereby forming a gap 1〇1〇 and exposing a portion of the first conductive layer 53 1〇2〇. The gap 1010 can have a width of between about 1 and 15 F (see Figure 1) and can extend between the second conductive layer portions 1022 and 1 23 that are still present. The etch is controlled to reach the first conductive layer 53A and does not remove all of the first conductive layer 53A in the gap 1010. A protective barrier 922 and 923 are used to define a select gate structure. In one approach, for both the source side and the drain side of a NAND string, a gate selection structure similar to 125538.doc -20. 200832403 can be used. An alternative approach is to provide a source at the source side: (4) provided at the side of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Know the choice of gate transistor. In an alternative, a mask is applied over an area between the first protective barrier 922 and the second protective barrier 923 when the -first-remaining is performed. Then 'remove the mask' and place another-mask, 豸 another-mask

Between the protective barriers 922 and 923. The money is subjected to a separate quotation to remove only the portion of the second conductive layer between the protective barrier and the milk. The final result is shown in Figure 10. This practice involves an additional step 'but allowing etching between the first protective barrier 922 and the second protective barrier 923 to be performed independently of the etch between the other protective barriers defining the storage element. Figure 11 is a diagram showing the semiconductor material of Figure 1 after depositing a protective layer, resulting in a half-body material 11 〇〇. A protective layer 111 (which may be a dielectric material such as tantalum nitride) may be applied via a mask 12 in a region of the gap (7). The protective layer 1110 may cover the opposite sidewalls of the second conductive layer portions 1〇22 and 1〇23 and the exposed portion 1020 of the first conductive layer (FIG. 10). In addition, the portions 1112 and η 14 of the Baohan layer may cover the top members of the protective barriers 922 and 923 to allow for some degree of misalignment in the application of the protective layer 111. The result of the semiconductor material of FIG. 12 after the removal of the portions of the first conductive layer and the dielectric layer is the semiconductor material 12A. Specifically, a further etching process is performed to remove a portion of the first conductive layer (which is adjacent to the second conductive layer portion 1 22) and remove the dielectric layer 54 〇 125538.doc • 21 - 200832403 (FIG. 11) and portions of the first conductive layer 530 (the portions are oriented in the bit line direction between the second conductive layer portions 1023 and 1024, 1024 and 1025, 1025 and 1〇26 and 1〇26) Between 1 and 27). As a result, dielectric layer portions 1202, 1204, 1206, 1208, and 1210 are defined in addition to first conductive layer portions 1230, 1224, 1225, 1226, and 1227. The protective layer 1110 is prevented from being etched into the gap 1 0 10 . Extending in the direction of the bit line or NAND string, the semiconductor material 12 includes a select gate structure 1260 and an exemplary non-volatile storage element 1265,

1270, 1275 and 1280. The gate structure and the exemplary non-volatile storage element can be repeatedly traversed across the semiconductor substrate in a direction perpendicular to the page (e.g., word line direction) and in the direction of the bit line. As mentioned, only one portion of a NAND string is shown. In practice, a NAND string can include a number of select gates on either side of a series of non-volatile storage elements. The illustrated select gate structure 1260 can be provided on the source side and/or the drain side of a NAND string. The width of the select gate structure 126() can be about, wherein the width of the second conductive layer portions 1022 and 1023 can be about the same, for example, F. In another of about 3.5 F, wherein the second and second conductive layer portion options, the width of the width of the selectable gate structure 1260 can be about 15F, and the width of 1023 can be about F. In one approach, each non-volatile storage member may have a width of about F' and the non-volatile storage elements are spaced apart from each other in the direction of the bit line (see Figure 丨). Source/汲, regions 1250 and 1252 are formed in the substrate in either side of the selective closed structure 1260. In addition, source/125538.doc-22.200832403 drain regions 1254, 1256, and 1258 are formed in regions of substrate 510 (the regions are between the non-volatile storage elements in the bit read direction). The select gate structure 1260 includes a first conductive layer portion 1230 that extends between the source/drain regions 125A and 1252 in the bit line direction. On one side of the select gate structure 126, a second conductive layer portion 1022 is formed over the first conductive layer portion 1230 and electrically coupled to the first conductive layer portion 1230. Thereby a selective transistor is formed having a selected gate and source/drain regions 1250 and 1252 provided by the second conductive layer portion 1022 and the first conductive layer portion 123A. A voltage applied to the select gate controls a current flowing between the source/drain regions 125A and 1252. On the features of the first conductive layer portion 1230, a dielectric layer portion 1202 is formed for electrically insulating the second conductive layer portion 1 〇 23 from the first conductive layer portion 1230. The second conductive layer portion 1 〇 23 is used as a coupling electrode, for example, to reduce stylized interference during stylization. Moreover, in the storage element, dielectric portions 1204, 1206, 1208, and 1210 electrically insulate first conductive layer portions 1224, 1225, 1226, and 1227 (used as floating gates) from second conductive layer portions 1024, 1025, 1〇26 and 1〇27 (used as control gates). Figure 13 depicts the semiconductor material of Figure 12 after the sidewall spacers are formed. A spacer may be provided to prevent the bottom of the selected gate structure and the bottom of the floating gate of the storage element from being rounded by oxidation. The spacer can be created by: isotropically depositing the material to be used to form the spacer; and then anisotropically etching away the material leaving only a natural tapered spacer on the sidewalls of the pre-existing structure. In a specific embodiment, the spacer is made of SiN; however, other materials may be used. In particular, spacers 1304, 1306, 1308, 1310, 1312, 1314, 1316, 1318 may be provided along the side of select gate structure 125538.doc -23- 200832403 1260 and storage elements 1265, 1270, 1275, and 1280, 1320 and 1322. The height of the spacers can vary. In the illustrated example, the spacers extend from the protective regions 922, 923, 924, 925, 926, and 927 to the insulating layer 520. Figure 14 depicts the semiconductor material of the studded Figure 13 including the voltage applied to the selected gate, the face electrode of the selected gate structure, and the voltage coupling from the light junction electrode. A control line can be formed to allow voltage to be applied independently to a select gate 1430 (which is formed by the second conductive layer portion 1 22 and the first conductive layer portion 1230) and a coupling electrode 1440 (by The second conductive layer portion 1023 is formed). A sufficiently high voltage applied to the select gate 143 turns an inversion layer 1410 that turns on the select gate transistor and allows current to flow between the source/drain regions 1250 and 1252. In addition, the face electrode provides several advantages during the stylization process. For example, a voltage applied to the coupling electrode 1440 can affect the current flowing in the substrate. In particular, the GIDL (Gate Induced Drain Lowering) stylized interference has become an increasingly important issue as the Nand technology is further scaled. GIDL typically occurs at a maximum curvature point 1420 of the junction between source/drain region 1252 and insulating layer 520. This type of stylized interference particularly affects the non-volatile storage elements programmed by word line 0 (WL0), which is adjacent to the source side select gate in the NAND string. For example, if the select gate structure 1260 is on the source side, WL0, WL1, WL2, and WL3 may be extended to function as control gates 1024, 1025, 1026, and 1027, respectively, where WL0 is adjacent to the select gate junction. 125538.doc -24- 200832403 The end word line of 1260. The sub-line adjacent to the drain-side selection gate in the nanD string exhibits a small amount of stylized interference. Most of the WL0 stylized interference occurs during the programming of WL0 itself when the high program voltage (VpGM) value is reached and the ground WL occurs and the band-to-band tunneling is exacerbated. To solve this problem, it has been proposed to increase the interval between the end word line and its corresponding selection gate. Another proposed approach is to use dummy sub-lines and to have no data or binary data on the dummy word lines. Another approach involves storing one or two bits per storage element for non-volatile storage elements threaded by end words while storing three bits on each of the other non-volatile storage elements. . The selective gate structure 126 provided herein advantageously reduces the stylized interference by appropriately controlling the selection of the gate and the coupling electrode. This structure can be used in conjunction with other techniques that reduce the amount of interference. Specifically, in addition to the adjacent source/drain regions 1252, a voltage applied to the coupling electrode 144A is also capacitively coupled to the control gate (7) of the adjacent non-volatile storage element 1265 to interact with the juice gate. 1224. This voltage will help reduce the generation of hot electrons under the selective gate structure that occurs in GmL. Specifically, the depletion condition is changed to allow a floating gate to travel from the occurrence of the GIDL (point H2G) to the non-volatile storage element associated with the end word line (you 丨I. & K 4 ^ Μ, ,_

The increase in the +' electronic table due to the increase in the vertical field in the source/drain region 1252 increases.

125538.doc ~25 - 200832403 1430 'VCES is applied to the light-closing electrode 144A, a program voltage VpGM is applied to the selected sub-line (WL 〇 in this example)' and the pass voltage VPASS is applied To the remaining word lines WL1-WL3. For example, up to 8 volts or more can be placed at the coupling electrode 144A depending on the voltage level at which the dielectric layer portion 12〇2 (Fig. 12) under the coupling electrode 1440 can withstand. Additionally, during the threading of the non-volatile storage element via the end word, an electric cymbal can be applied to drive the light-closing electrode 144A. This creates a strong charge scatter by creating a strong accumulation layer. More electrons can be biased toward the coupling electrode 1440 and away from the floating gate of the adjacent non-volatile storage element. Additionally, the high voltage applied to the coupling electrode 144A can be reduced by coupling the voltage from the coupling electrode 40 to the non-volatile storage element of the end word line: to programmatically correlate the non-volatile associated with the end word line The maximum program voltage (vPGM) required to store the component, for example, from 22 volts to 21 volts. This coupled electromigration is related to VPGM. : Non-volatile storage elements associated with other non-adjacent word lines are programmed to apply the same voltage to select gate 1430 and coupling electrode 1 paste, for example, 0 volts. Other conditions are OK. Therefore, in the - item approach, the position of the word line in the NAND string that is currently being programmed to be one or more of the non-volatile library elements or the position of the word line to be programmed is currently selected. , to set the U-electrode 1 to the electric repeatedly. In another approach, the voltage on the coupling electrode 1440 is allowed to float when adjacent word lines, ' 仃耘 are used. That is, the following method is used to cope with the increase in the size of the selected gate structure, and the voltage of the coupling electrode is made to float and/or to be applied to the selected gate and phase. 125538.doc •26- 200832403 The voltages associated with the dissipative electrodes are simultaneously ramped or otherwise transformed in the same polarity direction such that coupling them to each other will enhance their charging or discharging. In general, the coupling electrode voltage is controlled according to various criteria, including stylized criteria, such as the position of the selected word line, temperature, program pulse level or number, number of device cycles, and program when multi-process programming is used. The number of processes. FIG. 15 illustrates an alternative semiconductor material 1500 having an alternative select gate structure 1560. In this manner, the dielectric layer 15〇2 extends successively between the second V-layers 1022 and 1023 such that the first conductive layer is not exposed in the gap 1〇1〇. A protective layer 151 is formed on a portion of the dielectric layer 1502 by a protective layer 111 类似于 similar to that of FIG. This design can be achieved by patterning the photoresist to extend it further to the left of the photoresist 62 绘 as depicted in Figure 6. Additionally, the components of the second conductive layer portion 1022 can be formed on the dielectric layer 502 to account for misalignment. Figure 16 illustrates a NAND string including the semiconductor material of Figure 13. Non-volatile storage systems typically include a number of NANd strings arranged end to end and side by side. Configuration 1600 depicts a complete nanD string 1620 and local NAND strings 1610 and 1630 arranged end to end. Specifically, the complete NANE 162 includes a source side select gate structure 1622, a series of non-volatile storage elements 1624, and a drain side select gate structure 1626. On one side of the string 1620, a portion of the other NAND string 1630 includes a source side select gate structure 1632 and an exemplary non-volatile storage element 1634. On the other side of the nand string 1620, another portion of the NANE 161 includes a drain side select gate structure 1614 and an exemplary non-volatile storage element 1612. 125538.doc -27- 200832403

Figure 17a illustrates an overview of a process for fabricating a semiconductor material having a selected gate structure. The process shown is merely an example of the various processes that can be used in practice. Referring also to Figures 5 through 14, at step 1700, a first conductive portion (e.g., portion 1230) is formed on an insulating layer (e.g., layer 52A) of a substrate (e.g., 'substrate 510). In step 17〇5, a second conductive portion (e.g., partial turns 22) is formed on the first member of the first conductive portion. At step 1710, a dielectric portion (e.g., portion 12A2) is formed on the second member of one of the first conductive portions. At step 1715, a third conductive portion (e.g., portion 1 〇 23) is formed on the dielectric portion, the third conductive portion being spaced apart from the second conductive portion. At step 1720, first and second source/drain regions (e.g., regions 1250 and 1252) are formed in the substrate on either side of the first conductive portion (1230). They are used to select the source/nopole region of the gate (143〇). The figure is a detailed process for fabricating the semiconductor material of Figure 13. The process shown is merely an example of the various processes that can be used in practice. In step 1725, a first conductive layer is formed on an insulating layer of a substrate (see, for example, Figure 5). At step 1730, a dielectric layer is formed over the features of the first conductive layer (e.g., 罜 罜 ...... month see Figure 5). As described, the dielectric layer 5 r may be formed on a desired region of one of the first conductive layers using an appropriate = two to be selectively removed at all of the first to expose the first conduction::: And give a sudden coffee, will ^ ^ ^. In step (10), the dielectric layer (see, for example, Figure 6). In the layer (for example, see Figure 7 = dry part down (four) to the first conduction ,, in step 1 745, remove the photoresist. l2553S.doc •28- 200832403

The second conductive layer is formed on the exposed portion of the first conductive layer and the remaining portion of the dielectric sound in step (10) (for example, please refer to the use of the mask in the second step 1 5) Protecting the barrier (for example, see figure / at step mo, the exposed portions of the second conductive layer are left down to the dielectric layer or the first conductive layer (see, for example, Figure 1G). (d) providing a mask outside the gap between the protective barrier and the second protective barrier (eg, see 'Figure 11}. In step 1770 'the gap in the selected gate structure Applying a protective layer (eg, 'see FIG. η). In step 1775, the exposed portion of the dielectric layer and the corresponding portion of the first conductive layer are etched down to the insulating layer (eg, see FIG. 12) In step 178, adjacent to the select gate structure and the non-volatile storage elements, a source/no-polar region is formed in the substrate (for example, see FIG. 2, finally, at step 1785, at Forming the gate structure and forming sidewalls on the non-volatile storage elements (eg, Referring to Figure 13) Figures 18a through I8i are another embodiment of a nand string having a dual voltage selective gate structure. In particular, Figure 18a illustrates another specific embodiment of a NAND string having a dual voltage selective gate structure. Embodiments In this embodiment, a select gate structure 1809 includes a first conductive portion 1815 formed on an insulating portion 1816 and a first conductive portion 1814 formed on the first conductive portion. The first conductive portions of the NAND string are spaced apart from each other in the word line direction. In addition, the second conductive portion 1814 extends successively across the plurality of NAND strings in the word line direction, and the first conductive portion is isolated from the NAND string. Between (for example, NAND strings 1800 and 1830). A third pass 125538.doc -29-200832403 lead portion 1810 is formed on a dielectric 1812 and also extends across the plurality of NAND in the direction of the word line. A protective barrier 1808 is provided on the third conductive portion 181. A filler 1820 (such as Si〇2) extends between the first conductive portions of each NAND string. The exemplary storage element 1802 includes a control gate. Pole/word line 18〇4 and Floating gates 1806 (which include a first conductive portion 1809 and a second conductive portion 1807). NAND strings 1800 and 1830 are formed on a substrate 1826 that includes a p-well region 1822 and a n-well region 1824. Also shown is an exemplary source/gt; and a polar region 1818. Figure 18b is a cross-sectional view of the storage element of the NAND string of Figure 18a. This view does not include a select gate structure so that the storage element can be more clearly seen For example, the assembly of the storage element 1 8 3 1 includes a protective barrier 18 3 2, a third conductive portion 1834, a dielectric 1836, a second conductive portion 1838, a first conductive portion 1839, and an insulator 1840. Here, the second conductive portions are spaced apart from each other in the direction of the word line, instead of being connected to each other as if the gate structure is selected. Fig. 18c depicts the configuration of the gate structure with respect to the NAND string and the word line. Word lines WL0-WL3 and NAND strings (including exemplary NAND strings / 1850) are shown. A zone 1841 indicates where the gate structure is selected. Figures 18d through 18f illustrate cross-sectional views along NAND string 1850, select gate structure regions 1841, and hips, respectively. Figure 18d shows a cross-sectional view of the NAND string along the configuration of Figure 18c. The exemplary NAND string 1850 includes a select gate structure 1851 and storage elements 1852, 1853, 1854, and 1855. The select gate structure 1851 includes an insulating layer 1878 formed on a substrate 12538.doc -30 - 200832403 plate 1885 - a conductive portion VIII - a conductive portion 1861. At the first, n, a conductive portion 1860 is provided. The first conduction Qiu 8 1861 and the second conductive portion 186 〇 邛 * * * * 组成 组成 组成 选择 选择 选择 选择 选择 选择 选择 选择 857 857 857 857 857 857 857. An "electrical portion 1849 insulates the first conductive portion eight-valued path, such as the seeker, and the second conductive portion from the second conductive portion 1859, which provides a light-conducting conductive portion to provide a protective portion 1858. ^二二传: The storage 7L piece includes a floating gate which is formed by the first transfer portion 4 and the second conductive portion knife π I. For example, as shown, the first conductive portion 865 and the second conductive portion 1864' for storage element purchase are respectively used for the first conductive portion 1869 and the second conductive portion of the storage element 1853! 8 6 8 ; the first conductive portion of the material element i 8 5 4 and the second conductive portion 1872; and the first conductive portion i877 and the conductive portion for the storage element 1855, respectively. Each of the storage elements further includes a control gate/word line portion, and the control gate/word line portions are insulated from the respective floating gates by respective dielectric portions of T. For example, as shown in the figure, the storage elements 1852, 18, and the control gate/sub-wire portions 1863, 1867, 1871, and 1875 are respectively used for the storage unit. Protected areas 1862, 1866, 1870 and 1874 are also provided for storage elements 1852, 1853, 1854 and 1855, respectively. Further, source/drain regions 1880, 1881, 1882, 1883, and 1884 are formed in the substrate 1885. In operation, a sufficiently high voltage vSGS is applied to the select gate 1857 to form an inversion layer 1 8 7 9 in the substrate 18 8 to allow current to flow. In addition, a voltage ~(3) applied to the coupling electrode 1856 is coupled to the control gate 1863 of the storage element 1852 and the floating gate (portions 1864 and 125538.doc -31 · 200832403 1865), and to the source/汲Polar region 1881, as discussed in conjunction with Figure i4. As described, the select gate structure 1851 can provide a benefit such as reducing gIDL. Specifically, a, the coupling (e.g., margin) between the coupling electrode 1856 and the floating gate of the storage element 1852 may allow a lower value of vP(}M to be used on WL0 during stylization.

Additionally, during the acquisition/verification process, the coupling electrode 1856 can interact with the floating gate of the storage member 1852. For example, consider storage element 1854 spaced from coupling electrode 1856. When the storage element 18 is read, a voltage in the range of about 0 volts to 4 volts is applied to the control gate 1871, and a read voltage in the range of about 5 volts to 6 volts is applied to the NAND. The control gates 其它^, i8_i875 of other storage elements in the string. The read voltage is just sufficient to turn on storage elements 1852, 1853, and 1855. In addition, the floating gates (conducting portions "" and "is" of the storage device 1854 will receive coupling effects from the adjacent control closures 1867 and 1875. However, when reading-end storage elements, only "from" The conventional components of the components are lightly coupled so that the set sensing voltage can be set higher. In contrast, with a selective gate structure having a face electrode as provided herein, the end storage element 1852 receives again from both sides. For example, about 4 volts to 8 volts can be applied to the coupling electrode 1856, and the sensing circuit 18e can be compensated accordingly to illustrate a cross-sectional view of the selected gate structure along the configuration of FIG. 18C. The select gate structure includes a third conductive portion (which provides a consuming electrode), a dielectric layer and a second conductive portion that extend in succession in the word line direction. The -th conductive portion is provided for each -NAND string And an insulating portion, and by a filler of 125538.doc -32 - 200832403 (such as SiOJ is isolated in the direction of the word line. The third conductive portion provides a common coupling electrode for the plurality of NAND strings, and the second conductive portion together with the a conducting part A select gate for each NAND string is provided together. The first conductive portion and the second conductive portion may be provided as two separately deposited polysilicon layers. In one approach, the first conductive portion is deposited, followed by shallow Channel isolation (STI) (4), wherein the first conductive portion is left as: and the strips extend along the NAND string. Then, the second conductive portion is deposited and also etched in the direction of the bit line. Depositing a dielectric layer and a third conductive portion, and etching the first conductive portion, the second pass V portion, the third conductive portion, and the dielectric layer toward the word line to provide separate portions that form a floating of the storage element The respective components of the gate. The mask used to etch the second conductive portion toward the bit line should be designed such that the mask retains the second conductive portion in the direction of the word line in a region of the selected gate structure Connected layers. The figure shows a cross-sectional view of the word line along the configuration of Figure 18c. Here, the individual floating gates are composed of the first conductive portion and the second conductive portion of each NAND string, and the first conductive portion is First The conductive portion has been separated in the word line direction /, bit 70 line direction, as discussed. The third conductive layer WL0 〇 Figure 18g shows the arrangement of the selected gate structure 1886 relative to the nand string and the word line. The shunting area 1887 and the contact point 1888. The gate voltage can be selected differently, and the gate is connected to the selected gate. In the method of the method, the method is the flow region, and the remaining portion passes through the third conducting portion and selects the closed pole level. The dielectric in the constituting region, thereby exposing the components of the second conducting portion. Points: 125538.doc -33- 200832403 Zone can be >t. Store 7 阵列 array area. See also Figure (10), Figure A cross-sectional view of the selected idler structure of the configuration of the middle edge 7F 々 Figure 18g. Next, a contact 1888 can be formed on the exposed features of the second conductive layer and connected to the control line that provides the VSGS. Figure 18i illustrates an overview of a process for fabricating an alternative embodiment of a semiconductor material having a selected gate structure. Step 189() includes forming a first conductive portion on an insulating layer of the substrate. Step 1891 includes performing a shallow trench isolation etch that etches the first conductive layer toward the bit line (e.g., NAND string). Step 1892 includes forming a second conductive portion. Step 1893 includes etching the second conductive portion toward the bit line to provide a second conductive portion strip on the existing first conductive portion strip. Step 丨894 includes forming a dielectric portion on the existing structure, and step 1895 includes forming a second conductive portion on the existing structure. Step 1896 includes etching the first conductive portion, the second conductive portion, the third conductive portion, and the dielectric layer toward the word line. Step 1897 includes optionally selecting a third conductive portion in a region of the gate structure to provide a shunt region. Step 1898 includes providing a contact in the shunt area to the second conducting portion. Step 1899 includes forming a source/drain region in the substrate. In view of the following, the operation of the N AND string having the selected gate structure as described above can be understood. Figure 19 illustrates an example of an array 1900 of NAND storage elements, such as the storage elements shown in Figures 1-3. Along each row, a bit line 19〇6 is coupled to a drain terminal 1926 for the drain select gate of NAND string 1950. Along each column of NAND strings, a source line 1904 can be connected to the source terminal 928 of the source select gate of 125538.doc -34-200832403 of all of the NAND strings. For examples of NAND architecture arrays and their operation as part of a memory system, see U.S. Patent Nos. 5,570,315; 5,774,397; and 6, 〇46,935. The array of storage elements (4) is divided into a plurality of storage element blocks. Like the flash EEPROM system, the block is the erase unit. That is, each block contains a minimum number of storage elements that can be erased together. Each block is typically divided into several pages. One page is a stylized unit. In a specific embodiment, individual pages can be divided into segments, and the segments can include a minimum number of storage elements that are written at a time as a basic stylized operation. One or more pages of data are typically stored in a list of storage elements. One page can store one or more sectors. One section includes user data and additional items (rhead). The additional item data typically includes an error correction code (ECC) that has been calculated from the user profile for that section. The controller-part (described below) calculates the song as it is programmed into the array, and also checks the coffee when it is read from the array. An alternative is to store / and / : other additional items in a different page than the user's profile (or even a different block). The user data of the spot is typically 512 bytes, which corresponds to the size of the magnetic zone (one). The additional item data is typically an additional 20 groups. A large number of pages form a block, for example, from 8 pages to a maximum of 32, 64 or even more. In some embodiments, a column of NAND strings includes a block. In her case, the memory storage component is erased by making the ρ erase voltage (eg, 20 volts) for a sufficient period of time, 125538.doc -35 - 200832403 and grounding the word line of the selected block. At the same time, the source line and the bit line are in a floating state. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and common source lines also rise to a significant fraction of the erase voltage. Therefore, a strong electric field is applied to the traversing oxide layer of the selected storage element, and since the electrons of the floating interpole are emitted to the substrate side, the data of the selected storage element is removed, typically by F〇wler_N〇rdheim Follow the mechanism. As the electrons move from the floating gate to the p-well, the selected storage component is limited

It was lowered. Erasing can be performed on the entire memory array, separate blocks, or other storage element units. Figure 20 is a block diagram showing a non-volatile memory system using a single column/row decoder and read/write circuits. In accordance with an embodiment of the present invention, the memory device 2G96 has read/write circuits for parallel reading and materialization of the gastric storage element. Memory device 2096 can include one or more memory dies 2098. Memory die 2〇98 includes a two-dimensional array of storage elements 1900, control circuitry 2〇1〇, and read/write circuitry (9). In some embodiments, the array of storage elements may be three-dimensional. Memory array 19 The system is addressed by a column decoder 203 by a word line and via a row of decoders 2 〇 6 〇 by a bit line. The read/write circuit 2065 includes a plurality of sensing blocks 2000, And allowing one page of storage elements to be read or programmed in parallel. Typically, a controller 2050 is included in a memory device (eg, a 'removable memory card) that is identical to one or more memory dies 2098. Commands and data are transmitted between the host and controller 2〇5〇 via line 2020, and a good path 2018 is transmitted between the controller and one or more memory dies 2098. 125538.doc * 36 - 200832403 The control circuit 201 0 cooperates with the read/write circuit 2〇65 to perform a memory operation with respect to the memory array 1900. The control circuit 2〇1 includes a state machine 2012, an on-chip address decoder 2014 and a Power Control Module 2016. Wafer level control of memory operations. The on-wafer address decoder 2014 provides an address interface between the hardware address used by the host or a memory controller and the hardware address used by the decoders 2030 and 2060. Power Control Mode Group 2016 controls the power and voltage supplied to the word lines and bit lines during memory operation. In some embodiments, some components may be combined. In various designs, one or more of the storage element arrays 19 The components (individual or combined) may be considered as a single official circuit. For example, one or more of the management circuits may include any one or a combination of the following: control circuit 2010; state machine 2012; decoder 2014, 2030 And 2060; power control module 2〇16; sensing block 2000' item fetch/write circuit 2〇65; controller 2〇5〇, etc. ® 21 shows use of double column/row decoder and read Block diagram of the non-volatile L-body system of the write circuit. Another configuration of the memory device 96 shown in Fig. 2A is provided. Here, the memory array is obtained by various peripheral circuits! Symmetrical at the opposite sides of the array The implementation is such that the density of the access line and circuitry on the female side is reduced by a factor of 2. Thus, the column decoder is split into column decoders 2030 and 2〇3〇6, and the row decoder is split into row decoders 2060A and 2〇6〇b. Similarly, the read/write circuit is divided into a read/write circuit 2〇65A (which is connected from the bottom end of the array 19 to the bit line) and the read/write circuit 2 〇 65B (which is connected from the top of the array to the bit line) in this way substantially reduces the density of the read/write module by a factor of two. 125538.doc •37- 200832403 The device of Figure 21 also includes a controller As described above with respect to the apparatus of Figure 20. 22 is a block diagram of an individual sensing block 2000 that is divided into a core portion (referred to as sensing module 2080) and a common portion 2090. In one embodiment, there is a separate sensing mode group 2080 for each bit line and a common portion for a group of multiple sensing modules 2080. 2090. In one example, a sensing block will include a common portion ^ 2090 and eight sensing modules 2080. Each sensing module in a group will pass through a data bus 2072 to communicate with the associated common portion. For further details, please refer to US Patent Application No. 2006/0140007, entitled "Non-Volatile Memory & Method with Shared Processing for an Aggregate of Sense Amplifiers", published on June 29, 2006. The content is incorporated herein by reference. The sensing module 2080 includes a sensing circuit 2070 that determines whether a conduction current in a connected bit line is above or below a predetermined threshold level. The sensing module 2080 also includes a one-bit line latch 2082 for setting a voltage strip/piece on the connected bit line. For example, latching in a bit element A predetermined state in line latch 2082 will cause the connected bit line to be pulled to a specified stabilizing state (e.g., VDD). Common portion 2090 includes a processor 2092, a set of data locks The memory 2094 and an I/O interface 2096 coupled between the set of data latches 2094 and the data bus 2020. The processor 2092 performs an operation. For example, one of the functions of the processor is to determine the sensed Storage component The stored data, 125538.doc -38 - 200832403, and store the data of the S-thinking in the set of data latches. The set of data latches 2094 is used to store the processor 2 during the read operation. The data bit determined by 〇92. The data latch is also used to store data bits imported from the data bus 2020 during the stylization operation. The data bits indicated are intended to be programmed into the memory. The data is written in. 1/〇 interface 2〇96 provides an interface between the data latch 2094 and the data bus 2〇2〇. During the item capture or sensing, the system operates in the state machine 2 Under the control of 〇12, the state machine controls the supply of different control gate voltages to the addressed storage element. With the gradual adoption of various predefined control gate voltages corresponding to the various memory modalities supported by the memory, sense The test module 2〇8〇 can sense one of the voltages, and will provide an output from the sensing module 2080 to the processor 2〇92 via the bus bar 2〇72. At this time, the processor 汕% borrows Considering the sensing events of the sensing module and The input line 2〇93 derives information from the state machine via the control gate to determine the resulting memory state. The processor then computes the binary encoding of the memory state and stores the resulting data bit in the data latch 2 In another embodiment of the core portion, bit line latch 2082 has a dual purpose as a latch for latching the output of sense group 2080 and also as described above. The bit line latch. It is contemplated that some embodiments will include multiple processors 2〇92. In one embodiment, each processor 2 〇 92 will include an output line (not shown in Figure 19) such that each output line is or wired (wired_〇R) together. In some embodiments, the output lines are inverted as before being connected to the or logical connection 125538.doc -39-200832403. This P ^ ^ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , For example, when each bit opens p, this, ^ ^ has reached its desired level, a logical "〇" of the bit will be sent to, or the logical connection line (or a data "1" is Reverse). When all the bits output one quintile (or one poor) 1 ” is reversed, the state machine knows to terminate the stylized ^, private because of the mother one processor and eight senses

The module communication 'reader must read or logically connect the line, or add logic to accumulate the result of the associated bit line to processor L so that the state machine only needs to read or logically connect the line-time . Similarly, the correct logic level is chosen by the global state machine to determine when the bit changes its behavior and changes the algorithm accordingly. During stylization or verification, the data to be programmed from the data bus 2020 is stored in the set of data latches 2094. Under the control of the state machine, the stylization operation includes a series of stylized voltage stampings applied to the control gates of the addressed storage elements. A read back (verification) is performed after each program pulse to determine if the storage element has been programmed to the desired memory state. The processor 2092 monitors whether the read back is erroneous with respect to the desired memory state. When the two § memories are in the same state, the processor 2 q 9 2 sets the locating element line latch 2082, causing the bit line to be pulled to a specified stylized inhibit state. This prohibits further programming of the storage element coupled to the bit line even if a program pulse is present on the control gate of the storage element. In other embodiments, during the verification process, the processor initially loads the bit line latch 2082 and the sensing circuit sets it to a disable value. 125538.doc -40· 200832403 The data latch stack 2094 contains a stack of data latches corresponding to the sense modules. In one embodiment, there are three data latches per sensing module 2800. In some embodiments, but not necessarily, the data latch is implemented as a shift register such that the parallel data stored therein is converted to serial data for data bus 2020 and vice versa. In a preferred embodiment, all of the data latches corresponding to the read/write blocks of the m storage elements can be linked together to form a block shift register so that Serial transmission to input or output a block of data. Specifically, the bank containing r read/write modules is adapted such that each of the group of data latches sequentially moves data into or out of the data bus as if it belonged to a bank. A component of the shift register for the entire read/write block. For additional information on the structure and/or operation of the specific embodiments of the non-volatile storage device, see: (1) U.S. Patent Application Publication No. 2004/0057287, filed on March 25, 2004, entitled "Non-Volatile Memory And Method with Improved Sensing; (2) US Patent Application Publication No. 2004/0109357, issued June 10, 2004, entitled "Non_Volatile Memory And Method with Improved Sensing"; 3) U.S. Patent Application Serial No. 11/015,199, filed on December 16, 2004, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation; (4) United States, filed on April 5, 2005 Patent Application No. 11/099, No. 133 entitled "Compensating for Coupling During Read Operations of

Non-Volatile Memory"; and (5) December 28, 2005 曰 Application 125538.doc -41 · 200832403 US Patent Application Publication No. 11/321,953 entitled, Reference Sense

Amplifier For Non-Volatile Memory. The entire contents of the five patent documents listed above are incorporated herein by reference. Figure 23 illustrates the § for all bit line memory architectures or for parity memory architectures. An example of a memory array organized into blocks. An exemplary structure of the load cell array/column 1900 is described. As an example, a NAND flash EEPROM that is divided into 1,024 blocks is described. The data stored in a block. In one embodiment, the block is simultaneously the smallest unit of the storage element. In this example, there is a corresponding bit line BL0 in each block. , BL1, ..., 8,851 rows of BL8511. In a specific embodiment called the All-Band Line (ABL) architecture (Architecture 23 10), a block can be selected simultaneously during read and program operations. All bit lines. The storage elements along a common word line and connected to any bit line can be simultaneously programmed. In the example provided, four storage elements are connected in series to form a _ NAND string. Included in each NAND string Storage elements, but four or more storage elements (eg, Μ, 32, 64, or other number) can be used. One terminal of the NAND string is via a drain select/gate (which is connected to SGD and CED) Connected to a corresponding bit line, and the other terminal is connected to a common source line via a source select gate (which is connected to sgs and CES). In another embodiment, 'the parity structure is' (Architecture 2300), the bit lines are divided into even bit lines (BLe) and odd bit lines (BL〇). In the odd/even bit line architecture, pairs are along a common word line and connected to odd bits. The storage elements of line 125538.doc -42- 200832403 are programmed once and another stylization is performed on the storage elements along a common word line and connected to the even bit lines. The material can be privately different at the same time. The data is read in and from the different blocks. In this example, there are 8,512 rows in each block, which are divided into even rows and odd rows. In this example, the figure shows four connections in series. Storing components to form a NAND string, although depicted in the figure Four storage elements are included in each NAND string 'but more or less than four storage elements can be used. During configuration of one of the read and program operations, 4,256 storage elements are simultaneously selected. The selected storage The elements have the same word line and the same bit line (for example, even bit lines or odd bit lines). Therefore, 532 bytes of data (which form a logical page) can be simultaneously read or programmed. And a block can store at least eight logical pages (four word lines, each word line has a countable page and an even number of pages). For a multi-state storage element, when each storage element stores two bits of data At the time, each of the two bits is stored in a different page, and one block stores 16 logical pages. Blocks and pages of other sizes can also be used. For an all-bit squall (ABL) architecture or an odd-even architecture, the storage element is erased by raising the well to an erase voltage (e.g., 20 volts) and grounding the word line of a selected block. The source line and the bit field are in a floating state. Erasing can be performed on the entire memory array, separate blocks, or other storage element units that are part of the memory device. Electrons are transferred from the floating gate of the storage element to the ρ well region, and the Vth of the storage element becomes negative. In the read and verify operations, the select gates (SGD and SGS) are connected to a voltage in the range of 2.5 volts to 4.5 volts, and the non-selected word lines are made (eg, 125538.doc -43.200832403, eg, when When WL2 is the selected word line, WLO, WL1, and WL3 are non-selected word lines) rise to a read transfer voltage VpASs (typically in the range of 4·5 volts to 6 volts) to enable the transistor to operate as a transfer gate. pole. The selected word line WL2 is coupled to a voltage that is specified for each read and verify operation to determine if the Vth of the associated storage element is above or below the bit/quasi. For example, in a read operation for a two-bit quasi-storage element: the selected word line WL2 is grounded such that it is detected whether its Vth is above zero. In a verify operation for a two-bit storage element, the selected word, line WL2 is connected to, for example, 88 volts, to verify that its v four has reached at least 0.8 volts. The source and p wells are in the dormant. The selected bit line (assuming an even bit line) is precharged to, for example, a level of 〇7 volts. If the VTH on the word line is above the read or verify level, the potential level associated with the bit line (BLe) associated with the storage element is maintained at a high level due to the non-conducting state storage element. On the 3rd, if the Vth is lower than the read or verify level, the potential level of the bit line (BLe) involved is reduced to a low level (for example, less than ^• volts). Yuan line discharge. Thereby, # is connected by the voltage comparator sense amplifier of the μ bit line. The technique of erasing, reading and detecting as described above is carried out. Therefore, the familiarity operation system can be changed according to the technology in this technology. Verification techniques well known in the art can also be used. τ item selection Figure 2 4 shows the exemplary limit of the data array of the two-element data storage array. For a erased storage component, 125538.doc •44- 200832403 provides a first threshold voltage distribution of £. Also, draw three threshold voltage distributions A, 13, and C for the stylized storage component. In a specific embodiment, the threshold voltage g voltage in the E distribution is positive. The threshold in the distribution of the negative values 'A, ^C' Each of the distinct threshold voltage ranges corresponds to a predetermined value for each set of data bits. The specific relationship between the data programmed in storage (4) and the threshold voltage level of the storage element depends on the data encoding scheme used for the storage element. For example, U.S. Patent No. MUM No. 4 and U.S. Patent Application Serial No. 2004/025 5090, issued Dec. 16, 2004, the entire contents of which are hereby incorporated by reference: Various f-coded schemes for multi-state fast-storage elements. In a specific embodiment, 'using a Gray code (Gray-assignment, assigning data values to the threshold voltage ranges such that if a floating gate is The threshold voltage is erroneously offset to its neighboring physical state, then only one bit will affect the text. An instance assigns "u " to the threshold voltage range e (state E); assigns "10" to Limit voltage range A (state A); assign "〇〇" to the threshold voltage range B (state B); and assign "01" to the threshold voltage range c (state c). However, in other implementations In the example, the Gray code is not used. Although four states are illustrated, the present invention can also be applied in conjunction with other multi-state structures (including multi-state structures having four or more states). Three read reference voltages Vr for reading data from the storage component a, Vrb and Vix. By testing whether the threshold voltage of a given storage element is higher or lower than Vra, Vrb and Vrc, the system can determine the state of the storage element. 125538.doc -45- 200832403 In addition, provide Three verification reference voltages Vva, Vv^Vvc. When the storage element is programmed to state_, the system will test whether the storage element has a large threshold voltage. When the storage element is programmed to state B, the system will test whether the storage element is Has a threshold voltage greater than or equal to Μ. When the material element is programmed to state c, the system will determine whether the storage element has a threshold voltage greater than or equal to Vvc. In the specific embodiment, the full sequence is named Stylized, the storage element can be directly programmed from the erased state E to any of the programmed states a, B or C. For example, a group of storage elements to be programmed can be wiped first. In addition, all the storage elements in the group are erased E. Then, a series of program pulses (such as the control gate voltage sequence shown in Figure 3) are used to directly program the storage elements. To state A, B or C. When some storage elements are being programmed from state e to state a, the other storage elements are being programmed from state E to state b and/or from state E to state C. Compared to the voltage change on the floating gate under WLn when staging from state E to state A or from state E to state b on WLn, when morphing from state E to state c on WLn at WLn The amount of charge change on the lower floating gate is the largest, so the parasitic coupling amount to the adjacent floating gate under WLn-1 is the largest. When the state E is programmed to the state B, the coupling amount to the adjacent floating gate is reduced. Small but still significant. When the state E is programmed to the state A, the coupling amount to the adjacent floating gate is further reduced. Accordingly, the amount of correction required to subsequently read each state of WLn-1 will vary depending on the state of the adjacent storage elements on WLn. 25 illustrates an example of a two-stage process 125538.doc-46-200832403 (tw〇-Pass) technique for a stylized multi-state storage element that stores two different pages (the next page with - The information on the upper page). The figure shows four states: state E (11), state A (10), state B (〇〇), and state c (eight). For state E, the two pages store q". For state a, the lower page stores τ and the upper page stores "1". For state B, the two pages store "〇". For state C, the lower page stores "1" and the upper page stores "0". Note that although a particular bit pattern has been assigned to each state by I, different bit patterns can be assigned. In the first stylization process, the threshold voltage level of the storage element is set according to the bit to be programmed into the lower logical page. Logic-, because it has been erased earlier, is appropriate: Second, the threshold voltage is not changed. However, if the bit to be programmed is a logic, the threshold voltage level of the storage element is increased to state A, as indicated by arrow 2500. This causes the first stylization process to terminate. In the second stylization process, the threshold voltage level of the storage element is set according to the bit being programmed into the upper logical page. If the upper logical page bit is storing logic ', then since the storage element is in the state or A (depending on the stylization of the lower page bit), both states have the upper page bit " 'So there is no stylization. If the upper page bit system logic "0" ', the threshold voltage is shifted. If the first process causes the memory element to remain in the erased state E, then in the second phase, the memory element is programmed such that the threshold voltage is increased to the state C range, as indicated by arrow 2520. If the first stylization process causes the storage element to be binarized to state A', then the storage element 125538.doc •47·200832403 is further programmed in the second process, causing the threshold voltage to be increased to state B Within the scope, such as the arrow 25 〇 〇 do not. The result of the third process is to normalize the storage component to the state specified for: the upper page stores the logic "〇", and does not change the information on the lower page. In Figs. 24 and 25, the light junction to the floating gate on the adjacent bit line is in the final state.

In a specific embodiment, a system can be set up to perform a full sequence of writes if sufficient data is written to fill the full page. If the data is not sufficient to write a full page, the stylization process can program the next page with the received data. When receiving subsequent data, the system will then program the upper page. In another embodiment, the system can begin writing in the pattern of the programmed lower page, and if sufficient data is subsequently received, the conversion: full sequence stylized mode to fill the entire (or large Most) storage of word lines. For more details on this specific example, please refer to the US Patent No. 2嶋m26 in the US Patent Announcement on June 15th, 2nd. The title is "Pipelined Pr〇g face ming Gf NQn_VGlatile 仏如如. (iv) Early Data", the entire contents of which are incorporated herein by reference. Figures 26a through 26c illustrate another effect for staging a non-volatile memory that reduces the floating gate to floating gate coupling by: for any particular storage element, the writer is adjacent to After storing the first page of the component, it is written to a particular page of the particular storage component. In an exemplary embodiment, each of the non-volatile storage elements uses four lean states to store two bits of data. For example, assume that state E is in an erased state' and state A is a stylized state. State e stores data 11. Sorrow A storage data 〇 1. Status B stores data丨〇. Shape 125538.doc -48· 200832403 State C storage data〇〇. This is an example of a non-Gray code because the two bits are changed between adjacent states. Other materials can also be used to revise the physical data status. Each storage element stores two pages of data. For the purpose of kites, their pages will be referred to as the upper and lower pages; however, other titles may be given. Regarding state A, the upper page stores the bit ^ the lower page stores #bit i. Regarding state B, the i page stores the bit and the lower page stores bit 0. Regarding state c, both pages store bit data 〇.

The stylization process is a two-step process. In the first step, the lower page is privateized. If the lower page is to maintain the data! , the storage component status is maintained in the shape HE. If the data is to be stylized as 〇, then the threshold voltage of the storage element is raised' so that the storage element is programmed to state B. Thus, Figure 26A illustrates the staging of the storage element from state (4) to state & State & Transition state B; therefore, the verification point is depicted as Vvb, which is lower than. & In the specific embodiment, the storage element is stylized from the gE to the B and then the next page of the adjacent storage element (machine η+ι) in the NAND string will be programmed. For example, please refer back to Figure 3. After the lower page of the storage element 346 is programmed, the lower page of the storage element 345 will be programmed. After staging the storage element 345, if the threshold voltage of the storage element 345 rises from state E to state b, the floating gate to floating terminal consuming effect will cause the apparent threshold voltage of the storage element 346 to rise. This will have the effect of widening the threshold voltage distribution of state B to the threshold voltage knife 2650 as depicted in Figure 26B. When the upper page is programmed, the apparent widening of the threshold voltage distribution will be remedied. . If the storage component is in the process of depicting the stylized upper page in Figure 26C, 125538.doc -49- 200832403

In addition to state E and the upper page is maintained at ^, the health element will remain in state E. If the (4) system, the (4) state E, and the upper page are to be programmed to 〇, then the threshold of the 4 storage element will rise, so that the storage element is at ^ A if the storage element is in the middle threshold (4) distribution 2 (four) and The P page 4 is held at 1 'and the storage element will be programmed to the final state B. The mass storage element is in the middle threshold voltage distribution 2 (four) and the upper page is I: into the data G, then the threshold current of the storage element will rise, so that the storage element is in state c. The process depicted in Figures 26A-26C reduces the floating gate to floating gate engagement effect because, only adjacent to the upper portion of the storage element, the page will affect the apparent threshold voltage of a given storage element. An example of an alternative state code is when the upper page data is "received, then moved from distribution 2 (four) to sinus C, and when the upper page data is Q, then moved to state b. Although Figures 26A-26C provide a The concept of four data states and two pages of information can be applied to the application of more or less than four data states and different from the two pages. Figure 27 is a diagram depicting stylized non- A timing diagram of various embodiments of a volatile memory process. The horizontal axis is for time in microseconds. The illustrated time period represents a period during which a program pulse is applied to a selected word line. The bit line voltage vBL of the NAND string is depicted; the waveform 2705 depicts the pass voltage vPASS, which is applied to the unselected word line, eg, the word line that is not currently used for programming; the waveform 2710 depicts the programmed voltage Vpgm 'which is applied To the selected word line for stylization; waveform 2715 depicts the voltage potential present in the channel of the NAND string; waveform 2720 depicts the voltage applied to the selected gate structure when the source line end word line of the selected word line is selected ; 125538.doc -50- 200832403 and waveform 2725 depict the voltage applied to the selected gate structure when the selected word line is not the source side end word line. First, at 3 microseconds, a source voltage VsRC (not shown) is from The squat rises to a level such as 2.5 volts. See Waveform 27〇〇, at 5 microseconds, the VBL for non-selected NAND strings rises from 0 volts to VcD, ίν林1丄τ~bl(b)υππ King VsRC, to prohibit stylization in associated non-volatile storage elements. In this example, the Vbl for the selected NAND string is maintained at idle during stylization.

The value of VBL for the selected NAND string can be between the ramp and Vsrc to reduce the stylization speed without completely disabling stylization, such as in the fine stylized mode of coarse/fine stylization techniques. Waveform 2705 depicts voltage vUW1 applied to a non-selected word line. It is set to the pass voltage VPASS and corresponds to the voltage across the control gate of the storage element connected to the non-selected word line. VpASdf, a boost voltage for boosting the voltage in the channel of the substrate. Specifically, Vuwl rises to VSRC at 5 microseconds to allow pre-charging, and then rises to about 9 volts at 10 microseconds to boost the nAND string associated with the non-selected bit line. v

PASS is maintained on the unselected word line until approximately 35 microseconds. Waveform 2710 depicts the voltage vSWL on the selected word line, which rises to VSRC at 5 microseconds to allow for pre-charging. Between 15 microseconds and 35 microseconds, the program pulse VPGM is applied. In one example, the program pulse can range from i2 volts to 21 volts. Waveform 2715 depicts the voltage (VNAND) in the NAND string channel, for example, in the active area of the substrate. In a non-selected NAND string, VNAND first transitions to a pre-charge level and then boosts to approximately 7.5 volts to disable programming of the 125538.doc -51-200832403 selected storage elements while in the selected string D string V_=0 to allow for stylized selected library components. Waveform 2720, in addition to depicting the pole side selection gate electric dust ν (10) and the box electrode current (10) respectively (these electromigration is applied to the drain side selection gate structure), respectively, also describes the source side selection closed pole electric waste Vsd. The face electrode is electrically VCES (the other power M is applied to the source side selection gate structure). In this case, the selected word line is the source side end word line, known as the chyle. As described above, depending on the position of the non-volatile storage element currently being programmed in the _string, or the position of the corresponding selected word line in the plurality of word lines, the stencil is applied to the light-closing electrode. What about electricity? In one approach, the current selected sub-line is the source side end of the sub-line (ie, 'the sub-line adjacent to the source-side select gate structure'). vCES is set to an elevated level above Vsgs, such as 8 Volts or other voltage levels that the associated dielectric can withstand during stylization. The voltage level at which the associated dielectric can withstand can be based on a number of factors, such as dielectric material, dielectric thickness, age, and number of programmed cycles. For example, a value can be obtained from an experiment. When the selected word line is other than the word line outside the source side end word line, it is also possible to recognize Vc£s to the level of the rising back. Vsgs is set to a level such as a sag to keep the source side select gate off. After a brief precharge to a level such as a higher 5 volts, VSGD is set to a level such as 2.5 volts to maintain the drain side select gate open. Vced can be set to a constant stagnation or can follow vSGD. In addition, coordinated control of %print and Vsgd (including ramping or ramping VcED and VSGD_ towards the same polarity direction, as shown in Figure 2) provides coupling to each other such that their charging or discharging will be enhanced. In general, 125538.doc -52- 200832403 says that the voltage of the selected gate and the light-closing electrode applied to the source-side selective idler structure or the non-polar-side selective closed-pole structure can be ramped up or down at the same time, so that they are mutually inclined The face will enhance its charging or discharging. In the other-(four) generation scheme, set v(10) to a relatively high level (such as the level of v(10)), which is why it assists channel boosting and then assists in stylization. Waveform 2 7 2 5 depicts when the selected word line is not the source side end word line

Vsgs, VcES, VsgA VcED. In this case, VCES is set to the level of reduction, such as 0 volts, '51* 46, you Λ7

/, followed by VSGS. Set Vsgd and I as indicated in the previous case (waveform 2720). In general, when the selected word line: is the source side end word line, the benefit of providing an elevated voltage on the source side light combining electrode can be weakened. In this case, the VCES has a passive role. 1 Note § When using a gateless gate with selective gate and junction electrodes, the control can be similar to the waveforms 2720 and 2725. In particular, V(10) can be raised 'up' when the word line on the test side of the word line is selected and is reduced in other cases to follow VSGD. In other words, when the selected word line is not at the end of the word line, 乂(10) and Vces can be set according to the waveform help indication, but VCED and vCES are exchanged. As noted, when the non-volatile storage element is threaded adjacent to the word, the elevated voltage can be used for the coupling electrode to reduce the GIDL. This improved efficiency and allows for the use of a reduced maximum VPGM. In addition, it may be desirable to use elevated VCES and/or VcED when the selected word line is not directly adjacent to the select gate. The level of VcEs and / or vCED can also be changed depending on the level of the selected word line. Another option is to allow vCES&/ or VcED to be floating when the selected word line is adjacent to the select gate 125538.doc •53-200832403. Figure 28 is a timing diagram depicting various specific embodiments of the process of reading a non-volatile memory. The horizontal axis is about the time in microseconds. The time period illustrated represents a cycle in which a read operation is performed, for example, verifying whether the storage element has been programmed or reading data from a previously stylized storage element. Waveform 2800 depicts bit line voltages Vbl for two read options (referred to as NAND strings of options A and ..., waveform 28〇5 depicts read voltage VREAD, which is applied to non-selected word lines, eg, a word line associated with a storage element that is not currently being read; and a waveform 281 〇 depicting a read control gate voltage VCGR that is applied to the selected word line (eg, associated with one or more of the currently read The control gate of the storage element of the word line of the storage element. Waveform 2815 depicts the voltage potential present in the channel of the non-selected NAND string (eg, a NAND string associated with a storage element that is not currently being read); And waveform 2820 depicts the voltage present in the channel of the selected NAND string (eg, the NAND string associated with the currently being stored storage element) for two read options. Waveform 2825 is depicted for two reads. The options of VsGD, VCED, VsGS, and VCES are taken. In waveform 2805, the selected Vread level is sufficiently higher than the threshold voltage of the storage element to ensure that the non-selected storage element is in conduction or turn-on state. For state E, A, The threshold voltages of 8 and c can be -2 volts, 0 volts, 2 volts, and 4 volts, respectively, and Vread can be 6 volts. In a read option (option A), for example, at t = 22 microseconds When the 乂808 is raised, the source side selection gate is turned on, as shown in the waveform “Is it 125538.doc-54-200832403. This provides a path for consuming the charge on the bit line. It can also make vCES along with VSGS. Rise or fix the VCES at a steady state level, for example, crouching. VSGD starts to rise at t = 〇 microseconds, so the gate selection gate is turned on. It can also cause vCED to rise with vSGD or fix vCED at Steady-state level. If the threshold voltage of the storage element selected for reading is greater than vcgr (the read level applied to the selected word line), the selected storage element will be unturned and the bit line will not be discharged. As shown in waveform 2800 (,, VBL is not discharged "). For example, for 4 fetch operations 'VCGR can be set to Vra, Vrb or Vrc, for verify operation' VCGR can be set to Vva, Vvb or Vvc (Fig. 26C). In this case, the VNAND of the selected NAND string is not dissipated, as shown by waveform 2820. If selected for reading If the threshold voltage of the storage component is lower than Vcgr, the selected storage component will be turned on (on) and the bit line will be discharged, as shown by waveform 2800 ("Vbl discharge"). In this case, the selected nand The string of vNANDs will dissipate as shown by waveform 2820. At some point between 22 microseconds and 4 microseconds (as determined by the particular implementation), the sense amplifier will measure the elevated BL voltage To determine if the bit line has consumed enough. At t = 4 〇 microseconds, Vsgs, VcES, % sen and Vc £d are lowered to a steady state level (or another value for standby or recovery). For the second read option (option B), the sense circuit and the array of storage elements measure the conduction current of the storage element based on the rate of charge of a dedicated capacitor in the sense amplifier. For example, at t = 5 microseconds, the source side selection gate is turned on by raising VsGs as shown by waveform 2825. VSGD also starts to rise at t = 5 microseconds, so the gate is selected to be turned on. It is possible to raise v(f) as the yang 5 rises or fix the VcEs at the steady state level and can cause the mark to rise with 125538.doc -55-200832403 ▽(10) or fix v(10) at the steady state level. The sense amplifier keeps the bit line voltage constant, regardless of the ongoing operation of the NAND string, so that the sense amplifier is clamped at the bit line, and the current in the flow is measured at this voltage. At t= After 5 microseconds and a certain time point before t=4〇 microseconds (determined according to the specific scheme), the sense amplifier will consume enough capacitors in the mosquito sense amplifier. At t=40 microseconds, Vsgs, and 乂^0 are reduced to a steady state value (or another value for standby or recovery). Note that in other embodiments, the timing of some waveforms can be changed. Figure 29 depicts the program A flowchart of a specific embodiment of a non-volatile memory method. In an embodiment, the health-storing component (in blocks or other units) is erased prior to stylization. In step 29, one, The data loading '' command is issued by the controller and is received by the control circuit 2〇1〇 (Fig. 2(9). In step 2905, the address data of the specified page address is input from the controller or the host to the decoder 2014 At step 2910, one of the pages addressed The page stylized data is input to the data buffer for programmaticization. The data is latched in the appropriate set of latches. In step 2915, a "stylized" command is issued by the controller to the state machine 2丨2. By the triggering of the π program" command, the stepping pulses 3010, 3020, 3030, 3040, 3050, ... applied to the appropriate word lines as shown in FIG. 3A are controlled by the state machine 2012 to be in the step The data latched in 2910 is programmed into the selected storage element. At step 292, the programmed voltage core (10) is initialized to a start pulse (eg, 12 volts or other value), and the state machine 2 〇 12 maintains one The privateization counter PC is initialized to 〇. At step 2925, a first VPGM pulse is applied to the selected word line to begin stylizing the storage elements associated with the 125538.doc - 56 - 200832403 selected sub-line And a suitable voltage is applied to the non-selected word line, the source side select gate and the coupling electrode, and the drain side select gate and the coupled electrode. For example, as shown in step 2926, for the source side coupled electrode Voltage and / or for bungee The voltage of the coupling electrode can be set according to various programming criteria, such as the position of the selected word line, the temperature, the program pulse level or number, the number of device cycles, and the number of programmed smuggling times when using multi-process programming. 31 & to 31. Further combinations of different criteria may be used. The voltage for the source side coupling electrode and/or the voltage for the drain side coupling electrode may also be set according to other criteria, such as A quasi-criteria related to the reading process or the verification process. If the logic "〇" stored in a particular data latch indicates that the corresponding storage element should be programmed, then the corresponding bit line is grounded. If the logic stored in the -specific latch, 丨" indicates that the corresponding storage element should maintain its existing data state, then the corresponding bit line is connected to VDD to disable stylization.

125538.doc Selected storage component. At step 2935, the pose mechanism knows that it has been determined whether all of the resources are stored in the logic "". If so, because all of the selected storage elements have been programmed and verified To the target state, so the stylization process is completed and successful, and in step _ report "pass" in step 2935 'If it is determined that not all data latches are storing logic "1", the stylized handler Continuing. At step 2945, the stylized counter PC is checked against a stylized limit value PCmax. An example

The stylized limit is 20; however, other values can be used. If the program counter PC is not less than PCmax, the stylization process has failed and the 2950 reports a "Failure" (FAIL) status. w If the program counter % is less than PCmax, the VpGM level is increased by the step size, and the program is incremented in step 2955, and the loop returns to step 2925 to apply the next vPGM pulse. Figure 30 illustrates a voltage waveform 3_' including a series of program pulses 30H), 3020, 3030, 3040, 3050, ..., which are applied to word lines selected for programming. In the example, the program pulse voltage Vpgm starts at 12 volts and is incremented by increments (eg, 0.5 volts) for each successive program pulse until a maximum of 21 volts is reached. A set of verify pulses 3012 is interposed between the program pulses. , 3022, 3032, 3042, 3 052, .... In some embodiments, there may be a verify pulse for each state in which the data is being programmed. In other embodiments, 'there may be more or more Fewer verification pulses. For example, the amplitude of the verify pulses in each set of verify pulses can be Vva, Vvb, and Vvc (Fig. 25). In one embodiment, the data is threaded along a common word to store 125538. .doc -58- 200832403 Archives Therefore, before the program pulse is applied, the word line for the stylization is selected. This word line is called the selected word line. The remaining word lines in a block are called non-selected word lines. There may be one or two adjacent word lines. If the selected word line has two adjacent word lines, the adjacent word line on the non-polar side is called the m side (four) 纟 line, and rides on the adjacent word line of the source (four) 彳Referring to the source side adjacent word line. For example, if the word line WL2 of FIG. 3 is the selected word line, then (4) the source side is adjacent to the word line and the wl3 system is (4) adjacent to the word line. Each includes a row-group bit line and a column word line forming a column. In the specific embodiment, the bit line is divided into an even bit line and an odd bit line. As discussed in conjunction with FIG. Performing a stylization of the storage elements along a common word line and connected to the odd bit lines, and performing another stylized odd/even (four)ization on the storage elements along the common word line and connected to the even bit lines ;). In another embodiment, all bytes along the block are threaded along a word. Save the component ("all bits are threaded"). In JL, it is the beginning of the process, 匕, 匕, 体, 体, in the case of the shell, you can subdivide the bit line or block into other groups (for example, Left and right, more than two groups, etc.) Figure 31a shows the relationship between the coupled electrode house and the selected word line position. In the chart shown, the horizontal axis is labeled for 32 word lines. The word line number of the string (which is from the source side (eg, 鸠) extension # to the immersion side (10), eg WL3D)' and the vertical axis indicates the voltage level. In this example, for one of the sources side or Multiple selected word lines, providing elevated levels of VCES (with real ride *) 'and # higher word lines are selected when the selected word line is lowered. Similarly, for one or more selected word lines on the non-polar side, 125538.doc -59-200832403 is provided for the raised level vCED (shown in dashed lines), and when the lower word line is the selected word line Decrease VCED. Figure 31b shows the relationship between the threshold voltage and temperature and between the coupled electrode voltage and temperature. In the chart shown, the horizontal axis indicates temperature 'and the vertical axis indicates electricity-. Specifically, it has been observed that the threshold voltage (Vth) of the non-volatile storage element decreases as the temperature increases. The change in voltage with respect to temperature is expressed as a temperature coefficient (α), which is typically about mV/°C. For example, with a range of operations from _4 to +8, the variation of the threshold electric grinder can be about (85-(_40))x(_2)=25〇 mV. The temperature coefficient depends on various memory device characteristics such as doping, layout, and the like. Accordingly, in one approach, the coupling electrode voltage can increase with increasing temperature to provide further assistance in increasing the vTH of the storage element. Figure 3C depicts the relationship between the coupling electrode voltage and the number of cycles of the memory device. Since the memory device has undergone multiple stylization and erase cycles over time, the storage elements generally become easier to program and can use fewer program pulses to bring the storage elements to their target stylized state. Accordingly, in the practitioner's practice, by reducing the coupling electrode voltage, the assistance provided by the coupling electrode is reduced as the number of cycles increases. For this purpose, a count of the number of cycles maintained by the memory device can be used. Figure 31 d shows the relationship between the voltage of the combined electrode and the number of pulses or voltage of the program. During the & characterization period, as successive program pulses with higher amplitudes are applied to the selected word line (see Figure 30), the coupling electrode can be assisted by increasing the level of the coupling electrode voltage. The amount increases. Therefore, depending on the number of program pulses (eg, -, second, third, etc.), and / 125538.doc -60 - 200832403 or similarly depending on the level of VPGM (eg, 10 volts, 11 volts, etc.) To adjust the coupling electrode voltage. Figure 3 1e shows the relationship between the coupled electrode voltage and the number of stylized processes for multi-process stylization techniques. For multi-process stylization techniques (such as the multi-process stylization techniques shown in Figures 25 through 26c), it may be advantageous to adjust the coupling electrode voltage in accordance with the stylizing process that is occurring. In a method of 'being', the first stylization process causes the Vth of the stylized storage element to increase more than the second stylization process, resulting in augmentation of the stylized storage element. In this case, in the first process, more assistance from the coupling electrode is required, so the coupling electrode voltage is increased in the first process. Embodiments of the present invention have been presented above for the purposes of illustration and description. The invention is not intended to be exhaustive or to limit the invention. Many modifications and variations are possible in light of the above teachings. The specific embodiments are chosen to best explain the principles of the invention and the application of the invention, use. The scope of the invention is intended to be defined by the scope of the appended claims. / [Simple diagram of the diagram] / Figure 1 shows a top view of two adjacent NAND strings with a selected gate structure. Figure 2 is an equivalent circuit diagram of the N AND string of Figure 1. 3 is a circuit diagram of three n AND strings with select gate structures. Figure 4a shows a cross-sectional view of a NAND string having a dual voltage select gate structure. 125538.doc -61- 200832403 Figure 4b is a cross-sectional view of the storage element of the NAND string of Figure 4a. 5 through 14 illustrate a process for fabricating a NAND string having a dual voltage select gate structure. Figure 5 illustrates a cross-sectional view of an unpatterned layered semiconductor material. Figure 6 illustrates the semiconductor material of Figure 5 after the photoresist has been deposited. Figure 7 illustrates the semiconductor material of Figure 6 after a portion of the dielectric layer has been removed. Figure 8 illustrates the semiconductor material of Figure 7 after the second conductive layer has been added. Figure 9 illustrates the semiconductor material of Figure 8 after the protective barrier has been added. Figure 10 illustrates the semiconductor material of Figure 9 after portions of the second conductive layer have been removed. Figure 11 illustrates the semiconductor material of the Figure after deposition of a protective layer. Figure 12 illustrates the semiconductor material of Figure 11 after removing portions of the first conductive layer and dielectric layer and forming source/drain regions. Figure 13 illustrates the semiconductor material of Figure 12 after sidewall spacers are formed. Figure 14 depicts the semiconductor material of the studded Figure 13 including the voltage applied to the select gate, the coupled electrode of the select gate structure, and the voltage coupling from the coupled electrode. Figure 15 depicts an alternative semiconductor material. Figure 16 depicts a NAND string including the semiconductor material of Figure 13. Figure 1 7a depicts an overview of the process used to fabricate semiconductor materials having a selected gate structure. Figure 171) depicts a detailed process that is not used to fabricate the semiconductor material of Figure 13. Figures 18a through 181 relate to another embodiment of an nAND string 125538.doc-62 - 200832403 having a dual voltage selective gate structure. Figure 18a depicts another embodiment of a string having no dual voltage selective gate structure. Figure 18b is a cross-sectional view of the storage element of the NAND string of Figure 18a. Figure 18c illustrates the configuration of the select gate structure relative to the NAND string and word line. Figure 18d shows a cross-sectional view of the NAND string along the configuration of Figure 18c. Figure 18e is a cross-sectional view of the selective gate structure along the configuration of Figure 18c. Figure 18f is a cross-sectional view of the word line along the configuration of Figure 18c. Figure 1 8g shows the arrangement of the select gate structure relative to the nand string and the word line, with the shunt area and junction being depicted. Figure 18h is a cross-sectional view of the selected gate structure along the configuration of Figure 18g. Figure 18i illustrates a process summary for an alternate embodiment for fabricating a semiconductor material having a selected gate structure. FIG. 9 is a block diagram showing an array of NAND flash storage elements. Figure 20 is a block diagram showing a non-volatile memory system using a single column/row decoder and read/write circuits. Figure 21 is a block diagram showing a non-volatile memory system using a dual column/row decoder and a read/write circuit. 22 is a block diagram of a particular embodiment of a sensing block. Figure 23 illustrates an example of organizing memory arrays into blocks for all bit line memory architectures or for parity memory architectures. Figure 24 depicts an exemplary set of threshold voltage distributions. Figure 25 depicts an exemplary set of threshold voltage distributions. Figures 26a-c illustrate various threshold voltage distributions and describe the process for stylizing non-volatile 125538.doc -63 - 200832403 hair memory. Figure 27 is a timing diagram showing various specific embodiments for describing a programmed non-volatile memory process. Figure 28 is a timing diagram depicting various specific embodiments of the process of reading a non-volatile memory. • Figure 29 shows a flow chart depicting a specific embodiment of a stylized non-volatile memory process. * Figure 30 illustrates an exemplary waveform of the control ® gate applied to a non-volatile storage element during stylization. Figure 3la illustrates the relationship between the coupled electrode voltage and the selected word line position. Figure 3 lb shows the relationship between the threshold voltage and temperature and the voltage between the coupled electrode and the temperature. Figure 3 1c illustrates the relationship between the voltage of the coupled electrode and the number of cycles of the memory device. Figure 3 Id shows the relationship between the coupling electrode voltage and the number of pulses or voltage. • Figure 3 1e shows the relationship between the coupled electrode voltage and the number of stylized processes for multi-process stylization techniques. [Description of main component symbols] 100, 102, 104, 106, 150, transistor 152, 154, 156 100CG, 102CG, 104CG, control gate 106CG, 150CG, 152CG, 125538.doc -64 - 200832403

342, 347, 3 62, Select gate structure 154CG, 156CG 100FG, 102FG, 104FG, 106FG, 150FG, 152FG, 154FG, 156FG 108 110 120 130 112 140 142 146 160 162 166 170 320, 340, 360, 400, 450 321, 341, 361 322, 327, 367, 410 323-326, 343-346, 363-366, 440, 452, 460 412 414 Floating Gate Source Side Coupling Electrode (CES) Source Side Select Gate Structure Source Polar contact bit line contact source side select gate (SGS) Source side select gate structure drain side select gate (SGD) drain side coupled electrode (CED) source side select gate structure source Polar side coupling electrode (CES) source side selection gate (SGS) source line contact NAND string bit line storage element third conduction part dielectric layer 125538.doc -65 - 200832403

416 418 420 422 424 426 428 430 454 454 456 470 472 474 476 478 500 510 520 530 540 600, 700, 800, 900, 1000, 1100, 1200 620 Protection barrier second conducting part first conducting part insulating layer source / > and polar region filler p well region η well region substrate control gate region (control gate / word line) floating gate region protection barrier second conduction portion dielectric first conductive portion insulator layered semiconductor material substrate Layer insulating layer first conductive layer dielectric layer semiconductor material photoresist layer 125538.doc 66- 200832403 810 910 922, 923, 924, 925, 926, 927 1010 1020 1022, 1023, 1024, 1025, 1026, 1027 1110 1112, 1114 1120 1202, 1204, 1206, 1208, 1210 1224, 1225, 1226, 1227, 1230 1250, 1252, 1254, 1256, 1258 1260 1265, 1270, 1275, 1280 1304, 1306, 1308, 1310, 1312, 1314, 1316 , 1318, 1320, 1322 1410 second conductive layer mask protection barrier (protection zone) gap one of the first conductive layer part of the second conductive layer part (control gate) protective layer protective layer part of the mask dielectric part first conduction Layer part source/potential region selection gate junction Storage element spacer inversion layer maximum curvature point 125538.doc -67- 1420 200832403 1430 selection gate 1440 coupling electrode 1500 alternative semiconductor material 1502 dielectric layer 1510 protective layer 1560 alternative selection gate structure 1600 configuration 1610, 1620, 1630 NAND string 1612 non-volatile storage element 1614 drain side select gate structure 1622 source side select gate structure 1624 a series of non-volatile storage elements 1626 drain side select gate structure 1632 source side select gate structure 1634 Volatile storage element 1800, 1830 NAND string 1802 storage element 1804 control gate/word line 1807 second conductive portion 1808 protection barrier 1809 selective gate structure 1809 first conductive portion 1810 third conductive portion 1812 dielectric 125538.doc - 68-

200832403 1814 1815 1816 1818 1820 1822 1824 1826 1831 1832 1834 1836 1838 1839 1840 1841 1849 1850 1851 1852, 1853, 1854, 1855 1856 1857 1858 1859 125538.doc -69- Second conducting part first conducting part insulating part source / > and polar region filler p well region η well region substrate storage element protection barrier third conduction portion dielectric second conduction portion first conduction portion insulator selection gate structure region dielectric portion NAND string selection gate structure storage Component coupling electrode selection gate protection portion third conduction portion

200832403 1860 1861 1862, 1866, 1870, 1874 1863, 1867, 1871, 1875 1864 1865 1868 1869 1872 1873 1876 1877 1885 1878 1879 1880, 1881, 1882, 1883, 1884 1886 1887 1888 1900 1904 1906 1926 Second conducting part first Conducting portion protection region control gate/word line portion second conducting portion first conducting portion second conducting portion first conducting portion second conducting portion first conducting portion second conducting portion first conducting portion substrate insulating layer inversion layer source Pole/drain region selection gate structure shunt area contact storage element array source line bit line no-pole terminal 125538.doc -70- 200832403

1928 Source Terminal 1950 NAND String 2096 Memory Device 2098 Memory Chip 1900 Storage Element Array (Memory Array) 2010 Control Circuit 2012 State Machine 2014 On-Chip Address Decoder 2016 Power Control Module 2018 Line 2020 Garbage Bus ( Line) 2030, 2030A, 2030B Column Decoder 2050 Controller 2060, 2060A, 2060B Line Decoder 2065, 2065A, 2065B Read/Write Circuit 2070 Sensing Circuit 2072 Data Bus 2080 Sensing Module 2082 Bit Line Lock Memory 2090 Common Section 2092 Processor 3093 Input Line 2094 Data Latch (Data Latch Stack) 125538.doc -71 - 200832403

2096 2000 2300 2310 2500 2520 2510 2650 3 000 3010, 3020, 3030, 3040, 3050,... 3012, 3022, 3032, 3042, 3052,... A, B, CB* E BLO, BL1,...BL8511 F PC I/O Interface sensing block parity structure

The threshold voltage level of the all-bit line (ABL) architecture storage element is increased to state A. The threshold voltage is increased to the state C range. The threshold voltage is increased to the threshold voltage distribution in the state B range. Program pulse verification pulse threshold voltage distribution (stylized state)

Transition state B First threshold voltage distribution (erased state) Bit line width stylized counter 125538.doc 72- 200832403 PCmax Stylized limit value SGD drain select line (drain selection gate) SGS select line (source Pole selection line) (source selection gate) VBL bit line voltage VCES Coupling electrode voltage VCGR Read control gate voltage VNAND NAND string channel voltage VPASS pass voltage (read transfer voltage) VPGM program voltage VREAD read voltage VSGS (source side) selects the gate voltage VSWL. The voltage on the selected word line VUWL is applied to the voltage of the unselected word line Vra, Vrb, Vrc read the reference voltage Vva, Vvb, Vvc verify the reference voltage Vvb, verify point WL3, WL2, WLl, WL0 word line 125538.doc 73-

Claims (1)

200832403 X. Patent Application Range: 1. A selective gate structure for a non-volatile storage system, comprising: 'a first conducting portion carried by a substrate; a second conducting portion, Forming on the first 'component of the first conductive portion and electrically coupled to the first component of the first conductive portion;" an electric P knife formed on one of the first conductive portions and the second member. And a third conductive portion formed on the dielectric portion, the third conductive portion being electrically isolated from the first conductive portion by the dielectric portion and spaced apart from the second conductive portion. The selective gate structure of claim 1, wherein: the first conductive portion and the second conductive portion provide a select gate; and the third conductive portion provides a coupling electrode. 3. The gate of claim 2 a pole structure, wherein: the selected gate and the coupled electrode system are independently driven. Φ 4. The selective gate structure of claim 1, wherein the second conductive portion and the third conductive portion extend in a word line direction 0 *5. The selective gate structure of claim 1, wherein: the third conductive portion is spaced apart from the one-dimensional line by the second conductive portion. 6. The selective gate structure of claim 1 · The first conductive portion extends successively to the substrate in a direction of a bit line 125538.doc 200832403 Between the first and second source/drain regions. The gate structure of claim 1, wherein the first conductive portion is formed by the first polysilicon layer and the second conductive portion is formed by the first conductive portion The layer is formed. 8. The selective gate structure of claim 1, wherein: the first conductive portion is formed on an insulating layer on the substrate. 9. A method for operating a non-volatile storage device, comprising: a component =?: a group of non-volatile storage elements, the non-volatile storage elements being associated with a -selective (four) pole structure, the selection The interpole structure includes a selection gate and a coupling electrode. The one of the selective closed electrodes extends between the coupling electrode and a substrate; and, during the stylization, independently driving the first and second voltages The gate is selected and the coupling electrode is selected. 1 0. The method of claim 9, wherein: The second voltage is higher than the method of claim 9, wherein: the pressure level provides the second voltage for reducing one of the substrates adjacent to the selection gate The gate in the source/drain region induces a drain leakage 0 12. The method of claim 9, wherein the second voltage is set according to a voltage that a dielectric material can withstand; Provided between the coupling electrode and the portion of the select gate extending between the coupling electrode and the substrate. The method of claim 9, wherein a plurality of sub-lines are associated with the plurality of non-volatile storage elements; and the method further comprises: when passing through at least one of the plurality of word lines a program voltage is applied to the plurality of non-volatile memory components until the second voltage is applied to the bonding electrode, and the second voltage is provided in the plurality of word lines according to the plurality of bits . 14. The method of claim 13, wherein: the at least one of the plurality of sub-lines is adjacent to the selected gate = day, a voltage applied to the coupling electrode is higher than when the plurality of word lines The at least one is non-adjacent to a voltage applied to the coupled a-electrode when the open-ended structure is selected. 15. The method of claim 9, wherein: - the first electrical product and the second voltage system are at least one of the following: (4) ramping up simultaneously with the knife ground; and (8) at least partially simultaneously ramping down. 16. The method of claim 9, wherein the second voltage is provided in one bit depending on the temperature. 17. The method of claim 9, wherein the pressure is based on the number of cycles of the memory device, and the second power is provided as a bit. The method of claim 9 wherein: And/or a program pulsed electric dust k for the second voltage. 19. The method of claim 9, wherein: 125538.doc 200832403 When a multi-process programming technique is used, the second voltage is only available in accordance with the number of stylized processes. 20. The method of claim 9, wherein: the non-volatile storage element is provided in at least one of the financial records. 21. The method of claim 2, wherein: the selective closed-pole configuration is provided at the source side of the NAND string. ,,mouth 125538.doc