200834684 九、發明說明： 【發明所屬之技術領域】 且尤係關於連 碱（electrically 本發明大致上係關於積體電路之製作 接積體電路中之電路元件的導電特 conductive feature)之形成。 【先前技術】 積體電路包括許多個別的電路元件 女哭》+ μ - _ , W如電晶體、電 合时及电阻盗。廷些元件係藉由導電特徵而 以形成複雜的電路，例如記憶體裝置、 @ 益精由增加母電路功能元件之數目以增加該電路之 性及/或藉由增加該等電路元件 、 b ^效H徵尺寸（feat⑽size)之減小讓大量的電路元 件付以形成於相同的面積上，因此，可增加電路之功能性， 並且也可減少訊號傳遞延遲，故可能增加電路元件 速度。 ⑩隨著積體f路的特徵尺寸之減小，積體電路之電路元 件需要更複雜的技術方能電性連接在一起。如果大量的電 /路元件係形成在相同的面積上，為了要能夠容納該導電特 被’該導電特徵之尺寸必須予以減小。此外，導電特徵也 可形成在彼此相互堆疊之複數個層中。 在見代積體包路中，車交高的互連層⑻的打加⑽⑽η⑽ level)中之導電特徵通常係由銅所製成。然而，如果銅擴散 至其中形成有電路元件之石夕基底内，且併入（inc〇rp 至該石夕基底之結晶格（crystal咖⑻内，則會產生深的雜質 94147 200834684 ， % * v ；層（deeP imPUrity kVel)。這種深的雜質層會導致電路元件 ··(例如場效電晶體）之效能的降低。為了避免這種問題，電 •路元件與第一層導電線之間的電性連接通常由鎢所製成。 一種依據目前技術形成半導體結構之方法將參閱第 la至lb圖而加以描述。第la圖顯示半導體結構ι〇〇於依 據目前技術之製造方法之第一階段中的示意剖面圖。 半導體結構100包括基底101，基底1〇1(可例如包括 鲁矽）包括場效電晶體102。場效電晶體102包括主動區103、 ，極區108和汲極區109。在依據目前技術之製造方法的 範例中（其中，場效電晶體1〇2為N型電晶體），基底ι〇ι 之材料可為P型摻雜的（P-doped)，而源極區1〇8和汲極區 109則可為N型摻雜的（N-doped)。相反地，在依據目前技 術之製造方法的範例中（其中，場效電晶體1〇2為p型電晶 體），主動區103可為N型摻雜的，而源極區1〇8與汲極·· 區109則可為P型摻雜的。因此，源極區1〇8與主動區ι〇3 籲之間的介面（interface)處和汲極區ι〇9與主動區1〇3之間的 介面處有PN過渡（PN transition)。 ~效龟日日體1〇2使包括閘電極（gate electrode) 105，閘 ，極105之侧面被側壁間隔件結構1〇7所包圍，並藉由閑 極絕緣層（gate insulation layer)106而與主動區1〇3分隔。 溝槽Ik離結構（trench isolation structure) 104將場效電晶體 102與半導體結構1〇〇中之其他電路元件予以電性絕緣。 場效電晶體102可藉由該領域中熟習技術者所已知的方法 力、以^/成，包含離子饰植（i〇n imp〗antati〇n)、沉積 6 94147 200834684 -(deposition)、光微影術（photolithography)、韻刻（etching)、 鴿 氣化（oxidation)及退火（annealing)等先進技術。 ， 介電材料層11〇係沉積於基底101之上，層110可包 括二氧化矽、氮化矽及/或氧氮化矽，並可藉由已知的沉積 技術（例如化學氣相沉積（chemical vapor deposition, CVD) 及電漿加強化學氣相沉積（plasma enhanced chemical vapor deposition，PECVD))來予以形成。層110之厚度可大於閘 ❿電極1〇5之高度。在沉積層11〇後，可實施已知的平坦化 製程（例如化學機械研磨（chemicai mechanical p〇lishing， CMP)) ’以獲得層11 〇之平坦表面。 接觸通孔（contact via)lll、112、113係形成於層110 中，為了這個目的，遮罩（masky(未顯示）係藉由已知的光 微影術方法而形成於半導體結構1〇〇之上，該遮罩將除了 接觸通孔111、112、1B待形成之部分以外之其餘部分的 層110予以覆盘。之後，實施已知的各向異性餘刻製程 _ (anisotropic etching Pr〇cess)(例如乾式蝕刻製程），以將未 被該遮罩所覆蓋之層110予以移除。該蝕刻製程之各向異 性有助於獲得接觸通孔ln、112、113的實質上係垂直: 侧壁。 接觸通孔111係形成在源極區1〇8之上方，因此，在 接觸通孔111之底部，源極區108的一部分係暴露的。接 觸通孔112、113分別形成在閘電極1〇5和汲極區1〇9之上 方，敌閘電極105係暴露在接觸通孔112之底部，而汲極 區109係暴露在接觸通孔丨丨3之底部。 94147 7 200834684 在依據目前技術之製造方法的一些範例中，㈣停止 層（etchmg stop layer)(未顯示）可設置在場效電晶體⑽及 層110之間，其中，錢刻停止層所包括的材料之餘刻率 (etchrate)係遠低於層110之介電材料的蝕刻率。因此，該 钱刻製程可在通孔m、112、113 —貫穿層11()之介· 料時，便立即可靠地停止。在形成接觸通孔⑴、⑴、⑴ 後’可實施第二_製程’以將該㈣停止層暴露在接觸 通孔m、m、m之底部的部分予以移除。在形成接觸 通孔m、m、⑴後，可藉由例如已知的光阻剝除法如如 strip method)來將該遮罩予以移除。 接下來，接觸通孔m、112、113係以鎢來予以填充， 為了這個目的’第-膠層（glue la㈣114及第二膠層ιΐ5 係沉積於半導體結構100之上。膠層114、115可改盖讯置 於接觸通孔m、. m、113中之鎮與層11〇之介電二之 間的黏著性。此外，如果該鶴係藉由化學氣相沉積（cvd) _製程及/或電漿加強化學氣相沉積（PECVE)製程來予以沉 積’則膠層114、115可有助於獲得具有較佳結晶結構的鶴。 第-謬層114可包括鈦，並可藉由離子化金屬電裝沉 積製程來予以形成。如該領域中熟習技術者所已知的，離 子化金屬電漿沉積係另一種物理氣相沉積，其中，金屬原 子（metal atom)係在電漿中被離子化，該金屬原子可例如藉 由濺鍍（sputtering)包括將被沉積之該金屬的靶材（targJ) 來予以產生。該電漿可藉由载體氣體（carrier胖5)中之電氣 輝光放電（electric glow discharge)來予以產生，該載體氣體 94147 200834684 :::包括虱軋及/或鈍氣(n〇ble gas)。該電氣輝光放電可 猎由個別地將射頻交流電流耦合至該載體氣體及/或藉由 將該射頻交流雷厭i 9 、 又/爪包壓施加至設置於該載體氣體内之電極來予 、產生該離子化的金屬原子接著藉由偏壓而朝基底10 加速，該偏壓係施加在基底1G1肖設置有反應器容器 (職二vessel)之電極之間，該離子化金屬電聚沉積係在該 反應器容器内實施。第二膠層115可包括氮化鈦，並可藉 由為該領域中熟習技術者所已知的化學氣相沉積及/或電 漿加強化學氣相沉積來予以形成。 包括鎢之晶種層（seed layer)116係形成在半導體結構 1〇0之上方，晶種層U6可藉由原子層沉積（atomie layer deposition，ALD)製程來予以形成。如該領域中熟習技術者 所已知，原子層沉積係另一種化學氣相沉積，其中，該半 導體結構係相繼地暴露於複數個氣態先質化合物（gaseous pi^urso!： compound)，該等氣態先質化合物係相繼地流至 ⑩半導體結構100設置於其中的反應器容器。當第一先質流 至半導體結構100時，第一先質之實質上單原子層 (mono-atomic layer)係形成在第二膠層115之上方。由於該 第一先質之分子之間的黏著性可能不強，因此，藉由調適 該原子層沉積製程之溫度，可實質上避免沉積超過一層之 第一先質之單原子層。之後，第二先質係流至半導體結構 100，該第二先質與出現在半導體結構i 〇〇之表面上的第一 先質起化學反應。在該化學反應中，可產生鎢。 在晶種層116形成後，包括鎢之層117可形成在晶種 9 94147 200834684 層116之上方，為了這個目的，可採用廣為人知的沉積技 術’例如化學氣相沉積及/或電漿加強化學氣相沉積。在層 Π7之形成過程中，接觸通孔111、112、113之邊緣附近 之所進行的材料沉積可較接觸通孔m、U2、n3之底部 附L所進行的材料沉積為快。如此一來，便可在接觸通孔 111 112、113 之内侧形成接缝（seam)n8、119、120。 接下來’可實施化學機械研磨（CMP)製程，該化學機 械研磨製私係用來將膠層〗14、i丨5、晶種層116及包括鎢 之層117中沉積於接觸通孔U1、112、113之外的部分予 以移除。 第lb圖顯示半導體結構1〇〇於依據目前技術之製造 方法的較後階段中之示意剖面圖。第二層121介電材料係 形成在第-層110介電材料的上方。在依據目前技術之製 造方法的一些範例中，第二層121可包括.與第一介電層110 相同的材料。或者，第二層121可包括與第一介電層110 不同的材料，例如像是氫基倍半矽氧烷（hydrogen silsesquioxane)之低 k(low-k)材料。 在第二層121介電材料中，係形成有溝槽122、、 124’此可藉由該領域中熟習技術者所已知的光微影及钱刻 技術來予以完成。a 障壁層（barrier layer)125係形成在半導體結構ι〇〇之 上方’ 壁層125可包括叙及/或氮化趣，並可用來防止將 設置於溝槽122、123、124中之銅擴散至半導體結構1〇〇 之其他部分。 94147 10 200834684 ； 接下來，包括銅之晶種層127係形成在半導體結構100 、.之上，此可藉由例如化學氣相沉積或電漿加強化學氣相沉 積之已知方法來予以完成。之後，包括銅之層126係藉由 例如該領域中熟習技術者所已知的電鍍製程形成在晶^層 127之上。最後，晶種層127及層126位於溝槽122、123、 124之外的部分係藉由例如化學機械研磨製程來予以移 除。 依據目前技術之上述製造方法的問題為用來填充接 觸通孔111、112、113之鎢具有相當高的電阻率，因此， 隨著接觸通孔111、112、113之尺寸（特別是接觸通孔m、 112、113之直徑）之減小，流經接觸通孔m、112、m 之電流會受到高電阻的影響，該高電阻可導致訊號傳遞延 遲的增加，也會產生不想要的熱。由鎢所填充之接觸通孔 lli、112、113之電阻會由於接缝〃118、119、12〇之出現 而進一步增加。此外，膠層114、115可具有比鎢更高的電 春阻，因此，膠層114、115可進一步增加接觸通孔ln、112、 113之電阻。 依據目前技術之上述製造方法之另一個問題為一個 或更多個接縫118、119、120會於該化學機械研磨製程期 間打開（opened)，該化學機械研磨製程係用來將膠層U4、 115、晶種層ι16及層U7位於接觸通孔⑴、112、”3之 外的部分予以移除，此可導致以鎢所填充之接觸通孔 111 U2、113 之導電率（eiectricai e〇ncjuctivity)明顯的減 小’或甚至導致半導體結構1 〇〇的故障。 11 94147 200834684 ; 纟發明係關於可避t、或至少減小-個或更多個上述 \ 問題之效應的各種方法及裝置。 k 【發明内容】 以下提出本發明之簡化概要，以提供本發明之一些態 樣的基本了解。此概要並不是本發明詳盡的概觀，其並不 是用來確認本發明之關鍵或重要元件或描繪本發明之範 疇’其唯一的目的係以簡化形式提出一些概念，以作為稍 後討論之更詳細敘述的序言。 依據此處所揭露之一個例示實施例，一種形成 =構之方法包括提供半導縣底，該半導體基底包括一層 電材料，凹部（reeess)設置於該層介電材料中。該凹部以 包括銀之材料予以填充。 依據此處所揭露之另一個例示實施例，一種半導體結 ^冓包括半導體基底，該半導體基底包括—層介電材料，凹 部設置在該層介電材料中，該凹部以包括銀之材料予以埴 •充。 【實施方式】 本發明之不同例不實施例係揭露於下文中。為了清楚 的η a貝作之彳寸破並非全揭露於此說明書中，應領會 =，在任何這種真正實施例之發展中，必須作出各種特 =作之決^ ’以達成發展者之特戈目標，例如與系統相 纖制相谷’該限制會隨著實作之不同而改 ^此外，將領會的是，這種發展努力可能是複雜且耗時 、仁。卩仍然是該領域中具有此揭露利益之通常技術者所 12 94147 200834684 需從事的例行工作。 本發明之標的將參閱所附加的例圖來予以描述。不同 的結構、系統及裝置係示意地繪示於圖式中，其目的僅在 於解釋，以便不會以該領域中熟習技術者已知的細節來模 糊本發明。然而，該附加的圖式係包含以描述及解釋本發 明之例示範例。此處所使用之字與詞應被了解及解讀成^ 有與相關領域中之熟習技術者對於該些字與詞所為之解釋 相-致的意義。術語或詞之特収義（也就是，不同於該 ^熟習技術者所了解之通常及習慣意義)不會被此處： 子或詞的-致用法所暗示。到一個程度，如果術語或詞想 要具^特別意義，也就是除了熟習技藝者所了解的意義以 外的意義，則這種特別惫義將合 ^ 往盘词护，兰=我將會以直接且無疑義提供該術 #寸別疋我之疋我方式明確地提出於說明書中。 (該一Λ實施例中，形成於一層介電材料 層電材科係投置在半導體基底之上）_之凹部係以勺 :銀之材料來予以填充，該凹部可包括形： 設置在該半導體基底中，例如場效心 捉供對該電路％件之電性連接。 使用ft::該材料可包括實質上純的銀’其優點在於， =上純的銀可有助於提供該材料非常低 二其=施例令’包括銀之該材料可包括丄 銀）’例如銀與其他貴金屬（G至戰）之 二括 如為铑、銥、鉑、# $入 " 以貝金屬例 釕及金。也可使用包括其他金屬(例如铜、 94147 13 200834684 .鋁、鉻及钽）之合金。在另外的實施例中，也可使用包括叙、 :刪、磷、石夕、碳及硫之合金，其優點在於，叙、侧、碟、 .矽、碳及硫可提供粒界定位（grain boundary fix)。 再者，在一些實施例中，一層包括铑之材料可設置在 包括銀之材料之下及/或之上。包括姥之該層材料可機械性 地及/或化學性地保護包括銀之該材料。 其優點在於，包括銀之該材料可具有高的導電率，銀 之導電率係高於鶴之導電率，並且甚至高於銅之導電率，、 銅常用於較高之互連層的電性連接。因此，形成於半導體 基底中之電路元件的電性連接的電阻可減小，其可伴隨訊 號傳遞延遲之減小及產生於該半導體結構中之熱的減小°。 、此外，相較於鎢，包括銀之該材料可表現較軟的運作 行為（be—)，甚至可表現比銅更軟的運作行為，因此， 可減小該半導體結構.中於退火製程期間所產生的機械應 力，並能改善包括銀之該材料的結晶化。 一 籲 #者’包括銀之該材料可與出現在該電路元件中位於 該凹部之下的石夕開始化學反應。在該化學反應中，可形成 包括介於銀及石夕之間的化學化合物之石夕化物，此可有助於 咸i c括銀之該材料與該電路元件之間的接觸電阻率 (contact resistivity) 〇 一第2a圖喊不半導體結構2⑽於依據此處所揭露之 示實施例之形成半導體結構之方法的第—階段中之示音 半導體結構200包括基底別，基底洲包料 效电晶體202形式之電路元件。基底2()1可包括半導體 14 94147 200834684 ；料，例如矽。場效電晶體202包括形成於基底2〇1中之主 •動區203。閘電極205係形成於主動區2〇3之上方，並 .由閘極絕緣層206而與主動區2〇3分隔。在一些實 : 閘電極2 0 5可包括多曰访,, .. 曰曰夕（polycrystallme silicon)，而閘極 絕緣層206可包括二氧化石夕，氮化石夕及/或氧氮化石夕。閑電 極205之側面被側壁間隔件結構2〇7所包圍。鄰接閑電極 2〇5處，形成有源極區2()8和没極區謝。溝槽隔離結構 204將場效電晶體2G2與形成於基底則巾之其他電路 胃件予以電性隔離。 %效電晶體202及溝槽隔離結構綱可藉由該領域中 熟習技術者所已知的方法加以形成，包含光微影術、餘刻、 沉積、離子佈植及退火（annealing)等方法。 包括介電材料（例如二氧化矽或氮化矽）之層 -形成在基底201之上。為了 f侗 ，Λ 习习… 马了 W個目的，係採用該領域中熟 習技術者所已知的沉積技術’例如化學氣相沉積及/或電聚 #加強化學，相沉積。介電材料之層21()的厚度可大於間電 ° 之同度在开> 成介電材枓之層210後，可實施平坦 化製程(例如化學機械研磨製程），以減少介電材料之層川 的表面之粗糙度（roughness)。 曰 、u接觸通孔211、212、213之形式而設置之凹部係形 成於介電材料之層210中。接觸通孔211係形成在源極區 208之上方’接觸通孔212係形成在閘電極之上方， 而接觸通孔213係形成在汲極區謝之上方。因此，源極 區2〇8之一部分係暴露在接觸通孔211之底部，閘電極2〇5 94147 15 200834684 之一部分係暴露在接觸通孔212之底部，而汲極區2〇9之 一部分係暴露在接觸通孔213之底部。類似於參閱第la 至lb圖之依據前述目前技術之製造半導體結構的方法，接 觸通孔211、212、213可藉由形成遮罩（未圖示）之方式來 予以形成，該遮罩具有在接觸通孔211、212、213將被形 成之位置處的開口，且將半導體結構2〇〇暴露於蝕刻劑 (etchant)，該蝕刻劑係用來移除層21〇之材料。 包括铑之材料的層214形成在半導體結構2〇〇之上。 1包括铑之材料的層214可覆蓋接觸通孔211、212、213之 底表面及側壁，也可覆蓋層21〇之表面位於接觸通孔21卜 212、213之外侧的部分，例如層21〇之表面位於接觸通孔 211、212、213之間的部分。在接觸通孔211、2i2、 之底表面處，層214可分別位於源極區2〇8、閘電極2〇5 和〉及極區209上。- 在些貝轭例中，包括錄之材料的層214可藉由濺鍍 製程予以形成。在該雜製程中，包括叙_係以離子 來予以，、、、射例如為氬之鈍氣（n〇ble gas)離子。由於該離 子的撞擊（impact)’鍺原子會被撞離出該靶材。半導體結構 200係設置於相對於妹材，這樣，至少一部分被撞離出 該革巴材之姥原子會衝射（impinge)半導體結構2〇〇,以形成 層 214 〇 在其他實施例中，包括铑之材料的層214可藉由原子 層沉積製程來予以形成。在該原子層沉積製程中，半導體 結構細純置在反應器容器中，氣態先質可供應至該反 94147 16 200834684 .應谷之後包括姥(例如乙醯丙酮錢（III)(rhodium(m) • ac邮awte))之第一先質係供應至該反應器容器，因 此帛先貝之戶、質上單原子層係形成在半導體結構細 之上。該沉積製程之參數（例如半導體結構綱之溫度及/ 或該第一先質之流動）孫早 係予以调適，這樣，該第一先質之實 質上單原子層便仍在半導體結構之表面上，但該第一 先二之另C的为子亚不會實質上穩定地連結至該第一先質 • 上單原子層。在一個實施例中，該原子層沉積製程 产1〇0至電範圍内之溫度予以實施’在此溫 度乾圍内實施該原子声沉择制 效電晶體202中之石/部八貝助於避免損壞設置在場 7J如該領域中熟習技術者所孰 ㈣石夕部分可例如設置在源極H 208和汲極區·:、 第"〇 >氧之第—先質係供應至該反應H容器，該 Γ=:來與該第一先質起化學反應。在該化學反應 "結構:00之揮發性反應生成物。於該錄仍在半導 物可藉由直揮發性反應生成 器。 一二式泵（VaCUUm PumP)而被抽離出該反應器容 已、衾：後二重覆交替供應該第-及第二先質，直到層214 4預定的厚度。由於層2 係實質上受到該第_先質於二之循速=〇wth me) (也就是，實(cy )所沉積之量 的層214之Λ / 限制，因此，包括姥之材料 形成之邻八=可貫質上與半導體結構200之表面於其所 Ρ刀的傾向無關。特別是，包括錄之材料的層214 94147 17 200834684 •在接觸通孔211、212、213之底表面和侧壁上之厚度可實 ._質上等於層214在半導體結構200之於接觸通孔2ΐι、 • 212 213之外的貫質上水平部分（例如介電材料之層214 於接觸通孔211、212、213與接觸通孔211、212、213之 底表面之間的部分之上）的厚度。在另外的實施例中，可使 用其他方法來形成具有铑之材料的層214。舉例來說，層 214可藉由化學氣相沉積製程及/或電漿加強化學氣相沉積 鲁製程來予以形成。包括铑之材料的層214之厚度在從大約 5至30奈米（nm)之範圍内，特別是在從$至奈米之範 圍内。 在形成包括錢之材料的層214後，包括銀之晶種層215 係形成在半導體結構200之上方。在一些實施例中，晶種 層215可藉由化學氣相沉積製程來予以形成，在該化學氣 相沉積製程中，反應物（reactant)(例如包括銀之金屬有機化 合物（metal organic compound)，例如（1，1，1，5,5,5-六氟-2,4_ 籲乙醯丙酮基）-銀[雙（三曱基矽烷基）乙炔]((HH5，5-200834684 IX. Description of the invention: [Technical field to which the invention pertains] and in particular to the formation of a base (electrically, the present invention is generally related to the conductive characteristic of a circuit element in a fabricated circuit of an integrated circuit). [Prior Art] The integrated circuit includes many individual circuit components. Female crying + μ - _ , W such as transistor, electrical and resistance thief. These elements are formed by a conductive feature to form a complex circuit, such as a memory device, by increasing the number of female circuit functional elements to increase the circuit's properties and/or by adding such circuit components, b ^ The reduction in the size of the F (10) size allows a large number of circuit components to be formed on the same area. Therefore, the functionality of the circuit can be increased, and the signal transfer delay can be reduced, so that the circuit component speed can be increased. 10 As the feature size of the integrated circuit f decreases, the circuit components of the integrated circuit require more complicated techniques to be electrically connected together. If a large number of electrical/road components are formed on the same area, the size of the conductive features must be reduced in order to be able to accommodate the conductive features. Further, conductive features may also be formed in a plurality of layers stacked on each other. In the case of the inclusion package, the conductive features in the (10) (10) η (10) level of the interconnect layer (8) of the vehicle intersection are usually made of copper. However, if the copper diffuses into the base of the slab in which the circuit component is formed, and is incorporated (inc rp into the crystal lattice of the slate base (crystal coffee (8), deep impurities 94147 200834684 , % * v Layer (deeP imPUrity kVel). This deep impurity layer can cause a decrease in the performance of circuit components (such as field effect transistors). To avoid this problem, between the circuit components and the first conductive line The electrical connection is typically made of tungsten. A method of forming a semiconductor structure in accordance with the prior art will be described with reference to Figures 1a through 1b. The first diagram shows the semiconductor structure as the first method of fabrication according to the prior art. Schematic cross-sectional view of the stage. The semiconductor structure 100 includes a substrate 101, and the substrate 101 (which may include, for example, a reed) includes a field effect transistor 102. The field effect transistor 102 includes an active region 103, a polar region 108, and a drain region. 109. In an example of a manufacturing method according to the prior art (wherein the field effect transistor 1〇2 is an N-type transistor), the material of the substrate ι〇ι may be P-doped, and the source Polar zone 1〇8 and bungee 109 may be N-doped. Conversely, in the example according to the manufacturing method of the prior art (wherein the field effect transistor 1〇2 is a p-type transistor), the active region 103 may be N-doped, while the source region 1〇8 and the drain region·· region 109 can be P-doped. Therefore, the interface between the source region 1〇8 and the active region ι〇3 (interface There is a PN transition at the interface between the 〇9 and the active region 1〇3. The effect of the turtle is 1 〇2, including the gate electrode 105, gate, pole The side of the 105 is surrounded by the sidewall spacer structure 1〇7 and is separated from the active region 1〇3 by a gate insulation layer 106. The trench isolation structure 104 will be effective. The transistor 102 is electrically insulated from other circuit components in the semiconductor structure 1 . The field effect transistor 102 can be ionically implanted by means of methods known to those skilled in the art. I〇n imp〗 antati〇n), deposition 6 94147 200834684 - (deposition), photolithography (photolithography), rhyme (etching) An advanced technique such as oxidation and annealing, a dielectric material layer 11 is deposited on the substrate 101, and the layer 110 may include hafnium oxide, tantalum nitride, and/or hafnium oxynitride. It can be formed by known deposition techniques such as chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD). The thickness of layer 110 can be greater than the height of gate electrode 1〇5. After the deposition of the layer 11, a known planarization process (e.g., chemicai mechanical polishing (CMP)) can be performed to obtain a flat surface of the layer 11 . Contact vias 111, 112, 113 are formed in layer 110. For this purpose, a masky (not shown) is formed in the semiconductor structure by known photolithography methods. Above, the mask covers the remaining layer 110 except for the portion to be formed in contact with the through holes 111, 112, 1B. Thereafter, a known anisotropic etching process is performed _ (anisotropic etching Pr〇cess (eg, a dry etch process) to remove the layer 110 that is not covered by the mask. The anisotropy of the etch process helps to obtain a substantially vertical of the contact vias ln, 112, 113: side The contact via 111 is formed above the source region 1〇8, and therefore, a portion of the source region 108 is exposed at the bottom of the contact via 111. Contact vias 112, 113 are respectively formed at the gate electrode 1 Above the 〇5 and the drain regions 1〇9, the enemy gate electrode 105 is exposed at the bottom of the contact via 112, and the drain region 109 is exposed at the bottom of the contact via 3. The 94147 7 200834684 In some examples of the manufacturing method, (4) the stop layer (etchm A g stop layer) (not shown) may be disposed between the field effect transistor (10) and the layer 110, wherein the etchrate of the material included in the stop layer is much lower than the dielectric material of the layer 110. Etching rate. Therefore, the process can be reliably stopped immediately when the vias m, 112, and 113 pass through the layer 11 (), and can be implemented after the contact vias (1), (1), (1) are formed. The second process ′ is removed by exposing the (four) stop layer to the bottom of the contact vias m, m, m. After forming the contact vias m, m, (1), for example, by known photoresist A stripping method such as a strip method removes the mask. Next, the contact vias m, 112, 113 are filled with tungsten. For this purpose, a glue layer (glue la (114) 114 and a second glue layer ι 5 are deposited on the semiconductor structure 100. The glue layers 114, 115 may be The adhesive is placed between the town in contact with the through holes m, m, 113 and the dielectric of the layer 11 。. In addition, if the crane is chemical vapor deposition (cvd) _ process and / Or a plasma enhanced chemical vapor deposition (PECVE) process for deposition', the glue layers 114, 115 can help to obtain a crane with a better crystalline structure. The first layer 112 can include titanium and can be ionized A metal electrical deposition process is formed. As is known to those skilled in the art, ionized metal plasma deposition is another physical vapor deposition in which a metal atom is ionized in a plasma. The metal atom can be generated, for example, by sputtering a target (targJ) comprising the metal to be deposited. The plasma can be discharged by an electrical glow in a carrier gas (carrier fat 5). (electric glow discharge) to generate, the carrier gas 94147 200834684::: including rolling and/or n〇ble gas. The electrical glow discharge can be individually coupled to the carrier gas and/or by the radio frequency exchange. 9. The /claw is applied to the electrode disposed in the carrier gas to generate the ionized metal atom, and then accelerated toward the substrate 10 by biasing, and the bias is applied to the substrate 1G1. Between the electrodes of the vessel (the vessel), the ionized metal electropolymer deposition is carried out in the reactor vessel. The second subbing layer 115 may comprise titanium nitride and may be used by those skilled in the art. The known chemical vapor deposition and/or plasma enhanced chemical vapor deposition is formed. A seed layer 116 including tungsten is formed over the semiconductor structure 1 〇 0, and the seed layer U6 can be borrowed. It is formed by an atomic layer deposition (ALD) process. As is known to those skilled in the art, atomic layer deposition is another chemical vapor deposition in which the semiconductor structure is successively exposed to a plurality of Gaseous precursorization (gaseous pi^urso!: compound), the gaseous precursor compounds are successively flown to the reactor vessel in which the semiconductor structure 100 is disposed. When the first precursor flows to the semiconductor structure 100, the first precursor The substantially mono-atomic layer is formed above the second adhesive layer 115. Since the adhesion between the molecules of the first precursor may not be strong, the atomic layer deposition process is adapted. The temperature can substantially avoid depositing more than one layer of the first precursor of the monoatomic layer. Thereafter, the second precursor is passed to the semiconductor structure 100, which chemically reacts with the first precursor present on the surface of the semiconductor structure i 。 . In this chemical reaction, tungsten can be produced. After the seed layer 116 is formed, a layer 117 comprising tungsten can be formed over the seed layer 9 94147 200834684 layer 116. For this purpose, well-known deposition techniques such as chemical vapor deposition and/or plasma strengthening of the chemical gas can be employed. Phase deposition. During the formation of the layer Π 7, the material deposition in the vicinity of the edges of the contact vias 111, 112, 113 can be deposited faster than the material deposited at the bottom of the vias m, U2, n3. In this way, seams n8, 119, 120 can be formed inside the contact through holes 111 112, 113. Next, a chemical mechanical polishing (CMP) process can be implemented, which is used to deposit the adhesive layer 14, i丨5, the seed layer 116 and the layer 117 including tungsten in the contact via U1. Parts other than 112, 113 are removed. Figure lb shows a schematic cross-sectional view of the semiconductor structure 1 in a later stage of the fabrication method according to the prior art. A second layer 121 of dielectric material is formed over the first layer 110 of dielectric material. In some examples in accordance with the fabrication methods of the prior art, the second layer 121 can comprise the same material as the first dielectric layer 110. Alternatively, the second layer 121 may comprise a different material than the first dielectric layer 110, such as a low k (low-k) material such as a hydrogen silsesquioxane. In the second layer 121 dielectric material, trenches 122, 124' are formed which can be accomplished by photolithography and currency etching techniques known to those skilled in the art. a barrier layer 125 is formed over the semiconductor structure ι ' the wall layer 125 may include and/or nitride and may be used to prevent diffusion of copper disposed in the trenches 122, 123, 124 To the other part of the semiconductor structure. 94147 10 200834684; Next, a seed layer 127 comprising copper is formed over the semiconductor structure 100, which can be accomplished by known methods such as chemical vapor deposition or plasma enhanced chemical vapor deposition. Thereafter, a layer 126 comprising copper is formed over the layer 127 by an electroplating process such as is known to those skilled in the art. Finally, portions of the seed layer 127 and layer 126 that are outside of the trenches 122, 123, 124 are removed by, for example, a chemical mechanical polishing process. The problem with the above-described manufacturing method according to the prior art is that the tungsten used to fill the contact vias 111, 112, 113 has a relatively high resistivity, and therefore, with the size of the contact vias 111, 112, 113 (especially the contact vias) The decrease in the diameter of m, 112, and 113), the current flowing through the contact vias m, 112, m is affected by the high resistance, which can cause an increase in signal transfer delay and also generate unwanted heat. The resistance of the contact vias lli, 112, 113 filled with tungsten is further increased by the presence of the seams 118, 119, and 12 〇. In addition, the glue layers 114, 115 may have a higher electrical resistance than tungsten, and thus, the glue layers 114, 115 may further increase the resistance of the contact vias ln, 112, 113. Another problem with the above-described manufacturing method according to the prior art is that one or more seams 118, 119, 120 are opened during the chemical mechanical polishing process, which is used to bond the glue layer U4, 115, the seed layer ι16 and the layer U7 are removed at portions other than the contact vias (1), 112, "3, which may result in conductivity of the contact vias 111 U2, 113 filled with tungsten (eiectricai e〇ncjuctivity A significant reduction or even a failure of the semiconductor structure 1 11 11 94147 200834684 ; 纟 invention relates to various methods and apparatus for avoiding t, or at least reducing the effects of one or more of the above problems. BRIEF DESCRIPTION OF THE DRAWINGS The following presents a simplified summary of the invention in order to provide a basic understanding of the invention. The scope of the present invention is intended to be a <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; For example, a method of forming a structure includes providing a semiconductor substrate comprising a layer of electrical material, and a reeess is disposed in the layer of dielectric material. The recess is filled with a material including silver. In another illustrative embodiment, a semiconductor device includes a semiconductor substrate including a layer of dielectric material, the recess being disposed in the layer of dielectric material, the recess being filled with a material comprising silver. MODES OF CARRYING OUT THE INVENTION The different embodiments of the present invention are disclosed in the following. For the sake of clarity, it is not fully disclosed in this specification, and it should be understood that, in the development of any such real embodiment, It is necessary to make a variety of special decisions. 'To achieve the goal of the developer's Tego, for example, to match the system.' The limit will change with the implementation. In addition, it will be understood that this development effort It may be complex and time consuming, and it is still a routine work that is required by the general practitioners in this field who have the benefit of this disclosure. 94 94147 200834684 The various structures, systems, and devices are schematically illustrated in the drawings, and are merely intended to be illustrative, so as not to obscure the details as known to those skilled in the art. The accompanying drawings, which are included to illustrate and explain the embodiments of the invention, are intended to be understood and interpreted as the same. Explain the meaning of phase-to-phase. The specific meaning of the term or word (that is, the usual and customary meanings that are different from those known to those skilled in the art) will not be implied here: the use of the word or the word To a certain extent, if the term or word wants to have a special meaning, that is, meaning other than the meaning understood by the skilled artisan, then this special derogatory will be combined with the words, Lan = I will Directly and undoubtedly provide the technique #寸别疋我疋我疋 I clearly stated in the manual. (In the embodiment, the dielectric material layer is formed on the semiconductor substrate.) The recess is filled with a spoon: silver material, and the recess may include a shape: disposed on the semiconductor In the substrate, for example, the field effect captures the electrical connection of the % of the circuit. Use ft:: The material can include substantially pure silver', which has the advantage that = pure silver can help provide the material very low. 2 = The order of the material including silver can include silver. For example, silver and other precious metals (G to war) include such as 铑, 铱, platinum, # 入入" Alloys including other metals such as copper, 94147 13 200834684. Aluminium, chromium and niobium may also be used. In other embodiments, alloys including: smectite, phosphorus, stellite, carbon and sulfur may also be used, which have the advantages that the rib, the side, the dish, the 矽, the carbon and the sulphur can provide grain boundary positioning (grain) Boundary fix). Further, in some embodiments, a layer of material comprising tantalum may be disposed under and/or over the material comprising silver. The layer material comprising tantalum can mechanically and/or chemically protect the material including silver. The advantage is that the material including silver can have high conductivity, the conductivity of silver is higher than that of the crane, and even higher than the conductivity of copper, and copper is often used for electrical connection of higher interconnect layers. . Therefore, the electrical connection of the circuit elements formed in the semiconductor substrate can be reduced in electrical resistance, which can be accompanied by a decrease in signal transfer delay and a decrease in heat generated in the semiconductor structure. In addition, compared to tungsten, the material including silver can exhibit softer operating behavior (be-) and even exhibit softer operating behavior than copper, thus reducing the semiconductor structure during the annealing process. The mechanical stress generated and the crystallization of the material including silver can be improved. A material comprising silver may be chemically reacted with a stone that appears below the recess in the circuit component. In the chemical reaction, a lithology compound comprising a chemical compound between silver and shoal can be formed, which can contribute to the contact resistivity between the material of the icy silver and the circuit component. The second embodiment of FIG. 2a illustrates the semiconductor structure 200 in the first stage of the method of forming a semiconductor structure according to the embodiment disclosed herein, including the substrate, the substrate-based dielectric transistor 202 form. Circuit components. Substrate 2() 1 may comprise a semiconductor 14 94147 200834684; a material such as germanium. Field effect transistor 202 includes a main active region 203 formed in substrate 2〇1. The gate electrode 205 is formed above the active region 2〇3 and is separated from the active region 2〇3 by the gate insulating layer 206. In some implementations: the gate electrode 205 may include multiple sputum, .... polycrystallme silicon, and the gate insulating layer 206 may include SiO2, nitrite, and/or oxynitride. The side of the idle electrode 205 is surrounded by the sidewall spacer structure 2〇7. Adjacent to the free electrode 2〇5, the source region 2()8 and the immersion zone are formed. The trench isolation structure 204 electrically isolates the field effect transistor 2G2 from other circuit components formed on the substrate. The % effector 202 and the trench isolation structure can be formed by methods known to those skilled in the art, including photolithography, engraving, deposition, ion implantation, and annealing. A layer comprising a dielectric material such as hafnium oxide or tantalum nitride is formed over the substrate 201. For the purpose of f侗, ... 马 马 马 马 马 马 马 马 马 马 个 个 个 个 个 个 个 个 个 个 个 个 个 个 个 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ The thickness of the layer 21() of the dielectric material may be greater than the isoelectricity. After the layer 210 of the dielectric material is formed, a planarization process (eg, a chemical mechanical polishing process) may be performed to reduce the dielectric material. The roughness of the surface of the layer. The recesses provided in the form of 曰, u contact vias 211, 212, 213 are formed in the layer 210 of dielectric material. Contact vias 211 are formed over source regions 208. Contact vias 212 are formed over the gate electrodes, and contact vias 213 are formed over the drain regions. Therefore, a portion of the source region 2〇8 is exposed at the bottom of the contact via 211, a portion of the gate electrode 2〇5 94147 15 200834684 is exposed at the bottom of the contact via 212, and a portion of the drain region 2〇9 is It is exposed at the bottom of the contact via 213. Similar to the method of fabricating a semiconductor structure according to the prior art described above, the contact vias 211, 212, 213 may be formed by forming a mask (not shown) having the The contact vias 211, 212, 213 are to be opened at the locations where they are formed, and the semiconductor structure 2 is exposed to an etchant which is used to remove the material of the layer 21〇. A layer 214 comprising a material of germanium is formed over the semiconductor structure 2A. A layer 214 comprising a material of tantalum may cover the bottom surface and side walls of the contact vias 211, 212, 213, or a portion of the surface of the cover layer 21 located on the outer side of the contact vias 212, 213, such as layer 21 The surface is located at a portion between the contact vias 211, 212, 213. At the bottom surfaces of the contact vias 211, 2i2, the layers 214 may be located on the source regions 2〇8, the gate electrodes 2〇5 and the > and the pole regions 209, respectively. - In some of the yoke examples, the layer 214 comprising the recorded material can be formed by a sputtering process. In the heterogeneous process, the method includes the use of ions, and emits, for example, argon gas ions of argon. The atom is knocked out of the target due to the impact of the ion. The semiconductor structure 200 is disposed relative to the sister material such that at least a portion of the germanium atoms that are knocked out of the leather material impinge the semiconductor structure 2 to form the layer 214. In other embodiments, Layer 214 of the material of tantalum can be formed by an atomic layer deposition process. In the atomic layer deposition process, the semiconductor structure is finely placed in the reactor vessel, and the gaseous precursor can be supplied to the counter 94147 16 200834684. After the valley, the crucible is included (for example, acetamidine (III) (rhodium(m)) • The first precursor of the ac mail aw))) is supplied to the reactor vessel, so that the first household and the upper monoatomic layer are formed on the fine structure of the semiconductor structure. The parameters of the deposition process (such as the temperature of the semiconductor structure and/or the flow of the first precursor) are adapted so that the substantially monoatomic layer of the first precursor remains on the surface of the semiconductor structure. Above, but the first two of the other C is not substantially stably coupled to the first precursor/upper atomic layer. In one embodiment, the atomic layer deposition process produces a temperature in the range of 1 〇 0 to the electrical range to perform the 'in the temperature dry perimeter, the stone in the atomic acoustic deposition system 202 is used. Avoid damage to the presence of the field 7J as familiar to the skilled person in the field (4) The stone part can be set, for example, at the source H 208 and the bungee area::, "〇> oxygen first - the precursor is supplied to the The H container is reacted, and the Γ =: to chemically react with the first precursor. In the chemical reaction "structure: 00 volatile reaction product. The semiconductor still exists in the semiconductor by the direct volatility reaction generator. A two-stage pump (VaCUUm PumP) is pumped out of the reactor, and the second and second precursors are alternately supplied until the predetermined thickness of the layer 214 4 . Since the layer 2 is substantially subjected to the enthalpy of the first layer of the first phase = 〇wth me) (i.e., the layer 214 of the amount deposited by the solid (cy), the material including the crucible is formed. The neighboring eight = can be qualitatively independent of the tendency of the surface of the semiconductor structure 200 to be slashed. In particular, the layer 214 including the recorded material 94 94 17 17 200834684 • at the bottom surface and side of the contact vias 211, 212, 213 The thickness of the wall may be substantially equal to the upper horizontal portion of the semiconductor structure 200 outside the contact vias 2, 2, 212 213 (e.g., the layer 214 of dielectric material is in contact vias 211, 212). The thickness of 213, above the portion between the bottom surfaces of the contact vias 211, 212, 213. In other embodiments, other methods may be used to form the layer 214 of the material having germanium. For example, the layer 214 can be formed by a chemical vapor deposition process and/or a plasma enhanced chemical vapor deposition process. The thickness of layer 214 comprising germanium material ranges from about 5 to 30 nanometers (nm), in particular Is in the range from $ to nanometer. In the formation of layer 214 including material of money Thereafter, a seed layer 215 comprising silver is formed over the semiconductor structure 200. In some embodiments, the seed layer 215 can be formed by a chemical vapor deposition process in which the reaction is performed. Reactant (for example, a metal organic compound including silver, such as (1,1,1,5,5,5-hexafluoro-2,4_ acetamidine)-silver [double (three) Mercaptoalkyl)acetylene]((HH5,5-
Hexafluoro-2?4-pentanedionato)-silver [bis(trimethylsilyl) acetylene])或揮發性金屬乙脒鹽(v〇latiie metal acetamidinate)，[M(RNC(CH3)NR)x]y)係供應至該反應器容 器中，半導體結構200係設置在該反應器容器中。在半導 體結構200之表面處，該金屬有機化合物與選擇性地供應 至反應器容器之其他反應物進行化學反應，元素的銀 (elementary silver)係形成於該化學反應中。該銀係沉積於 半導體結構200上，以形成晶種層215，但其他反應產物 18 94147 200834684 . 可被抽離出該反應器容器。 • 在其他實施例中，可採用電漿加強化學氣相沉積製程 *來形成晶種層215。如該領域中熟習技術者所已知，電衆 加強化學氣相沉積為另一種化學氣相沉積，其中，輝光放 電係產生於該反應氣體中。為了這個目的，射頻交流電壓 及選擇性的偏壓係施加在半導體結構200及設置在該反應 裔容器中之電極之間。或者，該射頻交流電壓及/或該偏壓 可施加在第一及第二電極之間，其中，該等電極之一者係 鲁設置在半導體結構200之附近。該偏壓可為直流電壓或低 頻交流電壓。在該輝光放電中，化學反應性物種（chemically reactive species)(例如原子、離子及/或基（radical))係從該 反應氣體產生。如此一來，化學反應在該反應氣體中（其 中，係形成有沉積在半導體結構200之表面上元素的銀） ··所發生的溫度可低於在化學氣湘沉積製程中（其中，在該反 應氣體中沒有產生輝光放電）。其優點在於，此可降低半導 馨體結構200於形成晶種層215之期間的熱預算（thermal budget) 〇 在另外的實施例中，晶種層215可藉由無電沉積製程 (electroless deposition process)來予以形成。在該無電沉積 製程中，半導體結構200係插入至包括化合物之溶液中， 該化合物包括銀，例如硝酸銀或硫酸銀。在一些實施例中， 也可使用包括有機硫酸之化合物。此外，該溶液可包括抑 制劑（inhibitor)、平整劑（leveler)及催速劑（accelerator)，類 似於該領域中熟習技術者所已知的於銅鍍覆（copper 19 94147 200834684 • platmg)中所採用者。該溶液可復包括溶劑（s〇iven〇，該溶 •劑可包括水。在其他實施例中，可使用有機溶劑或超臨界 —氧化碳（super-critical carbon dioxide)。在半導體結構 2〇〇 之表面處發生化學反應，元素的銀係產生在該化學反應 中。該元素的銀係沉積在半導體結構2〇〇上，以形成晶種 層215。 曰曰 在形成晶種層215後，一層216包括銀之材料係沉積 癱在半導體結構200之上，層216可包括實質上為純的銀。 在其他實施例中，層216可包括銀合金。 在一些實施例中，包括銀之材料的層216可藉由電鍵 製私來予以形成，在電鍍中，半導體結構2〇〇及電極（該電 和之材料包括銀）係插入至電解液中，該電解 液可包括銀鹽（例如硝酸銀或硫酸銀）之水溶液（叫ue〇US solution)。在一些貫施例中，也可使用有機硫酸鹽。在層 216係包括實質上為純的銀之實施例中，該電極也可包括 ⑩貫質上為純的銀。在層216係包括銀合金之其他實施例 中"亥电極可包括該銀合金。在這種實施例中，該電解液 除了可包括銀鹽外，也可包括含有銀之其他材料成份之鹽。 電壓係施加在半導體結構2〇〇及該電極之間，該電壓 的極性使得（至少平均）半導體結構2〇〇變成陰極（cath〇d)， 而該電極變成陽極（anode)。因此，在半導體結構2〇〇處， 銀離子及選擇性從該電解液來的其他帶正電離子 (positively charged 1〇11)變成固態，並形成包括銀之材料的 層216。在該電極處，銀原子及選擇性的一個或更多個其 20 94147 200834684 並在該電解液中變成溶解狀態 他元素之原子被充電， (solved state)。 在其他實_中，包括銀之材料的層216可藉由化學Hexafluoro-2?4-pentanedionato)-silver [bis(trimethylsilyl) acetylene]) or v〇latiie metal acetamidinate, [M(RNC(CH3)NR)x]y) is supplied to the In the reactor vessel, a semiconductor structure 200 is disposed in the reactor vessel. At the surface of the semiconductor structure 200, the organometallic compound is chemically reacted with other reactants selectively supplied to the reactor vessel, and elementary silver of the element is formed in the chemical reaction. The silver is deposited on the semiconductor structure 200 to form the seed layer 215, but other reaction products 18 94147 200834684 can be pumped out of the reactor vessel. • In other embodiments, the seed layer 215 can be formed using a plasma enhanced chemical vapor deposition process*. As is known to those skilled in the art, electric power enhanced chemical vapor deposition is another chemical vapor deposition in which a glow discharge system is generated. For this purpose, a radio frequency alternating voltage and a selective bias voltage are applied between the semiconductor structure 200 and the electrodes disposed in the reactant container. Alternatively, the RF alternating voltage and/or the bias voltage may be applied between the first and second electrodes, wherein one of the electrodes is disposed adjacent to the semiconductor structure 200. The bias voltage can be a DC voltage or a low frequency AC voltage. In the glow discharge, chemically reactive species (e.g., atoms, ions, and/or radicals) are generated from the reaction gas. In this way, the chemical reaction in the reaction gas (wherein the silver formed on the surface of the semiconductor structure 200 is formed) may occur at a lower temperature than in the chemical gas deposition process (wherein No glow discharge is generated in the reaction gas). This has the advantage that this reduces the thermal budget of the semiconducting eutectic structure 200 during formation of the seed layer 215. In other embodiments, the seed layer 215 can be electrolessly deposited. ) to form. In the electroless deposition process, the semiconductor structure 200 is inserted into a solution comprising a compound including silver, such as silver nitrate or silver sulfate. In some embodiments, compounds including organic sulfuric acid can also be used. In addition, the solution may include inhibitors, levelers, and accelerators, similar to copper plating (copper 19 94147 200834684 • platmg) known to those skilled in the art. Adopted. The solution may include a solvent (s〇iven〇, the solvent may include water. In other embodiments, an organic solvent or super-critical carbon dioxide may be used. In the semiconductor structure 2〇〇 A chemical reaction occurs at the surface where the silver of the element is generated. The silver of the element is deposited on the semiconductor structure 2 to form the seed layer 215. After the seed layer 215 is formed, the layer The material 216 comprising silver is deposited on top of the semiconductor structure 200, and the layer 216 can comprise substantially pure silver. In other embodiments, the layer 216 can comprise a silver alloy. In some embodiments, a material comprising silver The layer 216 can be formed by electrical bonding. In electroplating, the semiconductor structure 2 and the electrode (the electrical material including silver) are inserted into the electrolyte, and the electrolyte can include a silver salt (such as silver nitrate or An aqueous solution of silver sulfate (called ue〇US solution). In some embodiments, an organic sulfate may also be used. In embodiments where layer 216 includes substantially pure silver, the electrode may also include 10 passes. The upper layer is pure silver. In other embodiments in which the layer 216 includes a silver alloy, the "high electrode" may include the silver alloy. In such an embodiment, the electrolyte may include, in addition to the silver salt, a salt of other material components of silver. A voltage is applied between the semiconductor structure 2〇〇 and the electrode, the polarity of the voltage is such that (at least average) the semiconductor structure 2 turns into a cathode (cath〇d), and the electrode becomes an anode Thus, at the semiconductor structure 2, silver ions and other positively charged ions 11 selectively from the electrolyte become solid and form a layer 216 comprising a material of silver. At the electrode, the silver atom and one or more of its 20 94147 200834684 are dissolved in the electrolyte and the atoms of the element are dissolved. In other realities, including silver Layer 216 of material can be chemically
程或電漿加強化學氣相沉積製程中形成，而不需區 予以形成，在 一化學氣相沉 ，而不需區別Process or plasma enhanced chemical vapor deposition process, without the need to form a zone, in a chemical vapor deposition, without distinction
鐘至大約二小時之範圍内。在該退火製程 中可私加包括銀之該材料的顆粒大小（grain size)，並關 閉在形成包括銀之材料的層216之期間所可能已經形成之 空隙（void)。因此，可改善該包括銀之該材料的導電率。 其優點在於，相較於參閱第1&至lb圖（其中，接觸通孔係 籲以鎢來填充）之依據前述目前技術之方法中所實施的，在該 退火製程期間該顆粒大小之增加及空隙之關閉可更有效率 地貫施。 第2b圖顯示半導體結構200於該方法之較後階段之 示意剖面圖。在形成包括銀之材料的層216後，實施平坦 化（planarization)製程，以將層216之位於接觸通孔211、 212、213之外之部分予以移除。該平坦化製程可為化學機 械研磨製程’在該化學機械研磨製程中，半導體結構2〇〇 係相關於研磨墊（polishing pad)而移動，其中，該研磨墊接 94147 21 200834684 •觸層2!6。裝料_巧)係供應至位於半導體結構㈣ 研磨墊之間之介面’該漿料包括—種或更多種化學化合 物’該化學化合物係用來與半導體結構綱之表面上的材 料起化學反應，尤其是，該漿料可與包括銀之層216的材 料起化學反應。該化學反應的生成物藉由包含於該裝料及/ 或該研磨墊中之研磨料（abrasive)而予以移除。 該化學機械研磨製程可在包括鍺之材 層 •露於半導體結構綱之表面時，便立即停止。妹錯之^ 料的層214在該化學機械研磨製程中不需被移除。其優點 在於，此可有助於減少包括銀之材料的層216位於接觸通 孔211、212、213之内側的部分被損壞之風險，如果包括 錄之材料的層214在該化學機械研磨製程中亦被移除的 話’則該損壞便有可能發生。 包括錢之材科的層217可沉積在半導體結構細上。 層217可包括與層214相同的材料，尤其是，層及層 籲217二者可皆包括純鍺。 θ 包括鍺之材料的層217可藉由電鍍製程來予以形成， 在“電鐘衣耘中，半導體結構2〇〇係插入於包括錄鹽（例如 硫酸，）之電解液中。除了半導體結構2〇〇外，包括姥之電 :=提供於該电解液中。電壓係施加於半導體結構2〇〇與 =電極之間，該電壓之極性使得（至少平均）半導體結構2〇〇 變成陰極，而該電極變成陽極。因此，在半導體结構200 處’，該電解液來的姥離子被中和（—rake)，並從該溶 解狀〜'艾成固恶，以形成包括铑之材料的層217。在該電 94147 22 200834684 •極處’姥原子被離子化，並從在該電極中之固態變成在咳 卜電解液中之溶解狀態。在其他實施例中，可採用賤錢、原: ，子層沉積、化學氣相沉積及/或電漿加強化學氣相沉積，來 形成包括铑之材料的層217，類似於上述之層2丨4之形成。 層217之厚度可在從大約5至3〇奈米之範圍内，尤其是， 層217之厚度可在從大約從5至1〇奈米之範圍内。、 在形成包括铑之材料的層217後，遮罩21 8可形成在 ⑩半導體結構200之上，該遮罩覆蓋接觸通孔211、212 = 213。 遮罩218可包括光阻（ph0t0Tesist)，且可藉由該領域中熟習 技術者所已知的光微影術製程來予以形成。 實施蝕刻製程以移除包括層214、217之铑的材料， 保留遮罩218及層218之介電材料實質上原封不動 (intact)。在一些實施例中，該蝕刻製程可為乾式蝕刻製 程，在乾式蝕刻中，輝光放電係產生於蝕刻氣體中，該蝕 刻氣體可例如包括氟或包括氟之化學化合物。該輝光放電 φ可藉由施加高頻交流電壓及/或可為低頻交流電壓或直流 電壓之偏壓於半導體結構200與設置於半導體結構2〇〇附 近之電極之間來產生。或者，該高頻交流電壓及該偏壓可 施加在第一及第二電極之間，其中，該等電極之一者係設 置在半導體結構200之附近。在該輝光放電中，化學反應 物種（例如原子、基及/或離子）係從該蝕刻氣體產生。該化 學反應物種可與包括在層214、217中之铑的材料起化學反 應，以產生揮發性反應生成物，該揮發性反應生成物可被 抽_出反應态谷裔，該鼓刻製程係實施於該反應器容器 23 94147 200834684 ，中。尤其是，包括鍺及氟之揮發性化學化合物可從層214、 ' 217中之錄來產生。 在其他貫施例中，層214、21 7未被遮罩21 8所覆蓋 之部分可藉由溼式化學蝕刻製程（wet chemical etching process)予以移除，在該溼式化學蝕刻製程中，半導體結構 200係恭露於具有化學化合物之溶液中，該化學化合物與 铑起化學反應。例如，該化學化合物可包括臭氧及/或氯化 氫’其可以水溶液的形成來予以提供。 苐2c圖减示半導體結構2〇〇於該製造製程之較後階 段之不意剖面圖。在該蝕刻製程後，可例如藉由已知的光 阻剝除製程來將遮罩218予以移除。在該蝕刻製程後，在 ，括接觸通孔2H、212、213之各者中的銀之材料之間的 實質上整個介面均被包括鍺之材料的層214、217所覆蓋。 ,然而，本發明並非受限於包括鍺之材料的層214、2i7The clock is within about two hours. The grain size of the material comprising silver may be privately applied during the annealing process and the voids that may have formed during the formation of the layer 216 comprising the material of silver may be closed. Therefore, the electrical conductivity of the material including silver can be improved. The advantage is that the particle size increases during the annealing process as compared to the method of the prior art described above with reference to the first & to lb (where the contact via is filled with tungsten) The closing of the gap can be applied more efficiently. Figure 2b shows a schematic cross-sectional view of the semiconductor structure 200 at a later stage of the method. After forming the layer 216 comprising the material of silver, a planarization process is performed to remove portions of the layer 216 that are outside of the contact vias 211, 212, 213. The planarization process can be a chemical mechanical polishing process. In the chemical mechanical polishing process, the semiconductor structure 2 is moved in relation to a polishing pad, wherein the polishing pad is connected to 94147 21 200834684 • the contact layer 2! 6. The charge is supplied to the interface between the semiconductor structure (4) polishing pad. The slurry includes one or more chemical compounds. The chemical compound is used to chemically react with the material on the surface of the semiconductor structure. In particular, the slurry can be chemically reacted with a material comprising layer 216 of silver. The product of the chemical reaction is removed by an abrasive contained in the charge and/or the polishing pad. The CMP process can be stopped immediately when it is exposed to the surface of the semiconductor structure. Layer 214 of the wrong material does not need to be removed during the chemical mechanical polishing process. This has the advantage that this can help reduce the risk of damage to the portion of the layer 216 comprising the silver material that is inside the contact vias 211, 212, 213 if the layer 214 comprising the recorded material is in the chemical mechanical polishing process. If it is also removed, then the damage may occur. A layer 217 comprising a material of the family of money can be deposited on the fine structure of the semiconductor structure. Layer 217 can comprise the same material as layer 214, and in particular, both layers and layers 217 can include pure germanium. θ The layer 217 comprising the material of tantalum can be formed by an electroplating process in which the semiconductor structure 2 is inserted into an electrolyte comprising a salt (for example, sulfuric acid). In addition, the electricity is included in the electrolyte: the voltage is applied between the semiconductor structure 2 and the = electrode, the polarity of the voltage is such that (at least average) the semiconductor structure 2 turns into a cathode, and The electrode becomes an anode. Therefore, at the semiconductor structure 200, the cerium ions from the electrolyte are neutralized, and from the dissolved state to the smear, a layer 217 is formed to form a material including ruthenium. At the end of the electricity 94147 22 200834684 • The cesium atom is ionized and changes from a solid state in the electrode to a dissolved state in the cough electrolyte. In other embodiments, the money can be used, Sublayer deposition, chemical vapor deposition, and/or plasma enhanced chemical vapor deposition to form a layer 217 comprising a material of tantalum, similar to the formation of layer 2丨4 described above. Layer 217 may range in thickness from about 5 to Within the range of 3 〇 nano, especially Yes, the thickness of layer 217 can range from about 5 to 1 nanometer. After forming layer 217 comprising a material of germanium, mask 21 8 can be formed over 10 semiconductor structure 200, the mask The cover contact holes 211, 212 = 213. The mask 218 may include a photoresist (ph0t0Tesist) and may be formed by a photolithography process known to those skilled in the art. The material comprising layers 214, 217, leaving the dielectric material of mask 218 and layer 218 substantially intact. In some embodiments, the etching process can be a dry etch process, in dry etch, glow The discharge system is generated in an etching gas, which may include, for example, fluorine or a chemical compound including fluorine. The glow discharge φ may be applied to the semiconductor by applying a high-frequency alternating voltage and/or a bias of a low-frequency alternating current voltage or a direct current voltage. The structure 200 is formed between an electrode disposed adjacent to the semiconductor structure 2A. Alternatively, the high frequency alternating voltage and the bias voltage may be applied between the first and second electrodes, wherein one of the electrodes is Setting In the vicinity of the semiconductor structure 200, in the glow discharge, chemical reaction species (e.g., atoms, radicals, and/or ions) are generated from the etching gas. The chemical reaction species may be combined with the materials included in the layers 214, 217. A chemical reaction is initiated to produce a volatile reaction product which can be pumped out of the reaction state, and the drumming process is carried out in the reactor vessel 23 94147 200834684. In particular, including hydrazine And fluorine volatile chemical compounds can be generated from layers 214, '217. In other embodiments, the portions of layers 214, 21 7 that are not covered by mask 21 can be processed by a wet chemical etching process. The (wet chemical etching process) is removed. In the wet chemical etching process, the semiconductor structure 200 is condensed in a solution having a chemical compound that reacts with the chelating chemical. For example, the chemical compound can include ozone and/or hydrogen chloride, which can be provided by the formation of an aqueous solution. The 苐2c diagram reduces the unintentional cross-sectional view of the semiconductor structure 2 at a later stage of the fabrication process. After the etching process, the mask 218 can be removed, for example, by a known photoresist strip process. After the etching process, substantially the entire interface between the materials of silver in each of the contact vias 2H, 212, 213 is covered by layers 214, 217 comprising a material of germanium. However, the invention is not limited to layers 214, 2i7 comprising materials of tantalum.
此可藉由各向異性蝕刻製程來予以 之底部的部分可在晶種層215 因此，包括在接觸通孔211、212、213之各者十的銀之材 料係由包括由層2U、217之數個部分所形成之錢的材料之 框架（cage)所包圍。包括錢之該材料可防止該銀舆介電層 2/0之材料接觸’故能化學性及機械性的保護該銀，尤^ 是，鍺具有高的化學穩定性(high cheiftieal ⑺。’、 形成框架之實相… 通孔 211、212 例中’在形成晶種層215之前， 於接觸通孔211、212、213之j 形成前先移除。此可藉由夂命至 以完成， 94147 24 200834684 := 各向異性㈣製程係用來以較層2i4於接觸通孔叫、 • - 213之側壁上的部分為高的速率移除層214於接觸通 _ m212、2i3之底部處之實質上水平部分。在這種實 :例中&括日日種層215及層216之銀的材料接觸源極區 跡閘電極205和汲極區2〇9之石夕。在層216之形成後所 貫施的退火製程中’包括銀之材料於接觸通孔2ιι、2ΐ2、 之底4處之分可與源極區2〇8、閘電極和沒極區 ❿209之石夕起化學反應’以形成銀石夕化物。其優點在於，該 銀石夕化物之形成有助於減少包括在接觸通孔2U、212、213 中之銀的材料與源極區2〇δ、閘電極2〇5和沒極區之 間的接觸電阻（contact resistance)。 凡弟2c圖顯示半導體結構2〇〇於該製造製程之較後階 段:之示意剖面圖。類似於依據參閱第la至lb圖之前述 目士前技術之製造方法，層221之介電材料可形成在半導體 、、Ό構200之上，層221可包括與層210相同的材料，或可 •包括=同的材料。在層221之形成過程中，可採用該領域 中熟習技術者已知的沉積製程，例如化學氣相沉積及/或電 漿加強化學氣相沉積。 在層221中，係形成有溝槽222、223、224,溝槽222、 223、224係類似於參閱第1&至之上述實施例中的溝 槽122、123、124。為了這個目的，係使用該領域中熟習 技術者所已知的光微影術及蝕刻方法。在溝槽222、223、 224中’可形成障壁層225、晶種層227及導電材料之層 25 94147 200834684 在些只％例中，晶種層227及導電材料之層226可 匕括銅，在這種實施例中，障壁層奶可包括鈕及/或氮化 短。障壁層225可有助於防止或至少減少銅從晶種層227 2及/Λ層I226擴散至層221之介電材料内及至半導體結構 ，化組件内’尤其是’障壁層225可有助於防止或 ::銅擴散至場效電晶體2〇2内，這樣便可實質地避免場 》包曰日體202因课的雜質層而減低效能，該深的 ，銅原子被吸收至半導體基底2〇1之結晶結構内所引 日曰種層227可猎由無電電鍍(electr〇le 學 沉積及/或雷喈加強几風-丄 子孔序目 :飞電水加強化學氣相沉積來予以形成，而層226則 可猎由電鍍來予以形成。 在其它實施例中，晶種層227及導電材料之層226可 ^㈣之材料組成’其中，可使用實質上為純的銀或銀 二在4種貫施例中，障壁層225之材料可由包括錄之 材料組成，類似於以上所描述的層214。類似於層214之 ’ ST/:早壁層225可藉由濺*、原子層沉積、化學氣相沉 似/或電漿加強化學氣相沉積來予以形成1種層227可 ::化Τ虱相沉積、電漿加強化學氣相沉積及/或無電沉積 :以形成’類似於以上所描述的晶種層125之形成。類 =包括銀之材料的層216之沉積，導電材料之層加（當 匕括銀之材料組成時）可藉由電鍍製程來予以沉積。 芥总：形成導電材料之層226後，實施平坦化製程，例如 化于機械研磨$程，以將㈣材料之層226及晶種層 位於溝槽222、223、224之外的部分予以移除。此外，在 94147 26 200834684 該平坦化製程中，障壁層225位於溝槽222、223、224之 外的部分可被移除。 在晶種層227及導電材料之層226包括銀而障壁層 225包括錄之一些實施例中，障壁層225在該平坦化製程 中π有被私除。在這種實施例中，障壁層位於溝槽 222 223、224之外的部分可藉由蝕刻製程來予以移除， ^似於上述之用於移除包括铑之材料的層214位於接觸通 孔1 212 213之外的部分之蝕刻製程。在一些實施例 中，另一層包括铑之材料可形成在溝槽222、223、224之 上方，類似於形成於接觸通孔211、212、213之上方的包 括铑之材料的層217。 在移除層226、晶種層227及導電材料之層挪位於 ' 2 223 224之外的部分後，這些層位於溝槽222、 ⑵、224之内側的其餘部分形成導電線⑽咖^办 uctive lme) ’該導電線可將源極區⑽ 和汲極區209遠接δ尘、曾_ mu 導體結構2GG中之其他電路元件。 ==广閘電極2。5和汲極區2〇9之間的電 &連接係由包括設置在接 銀的該材料所提供。觸通孔11、212、213中之包括 者而二為m ^此處所教不内容之本領域中的熟習技術 上所2 之方式來予峰改及實行。例如，以 A❸製程步驟可以不同的次序加以實施。此外，並 限制此處所顯示之架構及設計之細節1 了如以下 94147 27 200834684 申请專利範圍所描述的。如此—攻 + 此來，很明顯的，以上所揭 路=特別貫施例可加以改變或修改，而所有這種變化均應 :為係在本發明之範.及精神内。因此，此處所尋求的保 表係如以下之申請專利範圍中所提出的。 【圖式簡單說明】 .二發明可藉由參閱以上的敘述連同附隨的圖式而了 =在圖式t，相似的元件符號係指相似的元件，且在圖 第la至lb„示依據目前技術之製造半導體結構之 方法=多個階段中之半導體結構的示意剖面圖；以及 導wtr至&圖顯示㈣此處所揭露之實施例之製造半 VI。構之方法的多個階段中之半導體結構的 圖。 ^ W4 雖然此處所揭露之標的㈣㈣可有不同 f及替換形式’惟該標的之特定實施例已經藉由圖示中之 耗例而予以顯示且在此處詳細地描述。然而，應了解的是， 特定實施例此處的㈣並不是要將本發·料:， 特別形成，相反地，是要涵蓋所有落於附加之申浐鼻^ 圍所定義之本發明的精神及範疇内之修改、均等者、及= 換者。 曰 【主要元件符號說明】 100 、 200 101 、 201 102 、 202 半導體結構 基底 場效電晶體 94147 28 200834684 103 、 203 主動區 104 、 204 溝槽隔離結構 1 105 、 205 閘電極 106 、 206 閘極絕緣層 107 、 207 側壁間隔件結構 108 、 208 源極區 109 ^ 209 >及極區 110 層、第一層、第 • 111 、 112 、 113 、 211 、 212 、 213 114 第一膠層、膠層 115 第二膠層、膠層 一介電層 接觸通孔 226 層 溝槽 116、127、215、227 晶種層. 117 、 126 、 214 、 216 、 217 、 221 118、119、120 接缝 121 第二層 • 122 、 123 、 124 、 222 、 223 、 224 125、225 障壁層 218 遮罩 210 層、介電層 29 94147The portion of the bottom portion which can be imparted by the anisotropic etching process can be in the seed layer 215. Therefore, the material of the silver included in each of the contact vias 211, 212, 213 is comprised of the layers 2U, 217. Surrounded by the framework of the material of the money formed by several parts. The material including the money prevents the material of the silver-tantalum dielectric layer 2/0 from contacting, so that the silver can be chemically and mechanically protected, in particular, the yttrium has high chemical stability (high cheiftieal (7).', Forming the actual phase of the frame... In the example of the via holes 211, 212, before the formation of the seed layer 215, before the formation of the contact vias 211, 212, 213 is removed, this can be done by killing, 94147 24 200834684 := The anisotropic (four) process is used to remove the layer 214 at the bottom of the contact pass _ m212, 2i3 at a higher rate than the portion of the contact via, the side wall of the contact hole. The upper horizontal portion. In this example, the material of the silver layer 215 and the layer 216 of silver contact the source region gate electrode 205 and the drain region 2〇9. In the subsequent annealing process, the material including silver is chemically reacted with the source region 2〇8, the gate electrode and the gate region 209 at the bottom 4 of the contact vias 2, 1 and 2, respectively. Forming a silver-stone compound. The advantage is that the formation of the silver-stone compound helps to reduce the contact through the via 2U. The contact resistance between the material of the silver in 212, 213 and the source region 2 〇 δ, the gate electrode 2 〇 5, and the non-polar region. The Figure 2c shows that the semiconductor structure 2 is in the manufacturing process. A later stage: a schematic cross-sectional view. Similar to the manufacturing method of the aforementioned prior art according to the first to fifth embodiments, the dielectric material of the layer 221 may be formed over the semiconductor, the structure 221, and the layer 221 may include The same material as layer 210, or may include the same material. During the formation of layer 221, deposition processes known to those skilled in the art, such as chemical vapor deposition and/or plasma enhanced chemistry, may be employed. Vapor deposition. In the layer 221, trenches 222, 223, 224 are formed, and the trenches 222, 223, 224 are similar to the trenches 122, 123, 124 of the above-mentioned embodiments to the first & For this purpose, photolithography and etching methods known to those skilled in the art are used. In the trenches 222, 223, 224, a barrier layer 225, a seed layer 227 and a layer of conductive material 25 94147 can be formed. 200834684 In only a few cases, the seed layer 227 and the conductive material The layer 226 can include copper. In such an embodiment, the barrier layer milk can include a button and/or nitride short. The barrier layer 225 can help prevent or at least reduce copper from the seed layer 227 2 and/or the layer. I226 diffuses into the dielectric material of layer 221 and into the semiconductor structure, and the 'especially' barrier layer 225 within the component can help prevent or:: copper diffuse into the field effect transistor 2〇2, which substantially avoids The field contains the impurity layer of the body 202 to reduce the efficiency. The deep copper atoms are absorbed into the crystal structure of the semiconductor substrate 2〇1. The layer 227 can be hunted by electroless plating (electr〇le) Learn to deposit and / or thunder to strengthen the wind - scorpion hole order: flying water to strengthen chemical vapor deposition to form, and layer 226 can be hunted by electroplating to form. In other embodiments, the seed layer 227 and the layer 226 of conductive material may be composed of a material of '(4), wherein substantially pure silver or silver may be used. In four embodiments, the material of the barrier layer 225 may be included. The recorded material composition is similar to layer 214 described above. The 'ST/: early wall layer 225 similar to layer 214 can be formed by sputtering*, atomic layer deposition, chemical vapor deposition, or plasma enhanced chemical vapor deposition to form a layer 227. Phase deposition, plasma enhanced chemical vapor deposition, and/or electroless deposition: to form 'forms similar to the seed layer 125 described above. Class = deposition of layer 216 comprising a material of silver, a layer of conductive material (when composed of a material comprising silver) can be deposited by an electroplating process. After the formation of the layer 226 of conductive material, a planarization process is performed, such as mechanical polishing, to remove the layer 226 of the material and the portion of the seed layer outside the trenches 222, 223, 224. . Further, in the flattening process of 94147 26 200834684, the portion of the barrier layer 225 outside the trenches 222, 223, 224 can be removed. In the embodiment in which the seed layer 227 and the layer 226 of conductive material comprise silver and the barrier layer 225 is included, the barrier layer 225 is privately removed during the planarization process. In such an embodiment, the portion of the barrier layer outside the trenches 222, 224, 224 can be removed by an etching process, as described above for removing the layer 214 comprising the germanium material in the contact via. Etching process for parts other than 1 212 213. In some embodiments, another layer of material comprising tantalum may be formed over trenches 222, 223, 224, similar to layer 217 of a material comprising tantalum formed over contact vias 211, 212, 213. After removing the layer 226, the seed layer 227, and the layer of the conductive material from the portion other than '2 223 224, the layers are located on the inner side of the trenches 222, (2), 224 to form a conductive line (10). Lme) 'The conductive line can connect the source region (10) and the drain region 209 to other circuit components in the δ dust, _mu conductor structure 2GG. == The electrical & connection between the wide gate electrode 2. 5 and the drain region 2〇9 is provided by the material including the silver provided. The inclusion of the through holes 11, 212, and 213 is the same as the method of the prior art in the art. For example, the A❸ process steps can be implemented in a different order. In addition, and the details of the architecture and design shown herein are limited as described in the following Patent Application Serial No. 94147 27 200834684. In this way, it is obvious that the above-mentioned method can be changed or modified, and all such changes should be made within the scope and spirit of the present invention. Accordingly, the warrants sought herein are as set forth in the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS The invention may be referred to by the above description in conjunction with the accompanying drawings. In the drawings, like reference numerals refer to the like elements, and A method of fabricating a semiconductor structure in the prior art = a schematic cross-sectional view of a semiconductor structure in a plurality of stages; and a guide wtr to & graph display (d) in a plurality of stages of the fabrication of the embodiment of the disclosed embodiment A diagram of a semiconductor structure. W4 Although the subject matter of (4) and (4) disclosed herein may have different f and alternative forms, the specific embodiment of the subject matter has been shown by way of example in the drawings and is described in detail herein. It should be understood that the specific embodiments herein (4) are not intended to cover the present invention, and are specifically formed, and conversely, to cover all the spirits of the present invention as defined by the appended claims. Modifications, equals, and = replacements within the scope. 曰 [Main component symbol description] 100, 200 101, 201 102, 202 Semiconductor structure base field effect transistor 94147 28 200834684 103 , 203 active area 104 204 trench isolation structure 1 105 , 205 gate electrode 106 , 206 gate insulating layer 107 , 207 sidewall spacer structure 108 , 208 source region 109 ^ 209 > and pole region 110 layer, first layer, 111 , 112 , 113 , 211 , 212 , 213 114 first adhesive layer , adhesive layer 115 second adhesive layer , adhesive layer - dielectric layer contact via 226 layer trench 116 , 127 , 215 , 227 seed layer . 126, 214, 216, 217, 221 118, 119, 120 Seam 121 Second layer • 122, 123, 124, 222, 223, 224 125, 225 barrier layer 218 mask 210 layer, dielectric layer 29 94147