200820419 九、發明說明： 【發明所屬之技術領域】 本發明大體係關於半導體裝置，且更特定言之係關於電 源開關裝置及其方法。 【先前技術】 金氧半場效電晶體（MOSFET)為常見類型之電源開關裝 置。一 MOSFET裝置包括一源極區域、一汲極區域、一在 源極區域與沒極區域之間延伸之通道區域，及一經提供而 馨 鄰近該通道區域之閘極結構。該閘極結構包括一經安置而 鄰近通道區域且藉由一薄介電層與通道區域分離的導電閘 電極層。 當一 MOSFET裝置處於開啟狀態中時，將一電壓施加至 閘極結構以在源極區域與汲極區域之間形成一導電通道區 域’其允許電流流經裝置。在關閉狀態中，施加至閘極結 構之任何電壓足夠低而使得不會形成一導電通道，且因此 不發生電流流動。在關閉狀態期間，裝置必須支持源極區 ® 域與汲極區域之間的高電壓。 當今之高電壓電源開關市場由兩個主要參數推動：崩潰 電壓（BVdss)及開啟後電阻（Rds〇n)。特定應用需要一最小 朋’貝電壓，且實務上，設計者通常可進行設計以滿足一 BVdss規格。然而，此常常是以Rdson為代價的。關於效能 執行此項取捨對於高電壓電源開關裝置之製造者及使用者 而言為主要設計挑戰。 最近’超接合裝置已在改良之間的取捨方 115962.doc 200820419 面贏得了普遍認可。在一習知n_通道超接合裝置中，多個 重摻雜之經擴散η-型區域及p-型區域代替一個輕摻雜之^ 型磊晶區域。在開啟狀態中，電流流經重摻雜之心型區 域，此降低了 Rdson。在關閉或阻斷狀態中，重摻雜之卜 型區域及p-型區域耗乏至彼此中或彼此補償以提供高 BVdss。儘管超接合裝置看似有前途，但在其製造方面Z 存在重大挑戰。 ‘萷尚電壓電源開關產品之另一問題為其通常需要大的 _ 輸入（例如，閘電極或控制電極）電荷用於自一個狀態切換 至另一狀態。此需要對周邊控制電路形成額外負擔。 因此，需要用於提供較低Rdson、高BVdss及減少輸入電 荷之高電壓電源開關裝置結構及其製造方法。 【實施方式】 為易於理解，不必將所繪製之圖中之元件按比例繪製， 且相同元件編號始終適當地用於各個圖式中。雖然以下論 φ 述描述一 n_通道裝置，但本發明亦係關於p-通道裝置，其 可藉由反轉所描述層及區域之導電類型來形成。 此外，本發明之裝置可包含一單元式設計（其中主體區 域為複數個單元式區域）或一單體設計（其中主體區域由一 以狹長樣式（通常以一蜿蜒蛇形樣式）形成之單一區域組 成）。然而’為易於理解，將在整個描述中將本發明之裝 置描述為單元式設計。應理解本發明意欲包含一單元式設 計及一單一基底設計兩者。 圖1展示一根據本發明之絕緣閘場效應電晶體（IGFET)、 115962.doc 200820419 Γ:ΕΤ、超:合裝置或開關裝置或單元1〇的放大部分橫 m面圖。以實例說明 一加M人 衣直為與邏輯及/或其他組件 起正&至一半導體晶片中作一辦 -^.^ ^ ^ 電源積體電路之部分的 泎多此#裝置其中之一。或者，裝 ^ Α Α υ馬整合在一起以形 成一離政電晶體裝置之許多此等裝置其中之一。 裝置10包括半導體材料 ,,ΛΛ Α Λ 其包含（例如）具有範圍 在、、、勺0.001至約0 005歐姆-公 坶A刀内之電阻率的η-型矽基板 12’且其可摻雜有砷。在 牡所辰不之κ施例中，基板12提供 -汲極接觸。一半導體層14形成於基板12之中或之上，且 根據本發明為輕微摻雜的η_型或卜型，或含有可忽略量的 雜質(亦即，為固有雜質)。在一例示性實施例中，使用習 知蠢晶生長技術來形成層14。在—適用於75g伏特裝置之 例示性實施例中’層14為一具有約每立方公们㈣13個 原子至約每立方公分5.GxlGl3個原子之摻雜濃度的p_型， 且具有約4G微米左右之厚度。«置之所要BVdSS額定 值而定來增加或減少層14之厚度n解其他材料可用於 半導體材料主體U或其部分，包括錢、料碳、推雜石夕 之碳，或其類似物。 裝置10亦包括-形成於半導體材料區之上表面或主 表面18之中或鄰近處的n-型區域或毯覆層17。如將在下文 更詳細描述’ η·型區域17為裝置1G提供—低電阻電流路 徑。在-例示性實施例中，n_型區域17具有一約每立方公 刀6.0x10個原子左右的最大濃度，及約0.4微米的厚度。 視需要，一P-型區域或毯覆層19形成於主表面“之中或鄰 115962.doc 200820419 近處’且其在η·型區域17之下或鄰近卜型區域17。p_型區 域19對η-型區域17與半導體層14之間的叩接面提供較佳控 制，且在完全空乏條件下為η_型區域丨7提供電荷補償。在 一例不性實施例中，型區域19具有一約每立方公分 5·〇χ 1015個原子的表面濃度，及約〇·8微米的厚度。 根據本發明，裝置10進一步包括填充溝渠、半導體材料 填充溝渠、磊晶填充區域或溝渠、電荷補償溝渠區域、深 溝渠電荷補償區域、電荷補償填充溝渠或電荷補償區域 22。電荷補償填充溝渠22包括複數層或多層包括相反導電 類型之層的半導體材料，其較佳被一或多個本質或緩衝半 導體層分離。本質層起到防止相反導電類型層（亦即，兩 個電荷層）互混的作用，該彼此混合可在開啟狀態中對裝 置10之導電效率產生不良影響。 在一例示性實施例中，填充溝渠22包括使用磊晶生長技 術形成的多層或堆疊半導體材料層。舉例而言，填充溝渠 22包括一η-型層23，該η-型層23形成於鄰近半導體材料主 體11處之溝渠壁或表面上、上方或鄰接溝渠壁或表面。本 貝半導體層或緩衝層24形成於η_型層23上、上方或鄰接η_ 型層23，卜型層26形成於本質半導體層24上、上方或鄰接 本質半導體層24,及本質半導體層或緩衝層27形成於卜型 層26上、上方或鄰接Ρ-型層26。本質層24起到防止層23與 層26混合的作用，如前面所陳述，此改良了裝置1〇之導電 效率。本質層27起到填充溝渠之剩餘部分的作用。對於η_ 通道裝置且根據本發明，η_型層23在裝置1〇處於開啟狀態 115962.doc -10- 200820419 中時提供自通道至沒極的主垂直低電阻電流路徑。當裝置 ίο處於關閉狀態時，n•型層23Ap_型層26根據本發明彼此 補償以提供-增加的BVdss特徵。應瞭解，可使用額外& 3L層及p 5L層且其較佳被額外本質層或緩衝層分離開。 以實例說明之’ n_型層23&ρ_型層26各具有約每立方公 分2.0Χ，至約4.〇χ1〇16個原子左右的摻雜濃度且各具有 約0.1微米至約0.3微米的厚度。在—例示性實施例中，本 質半導體層或緩衝層24及27為未經摻雜的或具有少於約每 立方a刀2.〇χΐ〇㈤原子 < 推雜濃度之極輕微換雜的ρ_ 型’且每一者具有約0.5微米至约1.0微米的厚度。調整層 27之厚度（例如）以填充平衡溝渠。 主體區域或摻雜區域31形成於半導體層14中，在填充溝 渠22之間及接近或鄰近填充溝渠22，且自主表面a延伸。 在-例示性實施例中’主體區域31包含卜型導電性，且且 有適用於形成-反轉層之摻雜濃度，該反轉層作為如下2 所描述之裝置10之導電通道45操作。主體區域31自主表面 18延伸至約L〇至約5 半的择 锨木的/木度。一卜型源極區域33形 成於主體區域31内部或之中^主表面18延伸至約〇2微 未至約0.5微米的深度…卜型主體接觸區域或接觸區域％ =形成於主體區域31中’且在主表面18處提供一較低接觸 阻至主體區域31。此外，接觸區域36降低了源極區域Μ 之下的主體區域31之薄片電阻’如此抑制了寄生雙極效 應。 第一介電層4!形成於主表面18之部分的上方或鄰接主表 115962.doc 200820419 面18的部分。在一例示性實施例中，介電層4ι包含一具有 約0.1微米至約0.2微米之厚度的熱氧化層。第二介電層42 形成於介電層41之上方。在一例示性實施例中，第二介電 層42包含氮化矽，且具有一約〇1微米之厚度。 閘極介電層43形成於主表面18之鄰近主體區域31之其他 部分上方或鄰接該等主表面丨8的其他部分。在一例示性實 鉍例中，閘極介電層43包含氧化矽，且具有一約〇〇5微米 至約〇· 1微米之厚度。在替代性實施例中，閘極介電層43 包含氮化矽、五氧化鈕、二氧化鈦、鈦酸勰鋇或其組合 (包括與氧化矽之組合），或其類似物。 根據本發明之一實施例，一摻雜之多晶半導體層、導電 層或接地平面層46形成於介電層41及42上方，且經由形成 於介電層41及42之中的開口 47接觸p_型層26。在一例示性 實施例中，導電層46包含一多晶矽層，具有約❹丨微米之 厚度，且具有用於一 n-通道裝置之p_型導電性。當進行熱 處理時，ρ-型摻雜物自導電層46擴散至填充溝渠22中以形 成Ρ-型摻雜區域52，ρ-型摻雜區域52增強了與ρ_型層26之 歐姆接觸。在一替代性實施例中，導電層46包含非晶矽、 金屬、矽化物或其組合（包括與多晶矽之組合）。若將金屬 用於導電層46，則首先經由開口 47植入或沈積严型摻雜物 以形成Ρ-型摻雜區域52來增強與ρ-型層26的歐姆接觸。較 佳將導電層46直接或間接連接或耦合至如圖i所示之導電 接觸層或源極接觸層63。 根據本發明，導電層46充當一接地平面以提供一路徑用 115962.doc -12· 200820419 於將少數載子快速且更有效地自裝置清除或清除出裝置， 此減j/ 了用於將裝置丨0自一個狀態切換至另一狀態所需 輸入電射且提高了切換速度。此外，如將在下文更詳細 缸述，導電層46另外用作根據本發明之一邊緣終止結構的 部分。 第三介電層48形成於導電層46上方，及第四介電層51形 成於第二介電層48上方。在一例示性實施例中，介電層48 垂包合虱化矽（例如，厚度約0.05微米），且介電層51包含一 沈積乳化矽層（例如，厚度約〇·7微米）。導電層53形成於介 電層51卜 ’且匕含（例如）n-型多晶石夕（例如厚度約〇·3微 米）。 導電間隔閘極區域、垂直間隔閘極區域或間隔界定之閘 ::域57形成於閘極介電層43上方，且藉由介電間隔59而 與‘電層46分離。導電間隔閘極區域57連同閘極介電層43 •成控制電極或閘極結構58。導電間隔閘極區域57 • 例如）η-型多晶矽，且厚度為約〇·8微米。在一例示性 實施例中，介電間隔59包含氮切，且厚度為約微 ❿。將間隔閘極區域57搞合至導電層53以形成一導電閑極 結#，=控制通道45之形成及裝置10中電流之傳導。在所 育之Κ施例中，導電連接部分77將間隔閘極區域π耦合 5 ^電層53。導電連接部分77包含(例如)η-型多晶矽。間 隔閘極區域疋指由沈積於一個表面上之閘極材料形成以控 1形成於另1直表面上的通道之控制電極。在裝置10: 通道45形成於認為係一水平表面的表面1 ^處。沿 I15962.doc 13 200820419 垂直於表面18之垂直表㈣沈積用於形成間極 的控制電極薄膜。 』位匕堞57 5::口置相比而言’根據本發明之導電間隔閑極區域 以了取小限度的閘極對汲極重疊，從而顯著減少了門 極電荷。此外’在裝置10中’由導電層53提供閑極電ς 引，導電層53被提高至超過主表面18而進—步減少了閑極 電何。此外，導電層46充當插入在閑極區域與沒極區域之 間的接地平面以進一步減少閘極對汲極電容。本發明之此 等特徵提供了提高切換速度及減少輸入電荷之需求^。 第五介電層61形成於裝置10之部分上方，且包含(例如) 具有約0.05微米之厚度的氮切。層間介電_)層Μ形成 於裝置10之部分上方，且包含（例如）具有約0.8微米之厚度 的沈積氧化石夕。一開口形成於介電層之中而對源極接觸層 6、3提供對裝置1〇之接觸。如所展示’蝕刻主表面18之一部 分使得源極接觸層63與源極區域33及域區域％兩者接 觸。在一例示性實施例中，源極接觸層〇包含一紹石夕合金 或其類似物。沒極接觸層66形成於半導體村料區域^之相 對表面上’且包含（例如）—可焊接金屬結構（諸如鈦錄銀、 鉻鎳金，或其類似物）。 裝^ 1G之操作如下進行。假設源極端63於零伏特之電位 Vs下操作，間隔閘極區域57接收一大於裝置1〇之導電臨限 傳的控制電屢VG=r5.G伏特，且汲極端66於沒極電位ν〇=5·0 俾特下刼作。V(^Vs之值引起主體區域”在間隔閘極區域 下反轉以形成通道45，通道45將源極區域^電連接至 U5962.doc • 14 - 200820419 層17。裝置電流Is自源極端63流動且經由源極區域33、通 道45、層17、η-型層23導引至汲極端66。因此，電流1§垂 直流經η-型層23以產生—低導通電阻。在一實施例中， Is=l.〇安培。為將裝置1〇切換至關閉狀態，將一小於裝置 之導電臨限值之控制電壓％施加至間隔閘極57(例如 VG<5.0伏特）。如此移除通道45，Is不再流經裝置1〇，且導 電層46將少數載子清除出褒置。在關閉狀態中，當空乏區 域自主阻隔接面擴展時，型層23及p-型層26彼此補償， 此長:两了 BVdss在一實施例中’當層14為η·型時，主阻 隔接面由主體區域31及半導體層14形成。在另一實施例 中田層14為ρ-型時，主阻隔接面由半導體層14及基板12 形成。 現轉至圖2至圖7，描述用於形成根據本發明之裝置⑺的 製程。圖2展示在製造之早期階段裝置1〇之放大部分橫截 面圖。在一早期步驟中，介電層40形成於主表面18上方， 鲁且將可選ρ-型區域19經由介電層40離子植入至半導體層14 中。在-例示性實施例中，以約每平方公分5〇χΐ〇11個原 子之劑量及600 KeV之植入能量將硼植入以形成ρ_型層 19接者將η_型層17經由介電層40離子植入至半導體層14 中在 列示性實；^例中，以約每平方公分2·㈤〇12個原 子之劑量及600 KeV之植入能量將磷植入以形成η•型層 17 〇 遮罩層71隨後形成於主表面18上方且經圖案化以形成開 口 72。隨後使用習知技術蝕刻介電層4〇以經由開口 72暴露 H5962.doc -15- 200820419 半導體材料主體11之部分。以實例說明之，開口 72具有約 3.0微米至約5.0微米左右的寬度74。接著，經由層17、19 及14蝕刻溝渠122。在一例示性實施例中，溝渠ία延伸至 基板12之至少部分中。由為BVdss之函數的半導體層14之 居度來確疋溝渠12 2之深度。在一例示性實施例中，採用 以基於氟或氯之化學組成進行蝕刻之深反應性離子蝕刻 (DRIE)來形成溝渠122。若干技術可用於DRIE蝕刻，包括 低溫、高密度電漿或Bosch DRIE處理。在一例示性實施例 中，溝渠122具有大體上垂直的侧壁。在一替代性實施例 中，溝渠122具有一錐形輪廓，其中在溝渠下表面處的溝 渠蒐度小於寬度74。在使用習知餘刻技術形成溝渠122之 後移除遮罩層71。儘管將溝渠122陳述為複數個，但應瞭 解溝渠122可為一單一連續溝渠或經連接之溝渠矩陣（例 如，諸如在圖10中所展示且在下文所描述的溝渠）。或 者’溝渠122可為具有封閉末端且被半導體材料主體丨丨之 部分分離開的複數個個別溝渠。 圖3展示在處理之另一階段裝置1〇之放大部分橫截面 圖。此時，在溝渠122中形成、生長或沈積半導體材料之 層作為开々成填充溝渠22期間的第一階段。在一例示性實施 例中’半導艘蠢晶生長技術用於填充溝渠122。 在第步驟中，薄熱氧化物形成於溝渠122之侧壁上 以移除由DRIE步驟所引起之任何表面破壞。隨後使用習 知之各向同性餘刻技術來移除該薄熱氧化物。接著，將半 導體材料主體U置放在1晶生長反應器中且作Μ晶生 115962.doc -16 - 200820419 長製程之第—步驟進行預清潔。當選㈣為用於填充層 (例如，層23、24、26及27)之半導體材料時，諸如 SiHC13、SiH2C12、SiH4或Si2H6之發來源氣體適用於形成此 等層。在所展示之實施例中，生長毯覆層（亦即，在除溝 木122之主表面18上方生長層）。在一替代性實施例中，選 擇性磊晶生長技術用於形成層23、24、26及27使得此等層 不會形成於介電層40上方。 首先沿溝渠122之表面生長n-型層23，其中砷為一合適 的摻雜來源。在一例示性實施例中，n_型層23具有約每立 方公分2.OxlO16至約4.〇xi〇i6個原子左右的摻雜濃度，及一 約〇·1微米至約0.3微米的厚度。 接著，在η-型層23上方生長本質層或緩衝層24，且本質 層或緩衝層24為未摻雜的（除了通常存在於矽來源材料中 之微量雜質及/或在先前生長步驟之後保留在反應器腔室 中之殘餘摻雜氣體），或具有少於約每立方公分2 〇χ1〇14個 原子之摻雜濃度的極輕微摻雜的型。層24具有約〇 5微米 至約1.0微米的厚度。隨後在層24上方生長卜型層26，其中 哪摻雜源為適合的。在一例示性實施例中，型層26具有 約每立方公分2.0Χ1016至約4.0χ 10“個原子左右的摻雜濃 度’及約0·1微米至約0.3微米的厚度。在ρ_型層％上方生 長本質層或緩衝層27，且本質層或緩衝層27為未摻雜的 (除了通常存在於矽來源材料中之微量雜質及/或在先前生 長步驟之後保留在反應器腔室中之殘餘摻雜氣體），或具 有少於約每立方公分2.0Χ1014個原子之摻雜濃度的極輕微 115962.doc -17- 200820419 摻雜的P-型。層27具有一約〇·5微米至約1〇微米的厚度。 應瞭解，視溝渠122之寬度而定來調整層23、24、％及π 的厚度。在一例示性實施例中，此等層之厚度應使所產生 之蠢晶層過量填充溝渠122。當使用毯覆磊晶生長製程 時，用化學機械研磨技術、回蝕技術、其組合或其類似物 來將層27、26、24及23大體上平坦化。在平坦化處理期 間，將蠢晶層（epi layer)27、26、24及23向下或向後平坦 化至主表面18以形成填充溝渠22。在一例示性實施例中^ 平坦化處理亦移除介電層40。一額外姓刻步驟可用於進一 步自層40移除任何殘餘介電材料。若使用選擇性蟲晶生長 或選擇性回蚀技術，則介電層40可保留，且將代替如下文 所描述之層41。 圖4展示在進一步處理之後裝置1〇之放大部分橫截面 圖。第一介電層41形成於主表面18上方，且包含（例如）約 0.1微米至約0.2微米厚的氧化矽。在約75〇攝氏度下生長的 熱氧化物為適合的。在一可選步驟中，將一濺鍍蝕刻步驟 用於平滑第一介電層41之上表面或暴露表面。接著，第二 介電層42形成於介電層41上方，且包含（例如）約〇1微米之 氮化矽。一接觸光微影及蝕刻步驟隨後用於經由第二介電 層42及第一介電層41形成開口47。此暴露如圖4所示之填 充溝朱22上的主表面18之一部分。在一例示性實施例中， :開口 47具有一約〇·5微米至約ι·〇微米左右之寬度的。 導電層46¾後形成於第二介電層42上方且經由開口 47接 觸或耦合至填充溝渠22。在一例示性實施例中，導電層46 115962.doc -18- 200820419 包含約0 · 1微来夕夕 、去 、夕曰曰矽，且為沈積摻雜或未摻雜的。若 不刀始未摻雜沈積導 it k 在此例不性實施何中，導電層46摻 雜有硼以耠供對— P主層26之接觸。母平方公分約5〇><1〇15 ▲曰個原子之硼離子植入劑量以及約6〇 KeV之植 入月b里足以用於摻雜導 ’隹V電層26。在一酼後的熱處理步驟期 間，摻雜物自導電層 电曰的擴政至填充溝渠22中以形成p-型區 域52〇200820419 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to power switching devices and methods therefor. [Prior Art] A gold oxide half field effect transistor (MOSFET) is a common type of power switch device. A MOSFET device includes a source region, a drain region, a channel region extending between the source region and the non-polar region, and a gate structure provided adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to the channel region and separated from the channel region by a thin dielectric layer. When a MOSFET device is in the on state, a voltage is applied to the gate structure to form a conductive path region between the source region and the drain region that allows current to flow through the device. In the off state, any voltage applied to the gate structure is sufficiently low that a conductive path is not formed, and thus no current flow occurs. During the off state, the device must support a high voltage between the source region ® domain and the drain region. Today's high-voltage power switch market is driven by two main parameters: crash voltage (BVdss) and turn-on resistance (Rds〇n). A specific application requires a minimum voltage, and in practice, the designer can usually design to meet a BVdss specification. However, this is often at the expense of Rdson. About performance Performing this trade-off is a major design challenge for manufacturers and users of high-voltage power switchgear. Recently, the 'super-joining device has been widely accepted by the trade-off between the improvements 115962.doc 200820419. In a conventional n-channel superjunction device, a plurality of heavily doped diffused n-type regions and p-type regions replace a lightly doped epitaxial region. In the on state, current flows through the heavily doped heart region, which reduces Rdson. In the off or blocking state, the heavily doped regions and p-type regions are depleted into each other or compensate each other to provide high BVdss. Although the super-joint device appears to be promising, there are significant challenges in its manufacturing. Another problem with ‘customs voltage power switch products is that they typically require a large _ input (eg, gate or control electrode) charge to switch from one state to another. This requires an additional burden on the peripheral control circuitry. Accordingly, there is a need for a high voltage power switching device structure and method of fabricating the same for providing lower Rdson, high BVdss, and reduced input charges. [Embodiment] For the sake of easy understanding, the elements in the drawings are not necessarily drawn to scale, and the same component numbers are always used in the respective drawings. Although the following describes an n-channel device, the present invention is also directed to a p-channel device which can be formed by inverting the conductivity types of the layers and regions described. Furthermore, the apparatus of the present invention may comprise a unitary design in which the body region is a plurality of unitary regions or a single design (wherein the body region is formed by a single elongated pattern (usually in a serpentine pattern) Regional composition). However, for ease of understanding, the apparatus of the present invention will be described as a unitary design throughout the description. It should be understood that the present invention is intended to encompass both a unitary design and a single substrate design. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an enlarged portion of an insulated gate field effect transistor (IGFET), 115962.doc 200820419 Γ: ΕΤ, super-close device or switch device or unit 1 根据 according to the present invention. By way of example, one of the M-shirts is directly connected to the logic and/or other components. One of the devices in the semiconductor chip is one-^.^ ^ ^ part of the power integrated circuit . Alternatively, the Α υ υ horses are integrated to form one of many of these devices from the political crystal device. The device 10 includes a semiconductor material, and includes, for example, an n-type germanium substrate 12' having a resistivity ranging from 0.001 to about 0 005 ohm-to-A knives and is doped Arsenic. In the κ embodiment of the oysters, the substrate 12 provides a - 汲 contact. A semiconductor layer 14 is formed in or on the substrate 12 and is a lightly doped n-type or pad according to the present invention or contains a negligible amount of impurities (i.e., is an intrinsic impurity). In an exemplary embodiment, layer 14 is formed using conventional dormant growth techniques. In an exemplary embodiment suitable for a 75 g volt device, layer 14 is a p_ type having a doping concentration of about 13. Gxl Gl3 atoms per cubic metre (four) of about 13 atoms to about 3 centimeters per cubic centimeter, and having about 4G. Thickness around micron. «The thickness of the layer 14 is increased or decreased depending on the desired BVdSS rating. Other materials may be used for the semiconductor material body U or a portion thereof, including money, carbon, push carbon, or the like. Device 10 also includes an n-type region or blanket layer 17 formed in or adjacent to the upper surface or major surface 18 of the region of semiconductor material. As will be described in more detail below, the 'n-type region 17 provides a low resistance current path for the device 1G. In the exemplary embodiment, the n-type region 17 has a maximum concentration of about 6.0 x 10 atoms per cubic centimeter and a thickness of about 0.4 microns. A P-type region or blanket layer 19 is formed in the main surface "in the vicinity of or adjacent to 115962.doc 200820419" and is below or adjacent to the p-type region 17 of the p-type region. 19 provides better control of the splicing plane between the η-type region 17 and the semiconductor layer 14, and provides charge compensation for the η_type region 丨7 under complete depletion conditions. In one example, the type region 19 There is a surface concentration of about 5 〇χ 10 15 atoms per cubic centimeter, and a thickness of about 8 μm. According to the invention, the device 10 further comprises a filled trench, a semiconductor material filled trench, an epitaxial filled region or a trench, and a charge. Compensating for the trench region, the deep trench charge compensation region, the charge compensation fill trench or the charge compensation region 22. The charge compensation fill trench 22 includes a plurality of layers or layers of semiconductor material including layers of opposite conductivity types, preferably one or more essence or The buffer semiconductor layer is separated. The intrinsic layer functions to prevent the opposite conductivity type layers (ie, the two charge layers) from intermixing, and the mutual mixing can control the conduction efficiency of the device 10 in the on state. In an exemplary embodiment, the fill trench 22 includes a multilayer or stacked layer of semiconductor material formed using epitaxial growth techniques. For example, the fill trench 22 includes an n-type layer 23, the n-type layer 23 is formed on, adjacent to, or adjacent to the trench wall or surface adjacent to the semiconductor material body 11. The Benbe semiconductor layer or buffer layer 24 is formed on, above or adjacent to the η-type layer 23, The pattern layer 26 is formed on, above or adjacent to the intrinsic semiconductor layer 24, and an intrinsic semiconductor layer or buffer layer 27 is formed on, over or adjacent to the Bu-type layer 26. The intrinsic layer 24 serves to prevent The effect of layer 23 mixing with layer 26, as previously stated, improves the electrical conductivity of device 1. The intrinsic layer 27 acts to fill the remainder of the trench. For η_channel devices and in accordance with the present invention, the η-type layer 23 provides a main vertical low resistance current path from the channel to the pole when the device 1 is in the ON state 115962.doc -10- 200820419. When the device ίο is in the off state, the n•type layer 23Ap_type layer 26 according to the present hair The compensation is mutually compensated to provide an increased BVdss feature. It will be appreciated that additional & 3L layers and p 5L layers may be used and are preferably separated by additional intrinsic layers or buffer layers. By way of example, 'n_type layer 23& The p-type layers 26 each have a doping concentration of about 2.0 Å to about 4.16 Å and about 16 atoms and each have a thickness of about 0.1 μm to about 0.3 μm. In the exemplary embodiment, The intrinsic semiconductor or buffer layers 24 and 27 are undoped or have a slightly lighter ρ_type of less than about 2. 〇χΐ〇 (five) atoms per cubic a knives < A thickness of from about 0.5 microns to about 1.0 microns. The thickness of layer 27 is adjusted, for example, to fill a balanced trench. A body region or doped region 31 is formed in the semiconductor layer 14, between the filled trenches 22 and adjacent or adjacent to the filled trenches 22, and the autonomous surface a extends. In the exemplary embodiment, the body region 31 comprises a pad type conductivity and has a doping concentration suitable for forming a reversal layer which operates as a conductive via 45 of the device 10 as described in 2. The autonomous surface 18 of the body region 31 extends to a wood size of about 8 〇 to about 5 择. A type of source region 33 is formed in or in the body region 31. The main surface 18 extends to a depth of about 2 micrometers to about 0.5 micrometers. The body contact region or contact region % is formed in the body region 31. And providing a lower contact resistance to the body region 31 at the major surface 18. Further, the contact region 36 lowers the sheet resistance of the body region 31 below the source region ’, thus suppressing the parasitic bipolar effect. The first dielectric layer 4! is formed over portions of the major surface 18 or adjacent portions of the main surface 115962.doc 200820419. In an exemplary embodiment, dielectric layer 4i includes a thermal oxide layer having a thickness of from about 0.1 microns to about 0.2 microns. The second dielectric layer 42 is formed over the dielectric layer 41. In an exemplary embodiment, the second dielectric layer 42 comprises tantalum nitride and has a thickness of about 1 micron. A gate dielectric layer 43 is formed over or adjacent to other portions of the major surface 18 adjacent the body regions 31. In an exemplary embodiment, gate dielectric layer 43 comprises hafnium oxide and has a thickness of from about 5 microns to about 1 micron. In an alternative embodiment, the gate dielectric layer 43 comprises tantalum nitride, a pentoxide button, titanium dioxide, barium titanate or combinations thereof (including combinations with cerium oxide), or the like. In accordance with an embodiment of the present invention, a doped polycrystalline semiconductor layer, conductive layer or ground plane layer 46 is formed over dielectric layers 41 and 42 and is contacted via openings 47 formed in dielectric layers 41 and 42 P_type layer 26. In an exemplary embodiment, conductive layer 46 comprises a polysilicon layer having a thickness of about ❹丨 microns and having p-type conductivity for an n-channel device. When thermally treated, the p-type dopant diffuses from the conductive layer 46 into the fill trench 22 to form a Ρ-type doped region 52, and the p-type doped region 52 enhances ohmic contact with the p-type layer 26. In an alternative embodiment, conductive layer 46 comprises an amorphous germanium, a metal, a germanide, or a combination thereof (including combinations with polysilicon). If a metal is used for the conductive layer 46, a severe dopant is first implanted or deposited via the opening 47 to form the erbium-doped region 52 to enhance ohmic contact with the p-type layer 26. Preferably, the conductive layer 46 is directly or indirectly connected or coupled to the conductive contact layer or source contact layer 63 as shown in FIG. In accordance with the present invention, conductive layer 46 acts as a ground plane to provide a path for 115962.doc -12. 200820419 to quickly or more efficiently remove or remove a few carriers from the device, which is used to turn the device丨0 switching from one state to another requires input of an electric shot and increases the switching speed. Moreover, as will be described in more detail below, conductive layer 46 additionally serves as part of an edge termination structure in accordance with the present invention. A third dielectric layer 48 is formed over the conductive layer 46, and a fourth dielectric layer 51 is formed over the second dielectric layer 48. In an exemplary embodiment, dielectric layer 48 is filled with germanium (e.g., about 0.05 microns thick) and dielectric layer 51 comprises a layer of deposited emulsified germanium (e.g., having a thickness of about 7 microns). The conductive layer 53 is formed on the dielectric layer 51 and contains, for example, n-type polylith (e.g., a thickness of about 3 μm). A conductive spacer gate region, a vertical spacer gate region, or a spacer defined gate: region 57 is formed over the gate dielectric layer 43 and separated from the 'electric layer 46 by a dielectric spacer 59. Conductive spaced gate region 57 along with gate dielectric layer 43 is formed as a control electrode or gate structure 58. Conductively spaced gate region 57 • For example, η-type polysilicon, and having a thickness of about 〇·8 μm. In an exemplary embodiment, dielectric spacer 59 comprises a nitrogen cut and has a thickness of about micro. The spacer gate region 57 is bonded to the conductive layer 53 to form a conductive idle junction #, = the formation of the control via 45 and the conduction of current in the device 10. In the practice embodiment, the conductive connection portion 77 couples the spaced gate region π to the 5 ^ electrical layer 53. The conductive connection portion 77 contains, for example, an ?-type polysilicon. The spacer gate region is a control electrode formed of a gate material deposited on one surface to control a channel formed on the other straight surface. At device 10: channel 45 is formed at surface 1^ which is considered to be a horizontal surface. A control electrode film for forming the interpole is deposited along the vertical table (4) perpendicular to the surface 18 along I15962.doc 13 200820419. In the case of the 匕堞57 5:: 口 而言 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In addition, in the device 10, the idle polarity is provided by the conductive layer 53, and the conductive layer 53 is raised beyond the main surface 18 to further reduce the idle polarity. In addition, conductive layer 46 acts as a ground plane interposed between the idler region and the non-polar region to further reduce gate-to-drain capacitance. These features of the present invention provide the need to increase switching speed and reduce input charge. A fifth dielectric layer 61 is formed over portions of the device 10 and includes, for example, a nitrogen cut having a thickness of about 0.05 microns. The interlayer dielectric _) layer is formed over portions of the device 10 and includes, for example, a deposited oxidized oxide having a thickness of about 0.8 microns. An opening is formed in the dielectric layer to provide contact to the source contact layer 6, 3 to the device 1 . A portion of the etched major surface 18 is shown such that the source contact layer 63 is in contact with both the source region 33 and the domain region %. In an exemplary embodiment, the source contact layer 〇 comprises a smelting alloy or the like. The gate contact layer 66 is formed on the opposite surface of the semiconductor material region and includes, for example, a solderable metal structure (such as titanium-recorded silver, chrome-nickel gold, or the like). The operation of mounting 1G is as follows. Assuming that the source terminal 63 operates at a potential Vs of zero volts, the spaced gate region 57 receives a control power VG=r5.G volt greater than the conduction threshold of the device 1〇, and the 汲 terminal 66 is at the pole potential ν〇 =5·0 Special action. V (the value of ^Vs causes the body region) to be inverted under the interval gate region to form a channel 45, which electrically connects the source region ^ to U5962.doc • 14 - 200820419 layer 17. Device current Is from source terminal 63 Flowing and directing to the 汲 terminal 66 via source region 33, channel 45, layer 17, η-type layer 23. Thus, current 1 § flows vertically through η-type layer 23 to produce - low on-resistance. In the case of switching the device 1 〇 to the off state, a control voltage % smaller than the conduction threshold of the device is applied to the spacer gate 57 (for example, VG < 5.0 volts). 45, Is no longer flows through the device 1〇, and the conductive layer 46 removes a few carriers out of the device. In the off state, when the autonomous region of the depletion region expands, the layer 23 and the p-type layer 26 compensate each other. In the embodiment, when the layer 14 is of the η type, the main barrier interface is formed by the body region 31 and the semiconductor layer 14. In another embodiment, when the field layer 14 is ρ-type, The main blocking interface is formed by the semiconductor layer 14 and the substrate 12. Turning now to Figures 2 to 7, the description is for forming Process of the apparatus (7) of the present invention. Figure 2 shows an enlarged partial cross-sectional view of the apparatus 1 in an early stage of fabrication. In an early step, a dielectric layer 40 is formed over the major surface 18, and will optionally be ρ- The type region 19 is ion implanted into the semiconductor layer 14 via the dielectric layer 40. In an exemplary embodiment, boron is implanted at a dose of about 5 〇χΐ〇 11 atoms per square centimeter and an implantation energy of 600 KeV. In order to form the ρ_type layer 19, the η-type layer 17 is ion-implanted into the semiconductor layer 14 via the dielectric layer 40 in an exemplary manner; in the example, about 2 (f) 〇 12 atoms per square centimeter The dose and implant energy of 600 KeV implants phosphorus to form an n-type layer 17 . The mask layer 71 is then formed over the major surface 18 and patterned to form the opening 72. The dielectric layer is then etched using conventional techniques. 4〇 exposes a portion of the semiconductor material body 11 of H5962.doc -15-200820419 via opening 72. By way of example, opening 72 has a width 74 of from about 3.0 microns to about 5.0 microns. Then, via layers 17, 19, and 14 Etching the trench 122. In an exemplary embodiment, the trench ία extends to In at least a portion of the substrate 12. The depth of the trench 12 is determined by the residence of the semiconductor layer 14 as a function of BVdss. In an exemplary embodiment, a deep reaction is performed using a chemical composition based on fluorine or chlorine. Ion etch (DRIE) to form the trenches 122. Several techniques are available for DRIE etching, including low temperature, high density plasma or Bosch DRIE processing. In an exemplary embodiment, the trenches 122 have substantially vertical sidewalls. In an alternative embodiment, the trench 122 has a tapered profile wherein the trench search at the lower surface of the trench is less than the width 74. The mask layer 71 is removed after the trench 122 is formed using conventional engraving techniques. Although the ditches 122 are illustrated as a plurality, the ditches 122 may be a single continuous trench or a connected trench matrix (e.g., such as the trenches shown in Figure 10 and described below). Or the 'ditch 122' may be a plurality of individual trenches having closed ends separated by portions of the semiconductor material body. Figure 3 shows an enlarged partial cross-sectional view of the device 1 在 at another stage of the process. At this point, a layer of semiconductor material is formed, grown or deposited in the trench 122 as the first stage during the opening to fill the trench 22. In an exemplary embodiment, a semi-guided stray growth technique is used to fill the trenches 122. In the first step, a thin thermal oxide is formed on the sidewalls of the trenches 122 to remove any surface damage caused by the DRIE step. The thin thermal oxide is then removed using conventional isotropic residual techniques. Next, the body material U of the semiconductor material is placed in a 1-crystal growth reactor and pre-cleaned as a first step in the long process of 115962.doc -16 - 200820419. When (4) is a semiconductor material for filling layers (e.g., layers 23, 24, 26, and 27), a source gas such as SiHC13, SiH2C12, SiH4, or Si2H6 is suitable for forming such a layer. In the embodiment shown, the blanket blanket is grown (i.e., the layer is grown over the major surface 18 of the trench 122). In an alternative embodiment, selective epitaxial growth techniques are used to form layers 23, 24, 26, and 27 such that the layers are not formed over dielectric layer 40. First, an n-type layer 23 is grown along the surface of the trench 122, with arsenic being a suitable source of doping. In an exemplary embodiment, the n-type layer 23 has a doping concentration of about 6.OxlO16 to about 4. 〇xi〇i about 6 atoms per cubic centimeter, and a thickness of about 〇1 μm to about 0.3 μm. . Next, an intrinsic or buffer layer 24 is grown over the n-type layer 23, and the intrinsic or buffer layer 24 is undoped (except for trace impurities typically present in the germanium source material and/or retained after previous growth steps) A residual doping gas in the reactor chamber), or a very lightly doped type having a doping concentration of less than about 2 〇χ 1 〇 14 atoms per cubic centimeter. Layer 24 has a thickness of from about 5 microns to about 1.0 microns. Bud layer 26 is then grown over layer 24, which dopant source is suitable. In an exemplary embodiment, the pattern layer 26 has a doping concentration of about 2.0 Χ 1016 to about 4.0 χ 10" atoms per cubic centimeter and a thickness of from about 0.1 μm to about 0.3 μm. The intrinsic layer or buffer layer 27 is grown over %, and the intrinsic or buffer layer 27 is undoped (except for trace impurities typically present in the germanium source material and/or remains in the reactor chamber after the previous growth step) Residual dopant gas), or a very slightly doped 115962.doc -17-200820419 doped P-type having a doping concentration of less than about 2.0 Χ 1014 atoms per cubic centimeter. Layer 27 has a thickness of about 5 Å to about 5 microns. The thickness of 1 〇 microns. It will be appreciated that the thickness of layers 23, 24, %, and π is adjusted depending on the width of trenches 122. In an exemplary embodiment, the thickness of such layers is such that the resulting stupid layer Overfilling the trenches 122. When a blanket epitaxial growth process is used, the layers 27, 26, 24, and 23 are substantially planarized by chemical mechanical polishing techniques, etch back techniques, combinations thereof, or the like. During the period, the epi layers 27, 26, 24, and 23 are oriented. Or planarizing back to the main surface 18 to form the fill trench 22. In an exemplary embodiment, the planarization process also removes the dielectric layer 40. An additional surname step can be used to further remove any residual dielectric from the layer 40. Material. If a selective insect growth or selective etch back technique is used, the dielectric layer 40 may remain and will replace the layer 41 as described below. Figure 4 shows an enlarged partial cross section of the device 1 after further processing. The first dielectric layer 41 is formed over the major surface 18 and comprises, for example, about 0.1 micron to about 0.2 microns thick yttria. Thermal oxides grown at about 75 angstrom degrees Celsius are suitable. In a selection step, a sputtering etch step is used to smooth the upper surface or the exposed surface of the first dielectric layer 41. Next, a second dielectric layer 42 is formed over the dielectric layer 41 and includes, for example, about 〇1 Micron yttrium nitride. A contact photolithography and etching step is then used to form an opening 47 through the second dielectric layer 42 and the first dielectric layer 41. This exposure is as shown in FIG. One portion of surface 18. In an exemplary embodiment The opening 47 has a width of about 5 μm to about 1 μm. The conductive layer 463⁄4 is then formed over the second dielectric layer 42 and is contacted or coupled to the filled trench 22 via the opening 47. In an exemplary embodiment, the conductive layer 46 115962.doc -18- 200820419 comprises about 0·1 micro, 去, 曰曰矽, and is doped or undoped. In the case of this example, the conductive layer 46 is doped with boron to provide contact with the P main layer 26. The square square centimeters is about 5 〇><1〇15 ▲曰 atoms The boron ion implantation dose and the implantation period b of about 6 〇 KeV are sufficient for doping the conductive layer 隹V. During a subsequent heat treatment step, the dopants are expanded from the conductive layer to fill the trench 22 to form a p-type region 52.
接著，第三介電層48形成於導電層46上方，及第四介電 層51形成於第三介電層48上方。第三介電層48包含(例如) 說化石夕（例如’厚度約0·05微米），且介電層51包含一沈積 氧化物（例如，厚度約〇7微米）。導電層53隨後形成於第四 電層51上方，且包含（例如）n-型多晶矽（例如厚度約〇·3微 米）。保護層54形成於導電層53上方，且包含（例如）約〇15 微米之氮化石夕。 進行一光微影及蝕刻步驟以蝕刻過層54、53、5 1、48、 46及42之部分以提供開口 7〇。此亦形成一底座堆疊結構 56，其由層42、46、48、51、53及54之部分組成。在一例 不性實施例中，開口 70具有約5.0微米至約8.0微米左右的 寬度73。 圖5展示在用於形成介電間隔59之額外處理步驟之後的 裝置10的放大部分橫截面圖。在一例示性實施例中，一氮 化矽薄膜沈積於底座堆疊結構56及第一介電層41上方。以 實例說明之，使用化學氣相沈積技術來沈積約〇·1微米厚 H5962.doc 200820419 的氮化矽薄膜。接著，一習知各向異性回蝕步驟用於移除 底座堆疊結構56及第一介電層41上方的氮化矽層之部分， 同時留下底座堆疊結構56之側壁或垂直表面68上的氮化矽 層之部分以形成介電間隔59。 一氧化矽濕餘刻隨後用於移除開口 70内部之介電層41的 部分。以實例說明之，經稀釋之氫氟酸（例如，5〇: i)用於 蝕刻介電層41。在一例示性實施例中，延長蝕刻時間（例 如8至15分鐘）以便自介電間隔59下方自介電層41底切或移 除材料以形成凹進部分74。以此方式使介電層41凹進來確 保形成於主體區域31中之通道45(圖1所展示）延伸至層17中 以允許通道電流更有效地流動。在一例示性實施例中，在 介電間隔59下使得部分74凹進約〇·1微米的距離。一熱氧 化矽隨後在開口 70内部之主表面18上生長至約〇 〇8微米的 厚度以形成閘極介電層43。 圖6展示在進一步處理之後裝置1〇的放大部分橫截面 圖。一半導體材料之保形層沈積於裝置1〇上方至約〇1微 米至約0.15微米的厚度。隨後將硼摻雜物經由開口 7〇及半 導體材料之保形層引入至主表面18中以為主體區域31提供 P-型摻雜物。在一例示性實施例中，半導體材料之保形層 包含未摻雜之多晶矽，且將硼經由未摻雜之多晶矽植入至 層17中。約每平方公*h〇xl〇n個原子之離子植入劑量及 約160 KeV之植入能量適用於650伏特的裝置。在植入步驟 之後，一清潔步驟或蝕刻處理用於清潔半導體材料之保形 層的表面。 " 115962.doc -20- 200820419 半導體材料之第二保形層谴後沈積於第一保形層上方且 蝕刻該兩層以提供間隔閘極57。在一例示性實施例中，半 導體材料之第二保形層包含約0 8微米之卜型多晶矽，其可 在沈積製程期間摻雜或使用離子植入或其他摻雜技術來於 ik後摻雜。在形成間隔閘極57之後，將額外〇 〇15微米之 閘極介電（例如，氧化矽）添加至間隔閘極57的表面及閘極 氧化物43之暴露部分。 在一例示性實施例中，該蝕刻步驟暴露介電層54及介電 間隔59之上部部分。隨後蝕刻保護層54及介電間隔之上 部部分以便移除保護層54，且移除在間隔閘極57與導電層 53之間的介電間隔59之上部部分。 在另一步驟中，沈積導電材料（諸如多晶矽）以提供連接 導電部分77。連接導電部分77耦合或電連接間隔閘極刃至 導電層53。隨後進行一 n-型摻雜步驟以摻雜連接導電部分 77，且為源極區域33提供摻雜物。在一例示性實施例中， φ 每平方公分3·0Χ1015個原子之砷植入劑量以及80 KeV之植 入能量用於此摻雜步驟。 圖7展示在製造中其他步驟之後裝置1〇的放大部分橫截 面圖。沈積第五介電層61，且其包含（例如）約〇〇5微米之 氮化矽。ILD層62隨後沈積在第五介電層61上方。在一， 示性實施例中’ ILD層62包含一厚度約〇 8微米之沈積氧化 矽。一可選ILD錐形蝕刻用於几0層62之錐形部分“a，其 幫助隨後形成層之階梯覆蓋。 η 接著，-習知光微影及_步„於形成接觸開口 Η， 115962.doc .91- 200820419 接觸開口 81暴露主表面18的-部分。隨後使用一 P-型離子 植入步驛經由開口 81形成接觸區域36。以實例說明之，使 用每平^分3.0X，個原子之硼離子植人劑量及8〇 0 才月b里酼後沈積及蝕刻一保形間隔層以形成間隔 82。在—例示性實施例中，沈積及蚀刻0.3微米之氮化石夕 層以形成間隔82。此時使用—快速退火步驟以活化及擴散 各種離子植人物。舉例而言’將裝置1G暴露於攝氏 度之溫度下持續約45秒。 隨後一蝕刻步驟用於移除主表面18之一部分以形成凹進 部分84。此允許源極接觸層63與源極區域33及接觸區域刊 兩者接觸，如此將此等區域短接在一起。隨後移除間隔 82。在隨後的處理中，沈積及圖案化源極接觸層〇。隨後 視情況使基板12變薄，且沈積汲極接觸層66以提供圖乂中 所展示之結構。儘管未在圖2至圖7中展示，但一光微影及 蝕刻步驟在（例如）圖4至圖6中所描述之製造階段期間使用 以暴露導電層46之部分，以提供如圖丨所展示的將源極接 觸區域63耦合至導電層46之開口。應進一步瞭解，其他導 電層（諸如矽化物層）可在沈積源極接觸層63之前形成。 圖8為描繪根據本發明及根據本文所描述之處理參數的 裝置10之崩潰電壓（BVdss)特徵的曲線圖。如圖8所示，事 置1 〇展現了一自汲極至源極之約75〇伏特的標稱崩潰電 壓。此外且如圖8所示，裝置另外展示低於崩潰之低漏 電。 " 圖9為描繪根據本發明及根據本文所描述之處理表數的 115962.doc -22- 200820419 4置〇之開啟後電阻（Rd_)特徵的曲線圖。裝置ι〇展現 KMX β Vd_ ^況下與習知超接合裝置相比的極佳她〇n 特徵，其具有36毫歐姆/平方公分左右的典型Rdson值。 圖展示適用於根據本發明之裝置10之單元結構3 〇〇 的放大部分橫截面圖。將單元結構扇展示為具有一根據 本土月之實施例的填充溝渠322，填充溝渠似環繞其中 /成有效裝置或單兀之複數個多邊形的半導體層Μ區域 314。應瞭解’多邊形區域可具有圓角，且包括圓形、方 形、長方形或類似形狀之其他形狀為適合的。單元結構 3〇〇之-特徵為其提供一高填料密度，此改良了 ^議及電 流载運能力。根據本發明’填充溝渠322包括n_型層23、 本質層24及27及p-型層26。 圖11為裝置ίο之另一部分的放大部分橫截面圖，直展示 根據本發明之可選邊緣終止結構⑽。終止結構⑽之特徵 之-在於其倂入裝置10之基礎組件，此節省了處理成本。 終^结構_包括—形成於主表面18上方且鄰近主表面U 的v電接觸層或導電層146。在一例示性實施例中，導電 接觸層丨40包含與導電層46相同的材料，且I , 斑μ 1同日守形成0 舉例而a，導電接觸層包含ρ_型多 ^ ^ , ’在一熱處理 之後，Ρ-型摻雜物自導電接觸層146擴散 甘忙政从形成Ρ-型摻雜層 2，〜反摻雜η-型層17且耦合至可選卜型層19。圖丨丨另 展示經由開口 91耦合至源極接觸層63之邋 一 ’电接觸層146。 隔離溝渠1〇3形成於裝置10之周邊，且包含（例如）填 ’丨電材料1 〇8之經餘刻溝渠1 〇6。視需要，营 / 、 无形成一熱氧 115962.doc -23- 200820419 化層110以襯塾隔離溝渠103之側壁及/或下表面。 在曰代性實施例中且如圖11所示，隔離溝渠103另外 匕括半^體材料之層，該等層與填充溝渠22同時形成。以 貝例况明之，半導體材料之層包括如結合圖1所描述之n- 里層23本貝層或緩衝層24、P-型層26，及本質層或緩衝 ^ 若將半‘體材料之層排除在外，則在製造期間溝渠 106與填充溝渠22分離地形成。 在一例示性實施例中，介電材料1〇8包含一使用旋塗式 玻璃（SOG)、BPSG、削及mte〇s沈積技術所形成之氧 化石夕。在形成氧化物之後，使用回钕或化學機械平坦化技 術、其組合或其類似技術來平坦化介電區域之上表面。在 :例不性實施例中，溝渠106具有約30微米至約100微米之 寬度，且使用類似於用於形成結合圖2所描述之溝渠122之 技術來形成。溝渠106之侧壁可大體上為垂直的，或為錐 形的使得溝渠1〇6底部之寬度小於溝渠1〇6頂部之寬度。以 φ 實例說明之，如圖11所示，介電材料108及/或介電層110延 伸至半導體層14之下的深度或距離處。 在一替代性實施例中，當同時包括層23、24、26、27與 隔離溝渠103時，將一 η-型區域1〇9倂入至溝渠1〇6之下的 基板12中以減少與晶粒分離相關的任何漏電問題。 根據本發明，當導電層14包含ρ-型導電性時，Bvdssi 主接面為由半導體層丨4及η-型基板12所形成的卯接面 114。此特徵簡單化了邊緣終止結構1〇〇,且節省了空間。 舉例而言，習知裝置需要為終止結構磊晶層厚度之約1至 115962.doc -24- 200820419 [[3X]]i倍的距離。在本發明中，將此距離減少至約厚度的 [[1/2X]]—半。 在此實施例中，接面114比習知裝置中的更平坦，因為 該接面自基板12向上耗乏而非自主體區域31向下及跨越主 體區域31耗乏。此外，由於導電接觸層146經由摻雜區域 152及19耦合至半導體層14，因此接面橫向延伸至裝置 10之邊緣。以此方式，產生具有最佳BVdss的最佳平坦接 面。隔離溝渠103起到鈍化接面114的作用。 圖12展示根據本發明之一替代性隔離溝渠2〇3的放大部 分俯視圖。區域131表示用於如結合圖^所描述之終止結 構之裝置10的部分，且區域132表示用於如圖1所描述之有 效結構之裝置10的部分。隔離溝渠2〇3包括複數個柱體或 形狀117，或柱體或形狀丨丨7之矩陣，其在蝕刻隔離溝渠時 形成。在一例示性實施例中，形狀117之相鄰列如圖12所 展示相對於彼此偏移，使得形狀117大體上彼此等距。在 一例示性實施例中，將柱體117間隔開約5微米至約15微 米。 以實例說明之，形狀117為柱體或半導體材料主體^之 部分的區域。在一例示性實施例中，形狀丨17由基板12、 半導體層14、p-型層19、n-型層丨7及介電層41組成，且具 有約0.8微米至約ι·〇微米之寬度或直徑。在圖13中更清晰 地展示此情況，圖13為沿圖12之參考線13-13截取的隔離 溝渠203之一部分的放大橫截面圖。圖13展示在形成介電 材料208之前的隔離溝渠203。習知光微影及蝕刻技術用於 H5962.doc -25- 200820419 形成溝渠206及形狀117。舉例而言，〇11江與基於氟或氯之 化學組成一起使用。 在溝渠206及形狀117形成之後，如圖14所示，形成介電 層210。以實例說明之，介電層21〇包含一熱生長氧化矽。 接著，沈積及平坦化介電層208。在一例示性實施例中， 介電層208包含一旋塗式玻璃。根據本發明，當沈積介電 層208時，形狀117減少了表面凹陷效應，如此來提供更平 坦之表面、更佳的鈍化，及更可靠的裝置。形狀117可為 圓形、方形、長方形、多邊形、梯形、橢圓形、三角形、 其組合，或其類似物。形狀可進一步包括圓角。 圖15展示被描繪為藉由劃線柵格或區域461分離開之兩 個裝置之部分的相鄰或複數個隔離溝渠203a及203b的放大 部分橫截面圖。在此實施例中，一半導體晶圓上之相鄰裝 置10包括包含半導體材料主體11之劃線柵格461，而非相 鄰晶粒之間連續的介電材料208及210。如此允許一晶粒分 離裝置（諸如一切割機）沿中心線463分離該晶粒，此提供更 穩固之晶粒分離。 ® 16展示一電荷補償溝渠區域、深溝渠電荷補償區域、 電何補償填充溝渠或電荷補償區域122之一替代性實施例 的放大部分橫戴面圖。除了形成一介電層或鈍化層或襯層 171#為結構之最内層區域或核心外，電荷補償溝渠122類 Μ & /冓渠22。亦即，形成鈍化層m，使其覆蓋於溝渠區 /歲外蠢晶層（例如，層27)之上。 ^ 實施例中，襯層171經組態以補償、免除或克服在 115962.doc -26 - 200820419 最外猫晶生長層（例如，層27)形成時其中可 缺陷。特別要關注在最外層27填充 ：二 具有大的缺陷集中度。此等缺=生 ==力’或在某些應用中《不為所需之雜質，此 ==補償結構(例如’結構1❹)中產生不必要的導電 2路路徑。襯層171經組態以增加電荷補償結構之 的電阻，此防止在高電場或高溫下產生不 電流。Next, a third dielectric layer 48 is formed over the conductive layer 46, and a fourth dielectric layer 51 is formed over the third dielectric layer 48. The third dielectric layer 48 comprises, for example, a fossil (e.g., a thickness of about 0.05 microns), and the dielectric layer 51 comprises a deposited oxide (e.g., having a thickness of about 7 microns). Conductive layer 53 is then formed over fourth electrical layer 51 and comprises, for example, an n-type polysilicon (e.g., having a thickness of about 3 micrometers). A protective layer 54 is formed over the conductive layer 53 and comprises, for example, a nitride of about 15 microns. A photolithography and etching step is performed to etch portions of layers 54, 53, 5 1, 48, 46 and 42 to provide openings 7 . This also forms a base stack structure 56 which is comprised of portions of layers 42, 46, 48, 51, 53 and 54. In one embodiment, the opening 70 has a width 73 of from about 5.0 microns to about 8.0 microns. FIG. 5 shows an enlarged partial cross-sectional view of device 10 after additional processing steps for forming dielectric spacers 59. In an exemplary embodiment, a hafnium nitride film is deposited over the submount structure 56 and the first dielectric layer 41. By way of example, a chemical vapor deposition technique is used to deposit a tantalum nitride film of about 1 μm thick H5962.doc 200820419. Next, a conventional anisotropic etch back step is used to remove portions of the susceptor layer 56 above the pedestal stack structure 56 and the first dielectric layer 41 while leaving the sidewalls or vertical surfaces 68 of the pedestal stack structure 56. Portions of the tantalum nitride layer to form a dielectric spacer 59. The ruthenium oxide wet residue is then used to remove portions of the dielectric layer 41 inside the opening 70. By way of example, diluted hydrofluoric acid (e.g., 5 Å: i) is used to etch dielectric layer 41. In an exemplary embodiment, the etch time (e.g., 8 to 15 minutes) is extended to undercut or remove material from the dielectric layer 41 from below the dielectric spacer 59 to form the recessed portion 74. The dielectric layer 41 is recessed in this manner to ensure that the channels 45 (shown in Figure 1) formed in the body region 31 extend into the layer 17 to allow the channel current to flow more efficiently. In an exemplary embodiment, portion 74 is recessed at a distance of about 〇 1 μm under dielectric spacing 59. A thermal cerium oxide is then grown on the major surface 18 inside the opening 70 to a thickness of about 8 microns to form the gate dielectric layer 43. Figure 6 shows an enlarged partial cross-sectional view of the device 1〇 after further processing. A conformal layer of a semiconductor material is deposited over the device 1 to a thickness of from about 1 micrometer to about 0.15 micrometers. A boron dopant is then introduced into the major surface 18 via the opening 7 and a conformal layer of semiconductor material to provide a P-type dopant to the body region 31. In an exemplary embodiment, the conformal layer of semiconductor material comprises undoped polysilicon and boron is implanted into layer 17 via undoped polysilicon. An ion implantation dose of about *h〇xl〇n atoms and an implant energy of about 160 KeV are suitable for a 650 volt device. After the implantation step, a cleaning step or etching process is used to clean the surface of the conformal layer of the semiconductor material. " 115962.doc -20- 200820419 A second conformal layer of semiconductor material is deposited over the first conformal layer and etched to provide a spacer gate 57. In an exemplary embodiment, the second conformal layer of semiconductor material comprises a polymorph of about 0.8 microns, which may be doped during the deposition process or doped using ion implantation or other doping techniques. . After the spacer gate 57 is formed, an additional 15 μm gate dielectric (e.g., hafnium oxide) is added to the surface of the spacer gate 57 and the exposed portion of the gate oxide 43. In an exemplary embodiment, the etching step exposes the dielectric layer 54 and the upper portion of the dielectric spacer 59. The protective layer 54 and the upper portion of the dielectric spacer are then etched to remove the protective layer 54 and the upper portion of the dielectric spacer 59 between the spacer gate 57 and the conductive layer 53 is removed. In another step, a conductive material such as polysilicon is deposited to provide a connection conductive portion 77. The connecting conductive portion 77 is coupled or electrically connected to the gate electrode to the conductive layer 53. An n-type doping step is then performed to dope the connection conductive portion 77 and provide dopants for the source region 33. In an exemplary embodiment, an arsenic implant dose of φ 3·0 Χ 1015 atoms per square centimeter and an implant energy of 80 KeV are used for this doping step. Figure 7 shows an enlarged partial cross-sectional view of the device 1〇 after other steps in manufacturing. A fifth dielectric layer 61 is deposited and contains, for example, tantalum nitride of about 5 microns. The ILD layer 62 is then deposited over the fifth dielectric layer 61. In one illustrative embodiment, the ILD layer 62 comprises a deposited yttria having a thickness of about 8 microns. An optional ILD taper etch is used for the tapered portion "a of the 0 layer 62, which aids in the subsequent formation of the step coverage of the layer. η Next, - the conventional photolithography and the _ step „ in the formation of the contact opening Η, 115962.doc. 91- 200820419 The contact opening 81 exposes a portion of the major surface 18. Contact region 36 is then formed via opening 81 using a P-type ion implantation step. By way of example, a conformal spacer layer is deposited and etched to form a space 82 by using a 3.0X per square meter atomic boron ion implantation dose and an 8 Å 0 month. In an exemplary embodiment, a 0.3 micron layer of nitride nitride is deposited and etched to form a space 82. At this point, a rapid annealing step is used to activate and diffuse various ion implants. For example, device 1G is exposed to a temperature of Celsius for about 45 seconds. An etching step is then used to remove a portion of the major surface 18 to form the recessed portion 84. This allows the source contact layer 63 to be in contact with both the source region 33 and the contact region so that the regions are shorted together. The interval 82 is then removed. In a subsequent process, the source contact layer is deposited and patterned. Substrate 12 is then thinned as appropriate, and a drain contact layer 66 is deposited to provide the structure shown in the figure. Although not shown in FIGS. 2-7, a photolithography and etching step is used during the fabrication stages described, for example, in FIGS. 4-6 to expose portions of conductive layer 46 to provide an The source contact region 63 is shown coupled to the opening of the conductive layer 46. It should be further appreciated that other conductive layers, such as a germanide layer, may be formed prior to deposition of the source contact layer 63. Figure 8 is a graph depicting the breakdown voltage (BVdss) characteristics of device 10 in accordance with the present invention and processing parameters as described herein. As shown in Figure 8, event 1 shows a nominal collapse voltage of approximately 75 volts from the drain to the source. In addition and as shown in Figure 8, the device additionally exhibits low leakage below collapse. " Figure 9 is a graph depicting the post-opening resistance (Rd_) characteristics of 115962.doc -22-200820419 4 according to the present invention and according to the number of processing tables described herein. The device 〇 exhibits an excellent her 〇n characteristic compared to the conventional super-engaging device under KMX β Vd_^, which has a typical Rdson value of about 36 milliohms/square centimeter. The figure shows an enlarged partial cross-sectional view of a unitary structure 3 适用 suitable for use in a device 10 according to the invention. The unit structure fan is shown as having a fill trench 322 according to an embodiment of the native month, the fill trench being like a semiconductor layer region 314 surrounding a plurality of polygons of the active device or unit. It should be understood that the 'polygon region' may have rounded corners, and other shapes including circles, squares, rectangles, or the like are suitable. The cell structure is characterized by a high packing density which improves the current and current carrying capacity. The filled trench 322 includes an n-type layer 23, an intrinsic layer 24 and 27, and a p-type layer 26 in accordance with the present invention. Figure 11 is an enlarged partial cross-sectional view of another portion of the device ίο showing the optional edge termination structure (10) in accordance with the present invention. The termination structure (10) is characterized in that it breaks into the basic components of the device 10, which saves processing costs. The final structure _ includes a v electrical contact layer or conductive layer 146 formed over the major surface 18 and adjacent to the major surface U. In an exemplary embodiment, the conductive contact layer 40 includes the same material as the conductive layer 46, and I, the spot μ1 is formed by the same day as 0, and the conductive contact layer contains the ρ_type, ^, After the heat treatment, the Ρ-type dopant diffuses from the conductive contact layer 146 and forms a Ρ-type doped layer 2, a counter-doped η-type layer 17 and is coupled to the optional pad layer 19. The figure further shows an electrical contact layer 146 coupled to the source contact layer 63 via opening 91. An isolation trench 1〇3 is formed at the periphery of the device 10 and includes, for example, a residual trench 1 〇6 filled with the electrical material 1 〇8. If necessary, battalion / no thermal oxygen is formed 115962.doc -23- 200820419 The layer 110 is used to isolate the sidewalls and/or the lower surface of the trench 103. In a degenerate embodiment and as shown in Figure 11, the isolation trench 103 additionally includes a layer of semi-material, which is formed simultaneously with the filled trench 22. In the case of the case, the layer of the semiconductor material comprises the n-inner layer 23 of the shell layer or buffer layer 24, the p-type layer 26 as described in connection with FIG. 1, and the intrinsic layer or buffer. The layers are excluded, and the trenches 106 are formed separately from the filled trenches 22 during manufacture. In an exemplary embodiment, dielectric material 1 包含 8 comprises a oxidized oxide formed using spin-on glass (SOG), BPSG, and mte〇s deposition techniques. After the oxide is formed, the surface above the dielectric region is planarized using a retrograde or chemical mechanical planarization technique, a combination thereof, or the like. In an exemplary embodiment, the trench 106 has a width of from about 30 microns to about 100 microns and is formed using techniques similar to those used to form the trench 122 described in connection with FIG. The side walls of the trench 106 may be substantially vertical or tapered such that the width of the bottom of the trench 1〇6 is less than the width of the top of the trench 1〇6. As illustrated by the φ example, as shown in FIG. 11, dielectric material 108 and/or dielectric layer 110 extends to a depth or distance below semiconductor layer 14. In an alternative embodiment, when the layers 23, 24, 26, 27 and the isolation trench 103 are simultaneously included, an n-type region 1〇9 is inserted into the substrate 12 below the trench 1〇6 to reduce Any leakage problems related to grain separation. According to the present invention, when the conductive layer 14 contains p-type conductivity, the Bvdssi main junction is the splicing surface 114 formed by the semiconductor layer 丨4 and the η-type substrate 12. This feature simplifies the edge termination structure and saves space. For example, conventional devices are required to terminate the thickness of the epitaxial layer of the structure by a distance of about 1 to 115962.doc -24 - 200820419 [[3X]]i times. In the present invention, this distance is reduced to about [[1/2X]] - half of the thickness. In this embodiment, the junction 114 is flatter than in conventional devices because the junction is depleted from the substrate 12 and is not depleted from the body region 31 down and across the body region 31. Moreover, since the conductive contact layer 146 is coupled to the semiconductor layer 14 via the doped regions 152 and 19, the junction extends laterally to the edge of the device 10. In this way, the best flat interface with the best BVdss is produced. The isolation trench 103 functions as a passivation junction 114. Figure 12 shows an enlarged plan view of an alternative isolation trench 2〇3 in accordance with one embodiment of the present invention. Region 131 represents the portion of device 10 for the termination structure as described in connection with FIG. 2, and region 132 represents the portion of device 10 for the effective structure as described in FIG. The isolation trench 2〇3 includes a plurality of pillars or shapes 117, or a matrix of pillars or shapes 丨丨7 that are formed when the isolation trench is etched. In an exemplary embodiment, adjacent columns of shapes 117 are offset relative to one another as shown in Figure 12 such that the shapes 117 are generally equidistant from one another. In an exemplary embodiment, the posts 117 are spaced apart from about 5 microns to about 15 microns. By way of example, shape 117 is the area of the pillar or portion of the semiconductor material body ^. In an exemplary embodiment, the shape 丨 17 is composed of a substrate 12, a semiconductor layer 14, a p-type layer 19, an n-type layer 丨7, and a dielectric layer 41, and has a thickness of about 0.8 μm to about 1 μm. Width or diameter. This is more clearly shown in Figure 13, which is an enlarged cross-sectional view of a portion of the isolation trench 203 taken along reference line 13-13 of Figure 12. Figure 13 shows the isolation trench 203 prior to forming the dielectric material 208. Conventional photolithography and etching techniques are used for H5962.doc -25- 200820419 to form trenches 206 and shapes 117. For example, the 〇11 River is used with a chemical composition based on fluorine or chlorine. After the trench 206 and the shape 117 are formed, as shown in Fig. 14, a dielectric layer 210 is formed. By way of example, the dielectric layer 21A contains a thermally grown yttrium oxide. Next, the dielectric layer 208 is deposited and planarized. In an exemplary embodiment, dielectric layer 208 comprises a spin-on glass. In accordance with the present invention, shape 117 reduces surface dishing effects when dielectric layer 208 is deposited, thereby providing a more flat surface, better passivation, and a more reliable device. Shape 117 can be circular, square, rectangular, polygonal, trapezoidal, elliptical, triangular, combinations thereof, or the like. The shape may further include rounded corners. Figure 15 shows an enlarged partial cross-sectional view of adjacent or plural isolation trenches 203a and 203b depicted as portions of two devices separated by a scribe grid or region 461. In this embodiment, adjacent device 10 on a semiconductor wafer includes a scribe grid 461 comprising a body 11 of semiconductor material, rather than a continuous dielectric material 208 and 210 between adjacent dies. This allows a die separation device, such as a cutter, to separate the die along centerline 463, which provides for a more robust die separation. The ® 16 shows an enlarged partial cross-sectional view of an alternative embodiment of a charge compensation trench region, a deep trench charge compensation region, an electrical compensation fill trench or a charge compensation region 122. In addition to forming a dielectric layer or passivation layer or liner 171# as the innermost layer region or core of the structure, the charge compensation trenches 122 are Μ & / trenches 22. That is, the passivation layer m is formed to cover over the trench region/out-of-year layer (e.g., layer 27). In the embodiment, the liner 171 is configured to compensate, dispense with, or overcome defects in the formation of the outermost cat crystal growth layer (e.g., layer 27) at 115962.doc -26 - 200820419. Special attention should be paid to filling the outermost layer 27: two with large defect concentration. These missing = raw == force' or in some applications "not the desired impurity, this == compensation structure (eg 'structure 1❹) produces an unnecessary conductive 2-way path. Liner 171 is configured to increase the electrical resistance of the charge compensation structure, which prevents non-current generation at high electric fields or high temperatures.
襯層171包含(例如)氧化物、氣化物或氧化物及氮化物之 組合。在一實施例中’襯層171包含一乾氧化物。在一實 施例中，在形成襯層m之前使用一習知預擴散清潔步 圖π展示一電荷補償溝渠區域、深溝渠電荷補償區域、 電荷補償填充溝渠或電荷補償區域222之—替代性實施例 的放大部分橫截面圖。除了形成留有縫隙、空隙或氣隙 272的介電層或鈍化層或襯層271作為結構之最内層區域或 核心外’電荷補償溝渠222類似於溝渠122。在一實施例 中，如圖17所示，縫隙272自主表面18延伸至半導體層14 中。在一替代性實施例中，縫隙272僅佔據核心的一部 分0 總之’已描述具有深溝渠電荷補償之新型開關裝置结 構，包括製造方法。亦已描述一適用於本發明之裝置以及 其他半導體裝置的接地平面結構。此外，已描述適用於本 發明之裝置以及其他半導體裝置的邊緣終止結構。 115962.doc -27- 200820419 儘官已參考本發明之特定實施例描述及說明了本發明， 但本發明不應限於此等說明性實施例。熟習此項技術者將 識到可進行修改及變動而不脫離本發明之精神。因此， 期望本發明包含屬於所附專利中請範圍之所有此等變化及 修改。 【圖式簡單說明】 圖1說明根據本發明之一開關裝置的放大部分橫截面 圖； 圖2至圖7說明各製造階段中圖i之開關裝置的放大部分 橫截面圖； 圖8為展示用於圖1之開關裝置之崩潰電壓特徵的曲線 圖； 圖9為展示用於圖1之開關裝置之開啟後電阻特徵的曲線 圖； 圖10說明適用於根據本發明之一開關裝置之單元結構的 放大部分俯視圖； 圖11說明根據本發明之一開關裝置及邊緣終止結構的放 大部分橫截面圖； 圖12說明根據本發明之一替代性溝渠隔離結構的放大部 分俯視圖； 圖13說明在製造之早期階段沿參考線13-13截取的圖12 之溝渠隔離結構之放大部分橫截面圖； 圖14說明進一步處理之後圖13之結構的放大部分橫截面 圖； 115962.doc -28- 200820419 圖15說明根據本發明之另 截面圖； 一溝渠隔離結構的 A大部分橫 圖16說明一電荷補償溝渠結構之一替代性實施例的放大 部分橫截面圖；及 圖17說明一電荷補償溝渠結構之另一實施例的放大部分 橫截面圖。 【主要元件符號說明】Liner 171 comprises, for example, an oxide, a vapor or a combination of oxides and nitrides. In one embodiment, the liner 171 comprises a dry oxide. In one embodiment, a conventional charge pre-diffusion cleaning pattern π is used to display a charge compensation trench region, a deep trench charge compensation region, a charge compensation fill trench or a charge compensation region 222 prior to forming the liner m - an alternative embodiment A magnified partial cross-sectional view. The charge compensation trench 222 is similar to the trench 122 except that a dielectric layer or passivation layer or liner 271 leaving a gap, void or air gap 272 is formed as the innermost layer region or core of the structure. In one embodiment, as shown in FIG. 17, slit 272 autonomous surface 18 extends into semiconductor layer 14. In an alternative embodiment, slot 272 occupies only a portion of the core. In summary, a novel switching device structure with deep trench charge compensation has been described, including a method of fabrication. A ground plane structure suitable for use in the apparatus of the present invention, as well as other semiconductor devices, has also been described. Furthermore, edge termination structures suitable for use in the apparatus of the present invention, as well as other semiconductor devices, have been described. The invention has been described and illustrated with reference to the particular embodiments of the invention, but the invention should not be construed as limited. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that the present invention include all such changes and modifications as fall within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing an enlarged portion of a switch device according to the present invention; and FIGS. 2 to 7 are enlarged cross-sectional views showing a switch device of FIG. Figure 7 is a graph showing the characteristics of the breakdown voltage of the switching device of Figure 1; Figure 9 is a graph showing the characteristics of the resistor for the opening of the switching device of Figure 1; Figure 10 is a diagram showing the structure of a unit suitable for use in a switching device according to the present invention. Figure 11 illustrates an enlarged partial cross-sectional view of a switchgear and edge termination structure in accordance with the present invention; Figure 12 illustrates an enlarged partial plan view of an alternative trench isolation structure in accordance with the present invention; A cross-sectional view of an enlarged portion of the trench isolation structure of FIG. 12 taken along the reference line 13-13; FIG. 14 illustrates an enlarged partial cross-sectional view of the structure of FIG. 13 after further processing; 115962.doc -28-200820419 FIG. A further cross-sectional view of the present invention; a majority of the cross-sectional view 16 of a trench isolation structure illustrates an alternative embodiment of a charge compensation trench structure Partial cross sectional view; and FIG. 17 illustrates another structure of a charge compensation trench embodiment enlarged partial cross sectional view of the embodiment. [Main component symbol description]
10 開關裝置 11 半導體材料主體 12 η-型矽基板 14 半導體層 17 η-型區域 18 主表面 19 Ρ-型區域 22 填充溝渠 23 η-型層 24 本質層/緩衝層 26 ρ-型層 27 本質層/緩衝層 31 主體區域 33 η-型源極區域 36 接觸區域 40 介電層 41 第一介電層 115962.doc -29- 20082041910 Switching device 11 Semiconductor material body 12 η-type 矽 substrate 14 Semiconductor layer 17 η-type region 18 Main surface 19 Ρ-type region 22 Filling trench 23 η-type layer 24 Intrinsic layer / buffer layer 26 ρ-type layer 27 Essential Layer/buffer layer 31 body region 33 n-type source region 36 contact region 40 dielectric layer 41 first dielectric layer 115962.doc -29- 200820419
42 第二介電層 43 閘極介電層 45 通道 46 導電接觸層 47 開口 48 第三介電層 49 開口 47之寬度 51 第四介電層 52 P-型摻雜區域 53 導電層 54 保護層 56 底座堆璺結構 57 間隔閘極區域 58 控制電極 59 介電間隔 61 第五介電層 62 層間介電層 62a 層62之錐形部分 63 源極接觸層 66 汲極接觸層 68 垂直表面 70 開口 71 遮罩層 72 開口 115962.doc -30- 200820419 73 開口 70之寬度 74 凹進部分 77 導電連接部分 81 開口 82 間隔 84 凹進部分 91 開口 100 邊緣終止結構 103 隔離溝渠 106 經蝕刻溝渠 108 介電材料 109 η-型區域 110 介電層/熱氧化層 114 ρη接面 117 柱體 122 電荷補償溝渠 131 區域 132 區域 146 導電層 152 Ρ-型摻雜層 171 介電層/鈍化層/襯層 203 隔離溝渠 203a 隔離溝渠 203b 隔離溝渠 -31- 115962.doc 200820419 206 溝渠 208 介電層 210 介電層 222 電荷補償區域 271 介電層/鈍化層/襯層 272 缝隙/空隙/氣隙 3 00 單元結構 314 多邊形區域 322 填充溝渠 461 劃線拇格 463 中心線 115962.doc -32-42 second dielectric layer 43 gate dielectric layer 45 channel 46 conductive contact layer 47 opening 48 third dielectric layer 49 width 47 of opening 51 fourth dielectric layer 52 P-type doped region 53 conductive layer 54 protective layer 56 base stacking structure 57 spaced gate region 58 control electrode 59 dielectric spacer 61 fifth dielectric layer 62 interlayer dielectric layer 62a layer 62 tapered portion 63 source contact layer 66 drain contact layer 68 vertical surface 70 opening 71 Mask layer 72 Opening 115962.doc -30- 200820419 73 Width 74 of opening 70 Recessed portion 77 Conductive connection portion 81 Opening 82 Space 84 Recessed portion 91 Opening 100 Edge termination structure 103 Isolation trench 106 Dielectric through etching trench 108 Material 109 η-type region 110 dielectric layer/thermal oxide layer 114 ρη junction 117 pillar 122 charge compensation trench 131 region 132 region 146 conductive layer 152 germanium-type doped layer 171 dielectric layer/passivation layer/liner 203 Isolation trench 203a Isolation trench 203b Isolation trench -31- 115962.doc 200820419 206 Ditch 208 Dielectric layer 210 Dielectric layer 222 Charge compensation region 271 Dielectric Layer/passivation layer/liner 272 slit/void/air gap 3 00 unit structure 314 polygonal area 322 filled trench 461 lined thumb 463 center line 115962.doc -32-