TW200739583A - A latency control circuit, and method thereof and an auto-precharge control circuit and method thereof - Google Patents
A latency control circuit, and method thereof and an auto-precharge control circuit and method thereofInfo
- Publication number
- TW200739583A TW200739583A TW095142111A TW95142111A TW200739583A TW 200739583 A TW200739583 A TW 200739583A TW 095142111 A TW095142111 A TW 095142111A TW 95142111 A TW95142111 A TW 95142111A TW 200739583 A TW200739583 A TW 200739583A
- Authority
- TW
- Taiwan
- Prior art keywords
- signal
- control circuit
- precharge
- auto
- signals
- Prior art date
Links
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- Dram (AREA)
Abstract
A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20050111027 | 2005-11-19 | ||
KR1020060039897A KR100736397B1 (en) | 2006-05-03 | 2006-05-03 | Auto precharge control circuit and semiconductor memory device having the auto precharge control circuit |
KR1020060063463A KR100818720B1 (en) | 2005-11-19 | 2006-07-06 | Latency control circuit of semiconductor memory device, method there-of and semiconductor memory device having the latency control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200739583A true TW200739583A (en) | 2007-10-16 |
Family
ID=46497835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095142111A TW200739583A (en) | 2005-11-19 | 2006-11-14 | A latency control circuit, and method thereof and an auto-precharge control circuit and method thereof |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2012113819A (en) |
TW (1) | TW200739583A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI418987B (en) * | 2008-06-30 | 2013-12-11 | Intel Corp | Memory throughput increase via fine granularity of precharge management |
TWI845651B (en) * | 2019-11-18 | 2024-06-21 | 韓商愛思開海力士有限公司 | Semiconductor devices |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102576763B1 (en) * | 2016-03-17 | 2023-09-12 | 에스케이하이닉스 주식회사 | Semiconductor device |
US11687281B2 (en) * | 2021-03-31 | 2023-06-27 | Advanced Micro Devices, Inc. | DRAM command streak efficiency management |
-
2006
- 2006-11-14 TW TW095142111A patent/TW200739583A/en unknown
-
2012
- 2012-03-19 JP JP2012061805A patent/JP2012113819A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI418987B (en) * | 2008-06-30 | 2013-12-11 | Intel Corp | Memory throughput increase via fine granularity of precharge management |
TWI845651B (en) * | 2019-11-18 | 2024-06-21 | 韓商愛思開海力士有限公司 | Semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
JP2012113819A (en) | 2012-06-14 |
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