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TW200735175A - Integrated circuit fabrication - Google Patents

Integrated circuit fabrication

Info

Publication number
TW200735175A
TW200735175A TW095108884A TW95108884A TW200735175A TW 200735175 A TW200735175 A TW 200735175A TW 095108884 A TW095108884 A TW 095108884A TW 95108884 A TW95108884 A TW 95108884A TW 200735175 A TW200735175 A TW 200735175A
Authority
TW
Taiwan
Prior art keywords
features
integrated circuit
masking layer
substrate
lower masking
Prior art date
Application number
TW095108884A
Other languages
Chinese (zh)
Other versions
TWI309437B (en
Inventor
Luan C Tran
John Lee
Zeng-Tao Tony Liu
Eric Freeman
Russell Nielsen
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200735175A publication Critical patent/TW200735175A/en
Application granted granted Critical
Publication of TWI309437B publication Critical patent/TWI309437B/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

A method for defining patterns in an integrated circuit (100) comprises defining a plurality of features in a first photoresist layer using photolithography over a first region (102) of a substrate (108). The method further comprises using pitch multiplication to produce at least two features (120) in a lower masking layer (116) for each feature in the photoresist layer. The features in the lower masking layer (116) include looped ends (124). The method further comprises covering with a second photoresist layer (126) a second region (104) of the substrate (108) including the looped ends (124) in the lower masking layer (116). The method further comprises etching a pattern of trenches in the substrate (108) through the features in the lower masking layer without etching in the second region (104). The trenches have a trench width.
TW95108884A 2005-03-28 2006-03-16 Integrated circuit fabrication TWI309437B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66603105P 2005-03-28 2005-03-28

Publications (2)

Publication Number Publication Date
TW200735175A true TW200735175A (en) 2007-09-16
TWI309437B TWI309437B (en) 2009-05-01

Family

ID=39251306

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95108884A TWI309437B (en) 2005-03-28 2006-03-16 Integrated circuit fabrication

Country Status (2)

Country Link
CN (1) CN100555579C (en)
TW (1) TWI309437B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI484539B (en) * 2010-12-24 2015-05-11 Asahi Kasei E Materials Corp Insulating structure and manufacturing method thereof
US9666695B2 (en) 2007-12-18 2017-05-30 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101736983B1 (en) * 2010-06-28 2017-05-18 삼성전자 주식회사 Semiconductor device and method of forming patterns for semiconductor device
US9524878B2 (en) * 2014-10-02 2016-12-20 Macronix International Co., Ltd. Line layout and method of spacer self-aligned quadruple patterning for the same
US9818623B2 (en) * 2016-03-22 2017-11-14 Globalfoundries Inc. Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
CN110828460B (en) * 2018-08-14 2022-07-19 中芯国际集成电路制造(北京)有限公司 Semiconductor device and method of forming the same
KR102699634B1 (en) 2019-07-16 2024-08-28 양쯔 메모리 테크놀로지스 씨오., 엘티디. Self-aligning contacts in three-dimensional memory devices and their formation method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9666695B2 (en) 2007-12-18 2017-05-30 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US9941155B2 (en) 2007-12-18 2018-04-10 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US10497611B2 (en) 2007-12-18 2019-12-03 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
TWI484539B (en) * 2010-12-24 2015-05-11 Asahi Kasei E Materials Corp Insulating structure and manufacturing method thereof

Also Published As

Publication number Publication date
CN100555579C (en) 2009-10-28
CN101151720A (en) 2008-03-26
TWI309437B (en) 2009-05-01

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