[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TW200711061A - Method of manufacturing quad flat non-leaded semiconductor package - Google Patents

Method of manufacturing quad flat non-leaded semiconductor package

Info

Publication number
TW200711061A
TW200711061A TW094131778A TW94131778A TW200711061A TW 200711061 A TW200711061 A TW 200711061A TW 094131778 A TW094131778 A TW 094131778A TW 94131778 A TW94131778 A TW 94131778A TW 200711061 A TW200711061 A TW 200711061A
Authority
TW
Taiwan
Prior art keywords
metal plate
conductive pads
resist layers
metal
plating layer
Prior art date
Application number
TW094131778A
Other languages
English (en)
Other versions
TWI264091B (en
Inventor
Chun-Yuan Li
Fu-Di Tang
Chien-Ping Huang
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW094131778A priority Critical patent/TWI264091B/zh
Priority to US11/486,569 priority patent/US20070059863A1/en
Application granted granted Critical
Publication of TWI264091B publication Critical patent/TWI264091B/zh
Publication of TW200711061A publication Critical patent/TW200711061A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
TW094131778A 2005-09-15 2005-09-15 Method of manufacturing quad flat non-leaded semiconductor package TWI264091B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094131778A TWI264091B (en) 2005-09-15 2005-09-15 Method of manufacturing quad flat non-leaded semiconductor package
US11/486,569 US20070059863A1 (en) 2005-09-15 2006-07-14 Method of manufacturing quad flat non-leaded semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094131778A TWI264091B (en) 2005-09-15 2005-09-15 Method of manufacturing quad flat non-leaded semiconductor package

Publications (2)

Publication Number Publication Date
TWI264091B TWI264091B (en) 2006-10-11
TW200711061A true TW200711061A (en) 2007-03-16

Family

ID=37855710

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094131778A TWI264091B (en) 2005-09-15 2005-09-15 Method of manufacturing quad flat non-leaded semiconductor package

Country Status (2)

Country Link
US (1) US20070059863A1 (zh)
TW (1) TWI264091B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102142401A (zh) * 2009-12-01 2011-08-03 英飞凌科技股份有限公司 层压电子器件
TWI469289B (zh) * 2009-12-31 2015-01-11 矽品精密工業股份有限公司 半導體封裝結構及其製法
TWI474455B (zh) * 2008-08-21 2015-02-21 Advanced Semiconductor Eng 先進四方扁平無引腳封裝結構

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241890B (zh) * 2007-02-06 2012-05-23 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
CN100539054C (zh) * 2007-03-13 2009-09-09 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
US8120152B2 (en) * 2008-03-14 2012-02-21 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US20100078831A1 (en) * 2008-09-26 2010-04-01 Jairus Legaspi Pisigan Integrated circuit package system with singulation process
US8288207B2 (en) * 2009-02-13 2012-10-16 Infineon Technologies Ag Method of manufacturing semiconductor devices
US7858443B2 (en) * 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8334584B2 (en) * 2009-09-18 2012-12-18 Stats Chippac Ltd. Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof
US8241965B2 (en) * 2009-10-01 2012-08-14 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
US8420508B2 (en) * 2010-03-17 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with bump contact on package leads and method of manufacture thereof
US8389330B2 (en) 2010-06-24 2013-03-05 Stats Chippac Ltd. Integrated circuit package system with package stand-off and method of manufacture thereof
US8669654B2 (en) 2010-08-03 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with die paddle and method of manufacture thereof
US8435835B2 (en) * 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
TWI420630B (zh) 2010-09-14 2013-12-21 Advanced Semiconductor Eng 半導體封裝結構與半導體封裝製程
TWI419290B (zh) 2010-10-29 2013-12-11 Advanced Semiconductor Eng 四方扁平無引腳封裝及其製作方法
US8420448B2 (en) 2011-03-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with pads and method of manufacture thereof
US8502363B2 (en) 2011-07-06 2013-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with solder joint enhancement element and related methods
US8674487B2 (en) 2012-03-15 2014-03-18 Advanced Semiconductor Engineering, Inc. Semiconductor packages with lead extensions and related methods
US9653656B2 (en) 2012-03-16 2017-05-16 Advanced Semiconductor Engineering, Inc. LED packages and related methods
US9059379B2 (en) 2012-10-29 2015-06-16 Advanced Semiconductor Engineering, Inc. Light-emitting semiconductor packages and related methods
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
JP6608672B2 (ja) * 2015-10-30 2019-11-20 新光電気工業株式会社 半導体装置及びその製造方法、リードフレーム及びその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI474455B (zh) * 2008-08-21 2015-02-21 Advanced Semiconductor Eng 先進四方扁平無引腳封裝結構
CN102142401A (zh) * 2009-12-01 2011-08-03 英飞凌科技股份有限公司 层压电子器件
TWI469289B (zh) * 2009-12-31 2015-01-11 矽品精密工業股份有限公司 半導體封裝結構及其製法

Also Published As

Publication number Publication date
US20070059863A1 (en) 2007-03-15
TWI264091B (en) 2006-10-11

Similar Documents

Publication Publication Date Title
TW200711061A (en) Method of manufacturing quad flat non-leaded semiconductor package
CN105144367B (zh) 半导体器件和制造半导体器件的方法
US9627303B2 (en) Etching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with chip, and technological method
US7972906B2 (en) Semiconductor die package including exposed connections
CN103824836B (zh) 半导体承载元件及半导体封装件
WO2015018145A1 (zh) 先封后蚀芯片倒装三维系统级金属线路板结构及工艺方法
JP2014526793A (ja) 島プレパック成形化合物でリードフレーム構造を順次エッチングおよびめっき及びその製造方法
TWI268564B (en) Semiconductor device and fabrication method thereof
US8114713B2 (en) Method of manufacturing a lead frame with a nickel coating
US9659842B2 (en) Methods of fabricating QFN semiconductor package and metal plate
US20080174981A1 (en) Pre-molded lead frame and process for manufacturing the same
TW202414751A (zh) 電子封裝件之製法及其承載結構
WO2013097580A1 (zh) 一种芯片上芯片封装及制造方法
US20130329386A1 (en) Package carrier and manufacturing method thereof
KR101001876B1 (ko) 반도체 패키지용 다열 리드리스 프레임 및 이를 이용한 반도체 패키지의 제조방법
CN114883201A (zh) Aqfn制造方法
CN107086182B (zh) 一种低成本的智能芯片载带以及制造方法
TWI842404B (zh) 電子封裝件之製法及其承載結構
KR101358637B1 (ko) 두께를 얇게 할 수 있는 반도체 패키지 제조방법
KR20130113795A (ko) 실리콘 기판을 이용한 반도체 패키지 제조방법
CN103824820A (zh) 引线框区域阵列封装技术
KR101187913B1 (ko) 반도체 패키지용 리이드 프레임과, 이를 제조하는 방법
TW202435403A (zh) 電子封裝件之製法及其承載結構
KR101384343B1 (ko) 칩 패드가 없는 반도체 패키지 제조방법
CN1459838A (zh) 利用叠构式光阻影像转移的封装用载板制程