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TW200421567A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW200421567A
TW200421567A TW092108566A TW92108566A TW200421567A TW 200421567 A TW200421567 A TW 200421567A TW 092108566 A TW092108566 A TW 092108566A TW 92108566 A TW92108566 A TW 92108566A TW 200421567 A TW200421567 A TW 200421567A
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TW
Taiwan
Prior art keywords
mounting
packaging substrate
semiconductor device
recessed portion
electrode
Prior art date
Application number
TW092108566A
Other languages
Chinese (zh)
Inventor
Mikio Negishi
Hiroki Noto
Satoru Konishi
Tomio Yamada
Original Assignee
Renesas Tech Corp
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Publication date
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Publication of TW200421567A publication Critical patent/TW200421567A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention provides a semiconductor device (power amplifier module), which carries a plurality of semiconductor chips (the first mounting components) on the packaging substrate, and a plurality of chip components composed of resistors or capacitors; wherein, the surface of the packaging substrate is formed with a multi-level recess, and the bottom of the lower recess is carried and configured with semiconductor chips with transistors having large heat dissipation; and, a grounding layer (conductor layer) electrically connected to the back of the packaging substrate through the conductor filled in the via with the function of heat dissipation body; and, the upper recess is carried and configured with the control circuit or the transistors with the first amplifying level, the semiconductor chips with low heat dissipation, and the wiring providing specific connection of each electrode, so that the upper surface of the upper semiconductor chip has the same height as the surface (upper surface) of the packaging substrate, and carries the chip components around the upper surface of the upper semiconductor chip and the upper surface of the packaging substrate.

Description

200421567 Ο) 玖、發明說明 【發明所屬之技術領域】 本發明是關於半導體裝置’特別是關於’應用在配線 基板的表面成多層次方式重疊搭載半導體晶片’同時搭載 被動零件的架構之半導體模組時，很有效的技術。 【先前技術】 習知的高頻積體電路裝置，是分別在配線基板搭載： 裝配電晶體等主動元件的半導體晶片（第1安裝零件）；及 裝配電阻器或電容器等被動元件構成的晶片零件（第2安 裝零件）的半導體裝置（半導體模組）的一個例子。此高頻 積體電路裝置被使用在’例如’處理行動通信等各種通信 機器的高頻帶信號。 高頻積體電路裝置的一個例子，其架構是，具有：堆 疊複數個介電體層的多層基板；安裝在多層基板表面的半 導體晶片及晶片零件；設在多層基板表面的相反側的電子 機器之安裝面的開口部內的半導體晶片；圍繞多層基板的 周圍，同時直接接觸在安裝於多層基板表面的半導體晶片 表面，具有電磁遮蔽功能的電磁遮蔽罩；安裝在開口部的 半導體晶片下面的散熱板；設在多層基板的安裝面，用以 裝設到電子機器的電極。而在電磁遮蔽罩之端部形成有將 電磁遮蔽罩安裝到電子機器時的安裝部。（參照，例如： 專利文獻1)。 〔專利文獻1〕 -6- (2) (2)200421567 日本特開2000 - 299427號公報（第4 - 6頁， 第1圖） 攜帶式電話機用功率放大模組（亦稱作PA)，正在快 速小型·高功能化。通信方式之一有習知的GSM(Global S y s t e m Μ 〇 b i 1 e C 〇 m m u n i c a t i 〇 n )方式，此 G S Μ 方式的功率 放大模組的外形尺寸在目前是縱10 mm、橫8 mm的大 小，但推測下一代之模組將以縱6 mm、橫5 mm尺寸者 爲主流。 同時，在 CDMA(CDMA : code division multiple access)領域，也同樣被推測目前的縱6 mm、橫6 mm的 尺寸，將會被要求設法依次開發出縱5 mm、橫5 mm甚 至縱4 mm、橫4 mm大小的產品。 在這種超小型的功率放大器模組，僅是在配線基板構 成的模組基板表面以二維方式安裝零件，將無法搭載裝配 電晶體等主動元件的半導體晶片（第1安裝零件），或由電 阻器（晶片電阻器）、電容器（晶片電容器）等之被動元件構 成的晶片零件（第2安裝零件），而需要三維方式的安裝。 如傳統方式在封裝用基板的表面、背面（上下面）分別 搭載半導體晶片的構造，分別位於表面、背面的半導體晶 片間，及背面的半導體晶片與表面的晶片零件間的配線是 經由封裝用基板內部的導體或配線連接，因此，內層的配 線層數增加，致使基板的基準電源電位（第1基準電源電 位，例如接地電位）不穩定，所謂基板接地的劣化成爲問 200421567 Ο) 同時，由於貫穿的通孔很多，可配線的領域變少，不 得不要加大封裝用基板的尺寸，妨礙到小型化。 本發明的目的在藉由提高搭載零件的安裝密度，達成 半導體裝置的小型化。 本發明的其他目的在提供，能夠確保封裝基板內層有 較大配線領域的半導體裝置。 本發明的其他目的在提供，能夠達成第1基準電源電 位的穩定化的半導體裝置。 本發明的其他目的在提供，能夠提高發熱量多的半導 體晶片的散熱性的半導體裝置。 本發明的其他目的在提供，能夠穩定動作的半導體裝 置。 本發明的上述以及其他目的與新穎的特徵，可以從本 說明書的記述及附圖獲得進一步的瞭解。 【發明內容】 茲簡單說明本案所揭示的發明中，具代表性者的槪要 如下。 (1)在封裝基板分別搭載複數個：裝配電晶體等主動 元件的半導體晶片（第1安裝零件及裝配電阻或電容器 等被動元件的複晶片零件（第2安裝零件）的半導體裝置 (半導體模組）的半導體裝置，其特徵爲， 上述封裝用基板有表面及其相反面而成爲安裝面的背 面，並在上述表面有凹部，而在上述表面、背面、凹部底 -8 - (4) (4)200421567 及內部分別設有規定圖案的配線，同時，此等各配線的一 部分是經由塡充於設在封裝用基板的孔內的導體，成電氣 方式連接在一起， 具有：設在上述封裝用基板背面的複數個外部連接端 子；及 設在上述封裝用基板背面的兼具散熱功能而成爲第1 基準電源（接地）的導體層， 上述凹部內成上下重疊狀搭載有複數片半導體晶片， 同時，位於上方的半導體晶片的上面與封裝基板的表面大 致上同高， 上述晶片零件是搭載於：上述封裝用基板的表面；及 上述位於上方的半導體晶片上面；以及位於上方的半導體 晶片上面及封裝用基板的表面， 上述封裝用基板的表面側的半導體晶片或晶片零件， 是被設在上述封裝用基板的表面側的絕緣性樹脂構成的密 封部覆蓋。 同時，位於下方的半導體晶片是密集安裝在封裝用基 板，位於下方的半導體晶片是發熱量較位於上方的半導體 晶片的發熱量大的零件。同時，位於下方的半導體晶片的 下面電極是，經由塡充在通孔的導體電氣方式連接在上述 導體層，位於上方的半導體晶片的電極的一部分，也是電 氣方式連接在上述導體層。 同時，封裝用基板的表面的上述凹部是多層次凹部 (兩層次凹部），下方的半導體晶片是固定在最下位的凹部 -9- (5) (5)200421567 (下方凹部）底，下方的半導體晶片上面的電極是經由導電 性引線，成電氣方式連接在延伸於多層次凹部的階層部分 的階層凹部（上方凹部）底上面的配線，上方的半導體晶片 的電極是經由導電性的球電氣方式連接在此引線。 【實施方式】 茲參照附圖詳細說明本發明的實施形態如下。再者， 在用以說明發明的實施形態的全附圖，具有同一功能者， 標示同一記號，省略重複說明。 (實施形態1) 第1圖至第20圖是關於本發明一實施形態（實施形態 1)的半導體裝置（功率放大模組）的圖。第1圖是表示半導 體裝置的外觀的平面圖，第2圖是表示半導體裝置的內部 的截面圖，第3圖是卸下密封體的半導體裝置的放大平面 圖，第4圖是沿第3圖的Y - Y線的截面圖，第5圖是卸 下密封體及上方的半導體晶片的上述半導體裝置的平面 圖。第6圖至第11圖是表示半導體裝置的封裝用基板的 第1層至第6層的配線圖案的模式圖。第12圖是表示半 導體裝置的電路架構的方塊圖。第13圖至第20圖是製造 本實施形態1的半導體裝置的各製程圖。 在本實施形態1，所說明的半導體裝置，是以，將本 發明應用在，例如分成多級放大攜帶式電話機的高頻信 號，被稱作功率放大模組的高頻模組製品的例子。 -10- 200421567 ⑹ 本實施形態1的半導體裝置（功率放大模組）ι是如第 2圖所示，具有：由配線基板構成的封裝用基板（模組基 板）2;搭載於此封裝用基板2的表面、背面中的表面2a 的第1安裝零件，配置成兩層的半導體晶片3a、3b ;搭 載於封裝用基板2的表面2a的第2安裝零件的複數個晶 片零件5;設在封裝用基板2的表面側，用以被覆上述第 1·及第2安裝零件的絕緣性樹脂構成的密封部6;設在 封裝用基板2的背面2b的外部電極端子9e及兼具散熱功 能的成爲第1基準電源的導體層9f。 在半導體晶片3a、3b成單片方式裝配有電晶體等構 成的1至複數個主動元件。晶片零件5則呈裝配有電阻元 件或電容元件等被動元件的表面安裝型晶片零件構造。本 實施形態1是如第2圖所示，晶片零件5是兩端分別有電 極5a的構造，此等電極5a是經由焊錫等接合材10連接 在配線的一部分的電極固定部9c。 本實施形態1的半導體裝置1，在製造時使用配線母 基板。此配線母基板30是如第13圖所示，由長方形板構 成，是將製造半導體裝置1的製品形成部31縱橫排列配 置的架構。如後述，此等製品形成部3 i在其表面搭載第 1及第2安裝零件後，在表面形成絕緣樹脂層以覆蓋第1 及第2安裝零件，在製造的最後階段，如第13圖所示， 沿縱橫劃上的切斷線32a、32b切斷以製造半導體裝置 1，因此其外觀是如第1圖所示，成爲扁平四方形。 如第2圖及第3圖所示，封裝用基板2是呈，在表面 -11- (7) (7)200421567 及背面有配線層，且重疊複數片在通孔塡充導體的氧化鋁 陶瓷等介電体的構造。製造此封裝用基板2時是，重疊複 數片稱作生薄片（green sheet)的未燒成前的陶瓷板，藉熱 壓接加壓，接著以規定溫度燒成，形成基板。實際製品的 構造是以絕緣層5層、配線層6層構成。 實施形態1的封裝用基板2在表面中央有凹部11。 此凹部11是多層次凹部。本實施形態1是重疊狀裝配兩 片半導體晶片，因此多層次凹部成兩層凹部。 亦即，凹部11有上方凹部lib，及設在此上方凹部 lib的底部 11 bf的下方凹部（最下位凹部）lla。下方凹部 11a的寬度與上方凹部lib-致，但長度較短，其結果成 爲階層式凹部，長度方向露出上方凹部 lib的底部 11 bf。此底部llbf是起因於本實施形態1的兩個半導體 晶片的大小，因晶片的大小，也可以將上方凹部11 b的底 部設在寬度方向。下一層的最下位凹部（下方凹部）lla的 底部llaf位於底部llbf的下方。 再者，若在下方凹部11a的底面11 af設較底面11 af 小的凹部，便可以成爲三層的凹部，可以裝配三層半導體 晶片。 在封裝用基板2的表面2a、背面2b、下方及上方凹 部11a、lib的底部llaf' llbf及內部分別設有規定圖案 的配線9，同時，此等各配線9的一部分是經由塡充在設 於封裝用基板的孔（通孔）9a內的導體9b，電氣方式連接 在一起。封裝用基板2的表面2a也設有配線，其一部分 •12· (8) (8)200421567 是如上述，構成連接晶片零件5的電極5a用的電極固定 部9c。同時，下方凹部11a的底部11 af的配線是成爲固 定半導體晶片的晶片搭載部9d。而，封裝用基板2的背 面2b也設有配線，此等配線是如上述，構成外部電極端 子9e或兼有散熱功能的第1基準電源的導體層9f。導體 層9f也可以當作外部電極端子。 在第6圖至第11圖表示，封裝用基板2的第1層至 第6層的配線圖案。再者，第11圖是從上方透視封裝用 基板2的背面2b的第6層配線圖案的模式圖。此等配線 圖案是模式圖。在第7圖至第11圖，封裝用基板2是分 別去除部分介電體層及配線層的圖，但說明時均說明是封 裝用基板2。在此等圖式，黑色圓點部分表示通孔9a及 塡充在該通孔的導體9b，斜線部分是配線9。 在第6圖及第7圖，封裝用基板2的中央設有長方形 的孔2h、2i，形成上方凹部lib。同時，如第8圖所示， 在封裝用基板2的中央設有接近正方形的孔2m，以形成 下方凹部11 a。孔2m的左右排列配置有配線9的前端， 這一部分形成上方凹部lib的底部11 bf，此等配線9的 前端部分連接其一端連接在半導體晶片的電極的引線的另 一端。第7圖所示的第2層，部分導體9b被分離，但在 孔2i外側的封裝用基板2的大致上整個區域配設有成爲 第1基準電源（接地層）的配線9。 第9圖所示的第4層，部分導體9b被分離，但在封 裝用基板2的大致上整個區域配設有成爲第1基準電源 -13- 200421567 Ο) (接地層）的配線9。第4層成爲形成下方凹部11a的面。 因此，在封裝用基板2中央緻密配置有導體9b (通孔 9a)。此等緻密配置的部分形成固定半導體晶片的晶片搭 載部9d。緻密配置的導體9b貫穿第10圖的第5層，連 接在第11圖的封裝用基板2背面2b的兼具散熱功能的第 1基準電源（接地層）構成的導體層9f。封裝用基板2的下 方凹部11a底的晶片搭載部9d緻密配設有導體9b (通孔 9a)，便可以將固定在晶片搭載部9d上的半導體晶片產生 的熱量經由導體層9f迅速散發至製品外部。第10圖的第 5層，左右分別形成有細微條狀線9s、9t。第11圖的第6 層形成有外部電極端子9e。 如第7圖的第2層及第9圖的第4層所示，因爲在封 裝用基板2的廣闊面積部分配置接地層，可以加強基板的 接地。再者，配線材料選擇銅系導體材料、銀系導體材料 等。 如第2圖、第4圖及第5圖所示，在封裝用基板2的 最下位的凹部底的下方凹部11 a底部11 af，經由焊錫等的 接合材20，固定下層的半導體晶片3a。下層的半導體晶 片3a是如第5圖所示，並排固定兩個半導體晶片3a。亦 即，雖未圖示，但設在半導體晶片3a下面大致上整個區 域的電極是以密接狀態連接在晶片搭載部9d。此電極成 爲第1基準電源電位（接地電位）。下層的半導體晶片3a 較上層的半導體晶片3b，動作時的發熱量大。而這些熱 量是從多數密接配設的導體9b迅速傳導至導體層9f，以 -14 - (10) (10)200421567 散熱。 同時，半導體晶片 3a是藉由 TAB(Tape Automated Bonding)技術搭載。亦即，如第15圖所示，經由金屬製 的引線22支持在載送帶21的半導體晶片3a在引線22的 中間部分被切斷，同時，經由接合材20固定在下方凹部 11a的底部llaf。這時，引線22的外端是經由接合材20 連接在設於上方凹部lib的底部llbf的配線9。亦即， 經由引線22，以電氣方式連接在延伸於多層次凹部的台 階部分的中層凹部底上面的配線9。 如第2圖至第5圖所示，在上方凹部lib插入上層的 半導體晶片3b，藉由倒裝晶片連接方式搭載。上層的的 半導體晶片3b是經由突起電極，亦即，經由球25電氣方 式連接在引線22 (參照第2圖），或經由球26電氣方式連 接在設於上方凹部lib的底部llbf的配線9上（參照第4 圖）。如第4圖所示，較之上方凹部lib的底部llbf的配 線9上面的高度，連接在該配線9的引線22的上面較 高。因此，接合在配線9的球26使用較接合在引線22的 球25厚的球。這項高度差相當於引線22的厚度加上接合 材23的厚度的高度，例如，100 μπι左右。球25及球26 使用焊錫或金等材料。 同時，雖不特別詳細表示，但在上層的半導體晶片 3b的上面設有絕緣層，此絕緣層上設有配線，設有藉由 配線固定晶片零件5的電極5a的電極固定部9c。而在此 一對電極固定部9c，經由接合材1〇固定有晶片零件5的 •15· (11) (11)200421567 電極5a。同時，位於上述凹部11內的上方的上層的半導 體晶片3b上面的高度，是與封裝用基板2的表面大致上 同高。其結果，晶片零件5可以將一方的電極5a固定在 上層的半導體晶片3b上面的電極固定部9c’將另一方的 電極5a固定在封裝用基板2表面的電極固定部9c，可以 將晶片零件5掛在上層的半導體晶片3b與封裝用基板2 間安裝。其結果，可以提高晶片零件5的安裝效率。 同時，上層的半導體晶片3b的電極的一部分，特別 是接地電極是如第2圖所示，經由球25、引線22、接合 材23、配線9、導體9b、配線9(晶片搭載部9d )、導體 9b，電氣方式連接在導體層9f。同時，此路徑也成爲傳 遞熱量的路徑。 形成密封部6的絕緣性樹脂埋沒上層的半導體晶片 3b的周圍或下面，亦即，也塡埋與下層的半導體晶片3a 間的空間，成爲所謂塡底密封構造。 本實施形態1的半導體裝置1是如上述構成功率放大 模組1。本實施形態1的功率放大模組1是如第12圖所 示，將兩種頻帶分成兩個放大電路放大，各放大電路以3 級進行放大，而這個時候的各級放大電路是由上層的控制 用半導體晶片3b的控制電路加以控制。 兩種頻帶是，例如 GSM(Global System Mobile Communication)方式，頻帶是使用880〜915 MHz。而另 一方是 DCS(Digital Communication System 1800)，頻帶 使用1710 ~ 1785 MHz，是對應此兩種方式的模組。 (12) (12)200421567 GSM方式的放大系統，輸入端子〔Pin(GSM)〕與輸 出端子〔Pout(GSM)〕間設有第1放大級13、第2放大級 14、最後放大級15，DCS方式的放大系統，輸入端子 〔Pin(DCS)〕與輸出端子〔Pout(DCS)〕間設有第1放大 級16、第2放大級17、最後放大級18、各放大級是由連 接在控制端子（Vclt)得控制電路19加以控制。雖未圖示， 本實施形態1的電晶體（放大元件）是使用MOSFET (Metal Oxide Semiconductor Field Effect Transistor)。這時，控 制電路19是藉由控制施加在各放大級的MOSFET的閘極 的偏壓，來控制輸出的P out(GSM)、P out(DCS)的電力。 此等電路施加有第2基準電源電壓（Vdd)。 最後放大級的動作電流大，因此裝配此最後放大級的 電晶體的半導體晶片較之裝配第1放大級的電晶體的半導 體晶片，其發熱量大很多。第2放大級的動作電流也較第 1放大級的電晶體大，因此發熱量也較第1放大級的電晶 體大。因此，本實施形態1使下層的半導體晶片3a的一 方爲裝配GSM用的第2放大級及最後級的電晶體的半導 體晶片，使下層的半導體晶片3a的另一方爲裝配DCS用 的第2放大級及最後級的電晶體的半導體晶片，而密接安 裝在封裝用基板2的下方凹部11a的底部11 af。而以單片 方式裝配發熱量比較小的構成GSM用及DCS用第1放大 級的電晶體與控制電路19的半導體晶片，則作爲上層的 半導體晶片3b。 各放大級是由電晶體、偏壓電路或輸入匹配電路等構 -17- (13) (13)200421567 成。而此等電路是由電容元件、電阻元件及電感等構成。 因此，藉由使用規定數目的晶片電阻器、晶片電容器及晶 片電感器等，則可形成第12圖所示的電路。 其次，再參照第13圖至第19圖的模式圖，說明本實 施形態1的功率放大模組1的製造方法。第13圖是製造 本實施形態1的半導體裝置的配線母基板的模式斜視圖， 第14圖是上述配線母基板的製品形成部的模式截面圖， 第15圖是搭載半導體晶片的上述製品形成部的模式截面 圖，第1 6圖是以重疊狀搭載半導體晶片的上述製品形成 部的模式截面圖，第17圖是搭載晶片零件的上述製品形 成部的模式截面圖，第18圖是形成密封部形成用絕緣樹 脂層的上述製品形成部的模式截面圖，第19圖是切斷配 線母基板所形成的半導體裝置的截面圖。 首先，如第13圖所示，準備上述配線母基板30。第 14圖是表示製品形成部31放大截面圖。從此以後，至第 18圖，擬參照單一製品形成部3 1進行說明。圖中，一對 兩點虛線間的部分便是製品形成部3 1。 如第1 4圖所示，在各製品形成部3 1的表面中央形成 有如上述的凹部11(兩層凹部）。因此，如第15圖所示， 從載送帶21在虛線部分切斷引線22，從載送帶21分離 半導體晶片3a，同時，經由接合材20將下層的半導體晶 片3a下面的電極部分（未圖示）固定在凹部11的下方凹部 11a的底部llaf。同時，經由接合材23將引線22的外端 連接在設於上方凹部lib底部llbf的配線9。 -18- (14) (14)200421567 接著，如第16圖所示，將上層的半導體晶片3b插入 上方凹部lib，經由球25及球26 (參照第4圖）將上層的 半導體晶片3b藉由導裝晶片方式連接搭載於形成在上方 凹部lib的底部llbf的配線9。在這種狀態時，上層的 半導體晶片3b的上面與封裝用基板2的表面2a大致上在 同一高度。 接著，如第17圖所示，在上層的半導體晶片3b的上 面，與封裝用基板2的表面2a分別搭載晶片零件5。晶 片零件5將兩端的電極5a經由接合材10連接在設於上層 的半導體晶片3b的上面或封裝用基板2表面2a的電極固 定部9c。 這時，由於上層的半導體晶片3b的上面與封裝用基 板2的表面是大致上在同一高度，因此，可以將晶片零件 5的一方的電極5a固定在上層的半導體晶片3b上面的電 極固定部9c，將另一方的電極5a固定在封裝用基板2表 面的電極固定部9c。藉此，可以擴大晶片零件5的搭載 領域。其結果，可以搭載更多晶片零件5，如果是搭載有 限的晶片零件時，可以縮小封裝用基板2的尺寸，功率放 大模組1也可以小型化。 接著，如第18圖所示，在封裝用基板2的表面2a側 形成被覆上述晶片零件5的一定厚度的絕緣樹脂層28。 形成絕緣樹脂層28的絕緣樹脂層可埋沒上層的半導體晶 片3b的周圍或下面，亦即，也可以埋沒與下層半導體晶 片3a間的空間，成爲所謂塡底密封構造。 -19- (15) (15)200421567 接著，沿著第13圖的切斷線3 2a、3 2b切斷配線母基 板30連同絕緣樹脂層28，藉此可以同時製造複數個如第 19圖所示的半導體裝置（功率放大模組）1。 第20圖是表示製成的半導體裝置1的安裝狀態的模 式截面圖。母基板等之安裝基板40是由例如PCB(priiited circuit board)構成，表面及其相反面的背面，以及其內部 分別有配線40a，同時，規定的配線40a是經由塡充在通 孔的導體40b電氣方式連接在一起。此安裝基板40是對 應實施形態1的導體層9f及外部電極端子9e，具有由配 線40a構成的配線區40e。其結果，在安裝半導體裝置1 時，可以經由焊錫等接合材41將外部電極端子9e及導體 層9f連接在安裝基板40的配線區40e。在下層的半導體 晶片3a產生的熱量可經由接合材20、晶片搭載部9d、導 體9b、導體層9f、接合材41，迅速傳導至配線區40e， 進行散熱。 本實施形態1的半導體裝置1具有以下的效果。 (1) 因爲在設於封裝用基板2的表面2a側的凹部11 內，成重疊狀配置半導體晶片3a、3b，因此，較之將半 導體晶片排在平面的構造，可以提高安裝密度。 (2) 因爲在設於封裝用基板2的表面2a側的凹部11 內，成重疊狀配置半導體晶片3a、3b，因此，較之將半 導體晶片排在平面的構造，可以縮小封裝用基板2的面 積，達成半導體裝置1的小型化。 (3) 因爲在上層的半導體晶片3b上面也搭載晶片零 -20· (16) (16)200421567 件5，因此可以提高安裝密度或達成半導體裝置1的小型 化。也可以將搭載於上層的半導體晶片3b上面的晶片零 件5的電極，與上層的半導體晶片3b的內部配線連接。 (4) 因爲上層的半導體晶片3b上面與封裝用基板2 的表面2a的高度大体上同高，因此可以將晶片零件5的 一方的電極5a固定在上層的半導體晶片3b上的電極固定 部9c，將另一方的電極5a固定在封裝用基板2的表面2a 上的電極固定部9c，經由晶片零件5連接上層的半導體 晶片3b的配線與封裝用基板2的表面2a的配線。同時， 上層的半導體晶片3b與封裝用基板2的境界部分也可以 搭載晶片零件5，因此可以進一步提高安裝密度或達成半 導體裝置1的小型化。 (5) 因爲可以經由球25球26、甚至封裝用基板2內 部的配線9或導體9b，將上層的半導體晶片3b的接地以 短距離引至導體層9f，因此可以使上層的半導體晶片3b 的接地的阻抗降低。 (6) 藉由上述（5)，由於封裝用基板2內的配線9或 導體9b是以熱傳導性良好的金屬（以金屬糊漿形成）形 成，因此，上層的半導體晶片3b的散熱性也良好。 (7) 下層的半導體晶片3a是密接連接在封裝用基板 2的凹部11底，同時在此底部密接配設有複數個導體9b 用以將熱量傳給導體層9f，因此，縱使下層的半導體晶 片3a的發熱量很大，1乃可穩定動作。 (8) 在封裝用基板2，因爲貫穿全層的配線用通孔數 (17) (17)200421567 會減少，可以確保內層的配線領域有較大的面積，可以提 高基板的配線密度。藉此也可以達成封裝用基板2的小型 化。 (9) 各配線層由成爲第1基準電源（接地電位）的導體 層9f，經由複數個通孔9a及導體9b連接成低阻抗狀態， 可以強化整個基板的接地，因此，半導體裝置1可以穩定 動作。 (10) 由於使下層的半導體晶片3a爲包含構成功率放 大模組1的電晶體的半導體晶片3a，使上層的半導體晶 片3b成爲包含構成第1放大級或控制電路19的電晶體 的半導體晶片，因此可以提供小型，安裝密度高、且可以 穩定動作的功率放大模組1。 (實施形態2) 第21圖是表示本發明其他實施形態（實施形態2)的 半導體裝置的模式截面圖。本實施形態2的半導體裝置1 與實施形態1同樣，是將本發明應用在，含有：功率放大 模組等發熱量大的半導體晶片3a(第1安裝零件），與發熱 量較半導體晶片3a小的半導體晶片3b(第2安裝零件）的 半導體裝置1者。 實施形態2的半導體裝置1是，其設在封裝用基板2 表面2a的凹部11採單層構造，在此凹部底，與實施形態 1同樣，經由接合材20密接安裝半導體晶片3a的構造。 使搭載的半導體晶片3a的上面，與封裝用基板2的表面 -22- (18) (18)200421567 2a的高度大致上相同。這時，爲了使高度相同，在半導 體晶片3a下面配設熱傳導性良好，且電氣傳導性良好的 接合劑層（例如50 μπι左右的厚度），而藉由調整此接合劑 的厚度，以調整半導體晶片3a上面的高度。此方法也可 以適用於上述實施形態1。 同時，在半導體晶片3a上面與封裝用基板2的表面 2a上安裝中間配線板45 (用以電氣方式連接安裝在表 面、背面的電氣零件的基板：插入中間的配線板），再於 此中間配線板45上面以倒裝晶片方式安裝半導體晶片 3b。同時，在封裝用基板2表面2a，與實施形態1同樣 搭載晶片零件5 (第2安裝零件）。 中間配線板45的上下面的電極是經由設在表面及內 部的配線成電氣方式相連接，藉由中間配線板45以電氣 方式連接位於上下的上述第1安裝零件及封裝用基板間的 配線。亦即，中間配線板45在上面及下面有電極45a、 45b或配線45c。位於上方的半導體晶片3b在下面有電極 3e同時在其表面設有突起電極（突塊電極）3f。半導體晶片 3b的突起電極3f是以倒裝晶片方式安裝在中間配線板45 上面的電極45a或配線45c。 搭載於凹部11底部的半導體晶片3a在其上面有電極 3s，同時在其表面有突起電極（突塊電極）3t。而，此等突 起電極3t是連接在中間配線板45下面的電極45b。中間 配線板45較凹部11大，設在從凹部11突出的中間配線 板45的電極45b是經由突起電極2f連接在封裝用基板2 (19) (19)200421567 表面2a的電極2e。突起電極2f是預先設在電極2e。此 等各零件是由一次或分數次的接合材或突起電極的回流處 理加以安裝。 雖未圖示，但是，由於在重疊的各零件間進行塡底密 封，可以提高使用性或可靠性。同時，也可以在封裝用基 板2的表面2a，以覆蓋晶片零件5、半導體晶片3a、 3b、中間配線板45狀形成密封部6。 在本實施形態2，封裝用基板2的背面2b配設有兼 具散熱功能的成爲第1基準電源的導體層9f，設在位於 下方的半導體晶片3a(第1安裝零件）下面的電極是經由接 合材20、晶片搭載部9d、導體9b電氣方式連接在導體層 9f ° 本實施形態2的封裝用基板2較之實施形態1的封裝 用基板2，可以減少介電體及導體層（配線層）的層數，可 以降低半導體裝置1的製造成本。 本實施形態2的半導體裝置1的半導體晶片3a、 3b、封裝用基板2的配線連接的自由度很大，可以因應複 雜的偏壓電路、匹配電路等，有可以提高製品性能的效 果。 本實施形態2的半導體裝置1與實施形態1具有相同 的效果。 (實施形態3) 第22圖是表示本發明其他實施形態（實施形態3)的 (20) (20)200421567 半導體裝置的模式截面圖，第23圖是表示裝配到本實施 形態3的半導體積體電路裝置的上部半導體晶片的電極再 配線構造的部分模式放大截面圖。 本實施形態3的半導體裝置1是跟實施形態1同樣， 將本發明應用在，含有：功率放大模組等發熱量大的半導 體晶片3a(第1安裝零件），與發熱量較半導體晶片3a小 的半導體晶片3b (第2安裝零件）的半導體裝置1者。 實施形態3的半導體裝置1是以半導體晶片3b取代 實施形2的半導體裝置1的中間配線板者。亦即，半導體 晶片3b是在配設電極的下面設再配置配線層50，在此再 配置配線層50的表面設再配置突起電極（突塊電極）51。 因爲在半導體晶片3b的表面的再配置，各再配置突起電 極51可以連接到搭載於凹部11底部的半導體晶片3a上 面的電極3s，或封裝用基板2的表面2a的電極2e。 再配置突起電極51及再配置配線層50是如第23圖 所示。第23圖是以模式方式表示半導體晶片3b的一部分 的圖。在構成半導體晶片3b的半導體基板部分53的表面 部分，設有以絕緣性保護膜54被覆其周圍的電極墊52。 此電極墊52傳統上是被當作外部電極端子使用，是例如 進行線焊接的部分。 在本實施形態3，是將一端連接在電極墊52的導體 構成的再配線55選擇性設在絕緣性保護膜54上。同時， 在絕緣性保護膜54上形成選擇性被覆再配線55的絕緣膜 56。電極墊52的另一端露出，在此部分形成由突起電極 -25- (21) (21)200421567 (突塊電極）構成的再配置突起電極51。再配線55可以在 絕緣性的絕緣性保護膜54上形成爲所希望的圖案。 在本實施形態3’於封裝用基板2背面2b設有兼具 散熱功能成爲第1基準電源的導體層9f，設在位於下方 的半導體晶片3a(第1安裝零件）下面的電極是經由接合材 20、晶片搭載部9d、導體9b電氣方式連接在導體層9f。 本實施形態3的半導體裝置1不需要中間配線板，可 以薄型化。因爲，不需要中間配線板45，因此可以進一 步降低製造！成本。 本實施形態3的半導體裝置1與實施形態2同樣有提 高性能的效果。 本實施形態3的半導體裝置1也與實施形態1具有相 同的效果。 (實施形態4) 第24圖是表示本發明其他實施形態（實施形態4)的 半導體裝置的模式截面圖。 本實施形態4的半導體裝置1是在實施形態1的半導 體裝置1，以導電性的金屬線7電氣方式連接搭載於凹部 (兩階層凹部）11的下方凹部11a的底部llaf的半導體晶 片3a的電極3s，與設.在上方凹部lib的底部11 bf的配線 9。同時，半導體晶片3b的電極是經由球25電氣方式連 接在上方凹部lib的底部llbf的配線9。其他部分的構 造與實施形態1的半導體裝置1相同。 -26 - (22) (22)200421567 在本實施形態3，於封裝用基板2背面2b設有兼具 散熱功能，成爲第 1基準電源的導體層9f，設在位於下 方的半導體晶片3a(第1安裝零件）下面的電極是經由接合 材20、晶片搭載部9d、導體9b電氣方式連接在導體層 9f。同時，位於上方的半導體晶片3b的電極也是經由球 25、配線9導體9b配線9、導體9b電氣方式連接在導 體層9f。 本實施形態4的半導體裝置1具有跟實施形態1同樣 的效果。 (實施形態5) 第25圖是表示本發明其他實施形態（實施形態5)的半 導體裝置的模式截面圖。 本實施形態5的半導體裝置1是在實施形態1的半導 體裝置1，使凹部11包括有最下位的凹部llx、中層的凹 部lly、最上位的凹部llz，而成爲三層次凹部。最下位 的凹部llx與實施形態4的下方凹部11a相同，而經由 接合材20在此最下位的凹部llx密接安裝半導體晶片3a (第1安裝零件）。同時，在半導體晶片3a上面的電極3s 是與實施形態4同樣，經由金屬線7電氣方式連接在設於 中層凹部lly底（多階層凹部的台階部分的第1中段凹部 底）的導體層9f。 位於上方的半導體晶片3b(第1安裝零件）的下面周邊 載置於，最上位的凹部llz的凹部底（位於較第1中層凹 -27- (23) (23)200421567 部底爲上方的第2中層凹部底），並經由接合材61固定。 半導體晶片3b上面的電極3u，於設在最上位的凹部llz 底（第2中層凹部底）的配線9，是經由導電性的金屬線7 電氣方式連接在一起。 同時，封裝用基板2的表面2a以跟實施形態1同樣 的架構安裝有晶片零件5。同時，在封裝用基板2表面2a 設有密封部6，用以被覆半導體晶片3a、3b或晶片零件 5。在半導體晶片3a與半導體晶片3b間的空隙也塡充有 構成密封部6的絕緣性樹脂。 在本實施形態5，於封裝用基板2背面2b設有兼具 散熱功能，成爲第1基準電源的導體層9f，設在位於下 方的半導體晶片3a(第1安裝零件）下面的電極是經由接合 材20、晶片搭載部9d、導體9b電氣方式連接在導體層 9f。同時，位於上方的半導體晶片3b的電極也是經由金 屬線7、配線9導體9b配線9、導體9b電氣方式連接 在導體層9f。 本實施形態5的半導體裝置1具有跟實施形態1同樣 的效果，而且，半導體晶片3a、3b對封裝用基板2的高 度方向不需要有位置上的精密度，具有可以容易裝配的效 果。 以上，依據實施形態具體說明由本發明人所完成的發 明，但本發明並非限定如上述實施形態，當然可以在不脫 離其主旨的範圍內做各種變更。本發明可以廣泛應用在， 於封裝用基板的表面側成多層搭載複數個半導體晶片，並 -28- (24) (24)200421567 搭載晶片零件的架構的混合積體電路裝置。這時，裝配於 半導體晶片的電晶體可以是矽的氧化膜閘極型、氮化膜等 其他絕緣閘極型電晶體，而雙極電晶體等其他矽電晶體， 或化合物構成的各種電晶體也可以。 茲列舉可以藉由本案所揭示的發明中具代表性者獲得 的效果如下。 (1) 可以藉由提高搭載零件的安裝密度，達成半導體 裝置的小型化。 (2) 可以提供能夠確保較大的封裝用基板內層配線領 域的半導體裝置。 (3) 可以提供能夠達成第1基準電位（接地電位）的穩定 化的半導體裝置。 (4) 可以提供能夠提高發熱量多的半導體晶片的散熱 性的半導體裝置。 (5) 可以提供能夠穩定動作的半導體裝置。 (6) 可以提供能夠穩定動作的功率放大模組。 如以上所述，本發明的半導體裝置可以考慮散熱性， 將發熱量不相同的複數個半導體晶片分別搭載於封裝用基 板，因此半導體裝置可以穩定動作。同時，在分別搭載半 導體晶片時，以重疊方式搭載半導體晶片’因此可以達成 半導體裝置的小型化，最適合於攜帶式電話機用的高頻積 體電路裝置。因此，將本發明應用在功率放大模組時’可 以提供小型、輕量而可以穩定動作的功率放大模組° 【圖式簡單說明】 -29· (25) (25)200421567 第1圖是表示本發明一實施形態（實施形態1)的半導 體裝置（功率放大模組）的外觀的平面圖。 第2圖是表示上述半導體裝置的內部架構的截面圖。 第3圖是卸下密封體的上述半導體裝置的放大平面 圖。 第4圖是沿第3圖的Y- Y線的截面圖。 第5圖是卸下密封體及上方的半導體晶片的上述半導 體裝置的平面圖。 第6圖是表示上述半導體裝置的封裝用基板的第1層 配線圖案的模式圖。 第7圖是表示上述封裝用基板的第2層配線圖案的模 式圖。 第8圖是表示上述封裝用基板的第3層配線圖案的模 式圖。 第9圖是表示上述封裝用基板的第4層配線圖案的模 式圖。 第10圖是表示上述封裝用基板的第5層配線圖案的 模式圖。 第11圖是表示從上面側透視上述封裝用基板的背面 的第6層配線圖案的模式圖。 第12圖是表示本實施形態1的半導體裝置的電路架 構的方塊圖。 第13圖是製造本實施形態1的半導體裝置的配線母 基板的模式斜視圖 •30- (26) (26)200421567 第14圖是上述配線母基板的製品形成部的模式截面 圖。 第15圖是搭載半導體晶片的上述製品形成部的模式 截面圖。 第1 6圖是以重疊狀搭載半導體晶片的上述製品形成 部的模式截面圖。 第1 7圖是搭載晶片零件的上述製品形成部的模式截 面圖。 第1 8圖是形成密封部形成用絕緣樹脂層的上述製品 形成部的模式截面圖。 第19圖是切斷配線母基板所形成的半導體裝置的截 面圖。 第20圖是表示本實施形態1的半導體裝置的安裝狀 態的模式截面圖。 第21圖是表示本發明其他實施形態（實施形態2)的 半導體裝置的模式截面圖。 第22圖是表示本發明其他實施形態（實施形態3)的 半導體裝置的模式截面圖。 第23圖是表示裝配到本實施形態3的半導體積體電 路裝置的上部半導體晶片的電極再配線構造的部分模式放 大截面圖。 第24圖是表示本發明其他實施形態（實施形態4)的 半導體裝置的模式截面圖。 第25圖是表示本發明其他實施形態（實施形態5)的 •31 - (27) (27)200421567 半導體裝置的模式截面圖。 [主要元件對照表] 1 :半導體裝置 2 :封裝用基板 2 a :表面 2b :背面 2f、3f、3t :突起電極 2e、 3e、 3s、 5a:電極 2h、2i ··孑L 3a、3b :半導體晶片 5 :晶片零件 6 :密封部 7 :金屬線 9 :配線 9a :通孔 9b :導體 9 c :電極固定部 9d :晶片搭載部 9e :外部電極端子 9f :導體層 10 :接合材 11 :凹部 11 a :下方凹部 -32- (28) (28)200421567 lib :上方凹部 llaf、llbf ··底部 1 9 :控制電路 21 :載送帶 22 :引線 23、41、61 :接合材 25 、 26 :球 30 :配線母基板 3 1 :製品形成部 32a、32b :切斷線 40 :安裝基板 40a、45c:配線 40b ··導體 4 0 e :配線區 45 :中間配線板 45a、45b ：電極 5 0 :再配置配線層 5 1 :再配置突起電極 52 :電極墊 53 :半導體基板部分 54 :絕緣性保護膜 55 :再配線 56 :絕緣膜 -33·200421567 Ο) 玖, Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor device ', and particularly to a semiconductor module having a structure in which a semiconductor chip is mounted on a surface of a wiring substrate in a multi-layered manner while passive components are mounted. Very effective technology.  [Prior art] The conventional high-frequency integrated circuit device, Are mounted on the wiring board:  Semiconductor wafers with active components such as transistors (first mounting part); An example of a semiconductor device (semiconductor module) in which a chip part (second mounting part) composed of a passive element such as a resistor or a capacitor is mounted. This high-frequency integrated circuit device is used for processing high-frequency signals of various communication devices such as mobile communication.  An example of a high-frequency integrated circuit device, Its architecture is, have: A multilayer substrate stacked with a plurality of dielectric layers; Semiconductor wafers and wafer parts mounted on the surface of multilayer substrates; A semiconductor wafer provided in an opening portion of a mounting surface of an electronic device on the opposite side of the surface of the multilayer substrate; Around the multilayer substrate, At the same time directly contact the surface of the semiconductor wafer mounted on the surface of the multilayer substrate, Electromagnetic shielding cover with electromagnetic shielding function; A heat sink mounted under the semiconductor wafer at the opening; On the mounting surface of the multilayer substrate, Used to attach electrodes to electronic equipment. On the other hand, a mounting portion is formed at an end of the electromagnetic shielding cover when the electromagnetic shielding cover is mounted on an electronic device. (Reference, E.g:  Patent Document 1).  [Patent Document 1] -6- (2) (2) 200421567 Japanese Patent Laid-Open No. 2000-299427 (pages 4-6,  Figure 1) Power amplifier module (also known as PA) for portable telephones, Faster size and higher functionality. One of the communication methods is the conventional GSM (Global S y s t e m Μ 〇 bi i 1 e C 〇 m m u n i c a t i 〇 n) method, The size of this G S Μ power amplifier module is currently 10 mm vertical, 8 mm across, However, it is speculated that the next generation of modules will be 6 mm in length, A size of 5 mm across is the mainstream.  Simultaneously, In CDMA (CDMA:  code division multiple access) field, It is also estimated that the current vertical length of 6 mm, 6 mm across, Will be asked to try to develop a 5 mm vertical, 5 mm horizontal or even 4 mm vertical, 4 mm size products.  In this ultra-small power amplifier module, Only the components are mounted in two dimensions on the surface of the module substrate composed of the wiring substrate. Will not be able to mount semiconductor wafers (first mounting parts) equipped with active components such as transistors, Or by resistors (chip resistors), Chip parts (second mounting parts) made of passive components such as capacitors (chip capacitors), It requires three-dimensional installation.  On the surface of the packaging substrate, Structures for mounting semiconductor wafers on the back (top and bottom), Are located on the surface, Between the semiconductor wafers on the back, The wiring between the semiconductor wafer on the back and the wafer components on the front is connected via the conductor or wiring inside the packaging substrate. therefore, The number of wiring layers in the inner layer increases, The reference power supply potential of the substrate (the first reference power supply potential, Such as ground potential) is unstable, The so-called deterioration of the substrate ground becomes a problem 200421567 〇) At the same time, Because there are many through holes, Fewer wiring areas, Must not increase the size of the substrate for packaging, Prevents miniaturization.  The object of the present invention is to increase the mounting density of mounted components, Achieve miniaturization of semiconductor devices.  Other objects of the invention are to provide, It is possible to ensure a semiconductor device with a large wiring area in the inner layer of the package substrate.  Other objects of the invention are to provide, Semiconductor device capable of achieving stabilization of first reference power supply potential.  Other objects of the invention are to provide, A semiconductor device capable of improving heat dissipation of a semiconductor wafer having a large amount of heat.  Other objects of the invention are to provide, A semiconductor device capable of stable operation.  The above and other objects and novel features of the present invention, Further understanding can be obtained from the description of this specification and the drawings.  [Summary of the Invention] Among the inventions disclosed in this case, The key points of the representative are as follows.  (1) Multiple packages are mounted on the package substrate: A semiconductor device (semiconductor module) in which a semiconductor wafer including an active element such as a transistor (a first mounting component and a multi-chip component (second mounting component) including a passive component such as a resistor or a capacitor is mounted, It is characterized by,  The above-mentioned packaging substrate has a back surface that is a mounting surface with a surface and an opposite surface thereof, And there are recesses on the surface, And on the above surface, back, The bottom of the recess -8-(4) (4) 200421567 and the wiring with a prescribed pattern are provided inside, Simultaneously, A part of each of these wirings is a conductor filled in a hole provided in the packaging substrate via Connected together electrically  have: A plurality of external connection terminals provided on a back surface of the packaging substrate; And a conductor layer provided on the back surface of the above-mentioned package substrate and having a heat dissipation function and serving as a first reference power source (ground),  A plurality of semiconductor wafers are mounted on the recesses so as to overlap each other,  Simultaneously, The upper surface of the upper semiconductor wafer is approximately the same height as the surface of the package substrate.  The above chip parts are mounted on: The surface of the packaging substrate; And above the above-mentioned semiconductor wafer; And on the upper surface of the semiconductor wafer and the surface of the packaging substrate,  The semiconductor wafer or wafer component on the front side of the packaging substrate,  It is covered with a sealing portion made of an insulating resin provided on the surface side of the above-mentioned packaging substrate.  Simultaneously, The underlying semiconductor wafer is densely mounted on a packaging substrate. The semiconductor wafer located below is a component that generates more heat than the semiconductor wafer located above. Simultaneously, The lower electrode of the lower semiconductor wafer is, Is electrically connected to the above-mentioned conductor layer through a conductor filled in a through hole, A part of an electrode of a semiconductor wafer located above, It is also electrically connected to the conductor layer.  Simultaneously, The recesses on the surface of the packaging substrate are multi-level recesses (two-level recesses), The lower semiconductor wafer is fixed at the bottom of the lowest recess -9- (5) (5) 200421567 (the lower recess), The electrodes on the lower semiconductor wafer are via conductive leads, The wiring electrically connected to the bottom surface of the hierarchical recess (upper recess) extending over the hierarchical part of the multi-level recess, The electrode of the upper semiconductor wafer is electrically connected to this lead via a conductive ball.  [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Furthermore,  Throughout the drawings for explaining embodiments of the invention, Those with the same function,  Mark the same sign, Duplicate description is omitted.  (Embodiment 1) FIGS. 1 to 20 are diagrams showing a semiconductor device (power amplification module) according to an embodiment (Embodiment 1) of the present invention. FIG. 1 is a plan view showing the appearance of a semiconductor device. Fig. 2 is a cross-sectional view showing the inside of a semiconductor device. Fig. 3 is an enlarged plan view of a semiconductor device with a sealed body removed, Fig. 4 is a cross-sectional view taken along line Y-Y in Fig. 3, Fig. 5 is a plan view of the semiconductor device with the sealed body and the semiconductor wafer thereon removed. Figures 6 to 11 are schematic diagrams showing the wiring patterns of the first to sixth layers of the substrate for packaging a semiconductor device. Fig. 12 is a block diagram showing a circuit structure of a semiconductor device. 13 to 20 are diagrams showing respective processes for manufacturing the semiconductor device according to the first embodiment.  In the first embodiment, The described semiconductor device, So, Applying the present invention to For example, the high frequency signal of a portable telephone is divided into multiple stages, An example of a high-frequency module product called a power amplifier module.  -10- 200421567 ⑹ The semiconductor device (power amplifier module) of the first embodiment is shown in FIG. 2. have: Packaging substrate (module substrate) composed of wiring substrate 2; Mounted on the surface of this packaging substrate 2, The first mounting part of the surface 2a in the back surface, The semiconductor wafers 3a arranged in two layers, 3b; The plurality of wafer parts 5 mounted on the surface 2a of the packaging substrate 2 and the second mounting parts; Provided on the front surface side of the packaging substrate 2, A sealing portion 6 made of an insulating resin for covering the above-mentioned first and second mounting parts; An external electrode terminal 9e provided on the back surface 2b of the packaging substrate 2 and a conductor layer 9f serving as a first reference power source that also functions as a heat sink.  On the semiconductor wafer 3a, 3b is assembled in a monolithic manner with one to a plurality of active elements composed of transistors and the like. The chip component 5 has a surface-mount type chip component structure equipped with a passive element such as a resistive element or a capacitive element. In the first embodiment, as shown in FIG. 2, The chip component 5 has a structure in which electrodes 5a are respectively formed at both ends. These electrodes 5a are electrode fixing portions 9c connected to a part of the wiring via a bonding material 10 such as solder.  The semiconductor device 1 according to the first embodiment, A wiring mother substrate is used in manufacturing. This wiring mother substrate 30 is as shown in FIG. Made of rectangular plates, This is a structure in which the product forming portions 31 for manufacturing the semiconductor device 1 are arranged in a vertical and horizontal manner. As described later, After these product forming portions 3 i have the first and second mounting parts mounted on their surfaces, Forming an insulating resin layer on the surface to cover the first and second mounting parts, In the final stages of manufacturing, As shown in Figure 13,  Along the cut-off lines 32a, 32b is cut to manufacture a semiconductor device 1, So its appearance is shown in Figure 1. Become a flat square.  As shown in Figures 2 and 3, The packaging substrate 2 is There are wiring layers on the front -11- (7) (7) 200421567 and the back, A structure in which a plurality of dielectric bodies such as alumina ceramics are filled with conductors in the through holes is stacked. When manufacturing this packaging substrate 2, Overlapping a plurality of unfired ceramic plates called green sheets, By heat and pressure, And then fired at a predetermined temperature, Form a substrate. The structure of the actual product is 5 layers of insulating layer, The wiring layer is composed of 6 layers.  The package substrate 2 according to the first embodiment has a recessed portion 11 in the center of the surface.  This recessed portion 11 is a multi-level recessed portion. In the first embodiment, two semiconductor wafers are mounted on top of each other. Therefore, the multi-level recesses are formed into two levels of recesses.  that is, The recess 11 has an upper recess lib, And a lower recess (lowermost recess) 11a provided at the bottom 11 bf of the upper recess lib. The width of the lower recess 11a is the same as the width of the upper recess 11a, But shorter The result is a hierarchical recess, The bottom 11 bf of the upper recess lib is exposed in the length direction. The bottom 11bf is the size of the two semiconductor wafers resulting from the first embodiment. Due to the size of the chip, The bottom portion of the upper recessed portion 11b may be provided in the width direction. The bottom llaf of the lowermost recessed portion (lower recessed portion) 11a of the next layer is located below the bottom 11bf.  Furthermore, If a recessed portion smaller than the bottom surface 11 af is provided in the bottom surface 11 af of the lower recessed portion 11 a, It can become a three-layer recess, Three layers of semiconductor wafers can be assembled.  On the surface 2a of the packaging substrate 2, Back 2b, Lower and upper recesses 11a, The bottom llaf 'llbf and the inside of the lib are respectively provided with a predetermined pattern of wiring 9, Simultaneously, A part of each of these wirings 9 is a conductor 9b filled in a hole (through-hole) 9a provided in the packaging substrate via a pad, Electrically connected together. The surface 2a of the packaging substrate 2 is also provided with wiring, A part of it • 12 · (8) (8) 200421567 is as above, An electrode fixing portion 9c for the electrode 5a to which the wafer component 5 is connected is formed. Simultaneously, The wiring of the bottom portion 11 af of the lower recessed portion 11a is a wafer mounting portion 9d that becomes a fixed semiconductor wafer. and, The back surface 2b of the packaging substrate 2 is also provided with wiring, These wirings are as described above, The conductive layer 9f constituting the external electrode terminal 9e or the first reference power source also having a heat dissipation function. The conductive layer 9f can also be used as an external electrode terminal.  As shown in Figures 6 to 11, The wiring patterns of the first to sixth layers of the packaging substrate 2. Furthermore, Fig. 11 is a schematic view showing a sixth layer wiring pattern of the back surface 2b of the packaging substrate 2 as seen from above. These wiring patterns are pattern diagrams. In Figures 7 to 11, The package substrate 2 is a diagram in which a part of the dielectric layer and the wiring layer are removed, respectively. However, in the description, the substrate 2 for packaging is described. In these schemes, The black dots indicate the through-hole 9a and the conductor 9b filled in the through-hole, The hatched part is the wiring 9.  In Figures 6 and 7, A rectangular hole 2h is provided in the center of the packaging substrate 2. 2i, The upper recess lib is formed. Simultaneously, As shown in Figure 8,  A square hole 2m is provided in the center of the packaging substrate 2. To form a lower recess 11a. The front end of the wiring 9 is arranged on the left and right of the hole 2m.  This part forms the bottom 11 bf of the upper recess lib, The front end portion of these wirings 9 is connected to the other end of one of the leads connected to the electrodes of the semiconductor wafer. The second layer shown in Figure 7, Part of the conductor 9b is separated, However, a wiring 9 serving as a first reference power source (ground layer) is disposed over substantially the entire area of the package substrate 2 outside the hole 2i.  The fourth layer shown in Figure 9, Part of the conductor 9b is separated, However, the wiring 9 serving as the first reference power source (-13-200421567 0) (ground layer) is disposed over substantially the entire area of the packaging substrate 2. The fourth layer is a surface on which the lower recessed portion 11a is formed.  therefore, A conductor 9b (through hole 9a) is densely arranged in the center of the packaging substrate 2. These densely arranged portions form a wafer mounting portion 9d on which a semiconductor wafer is fixed. The densely arranged conductor 9b runs through the fifth layer in FIG. 10, A conductive layer 9f composed of a first reference power source (ground layer) having a heat dissipation function and connected to the back surface 2b of the package substrate 2 in FIG. 11 is connected. A conductor 9b (through-hole 9a) is densely arranged on the chip mounting portion 9d at the bottom of the lower concave portion 11a of the packaging substrate 2, Then, the heat generated by the semiconductor wafer fixed on the wafer mounting portion 9d can be quickly dissipated to the outside of the product through the conductor layer 9f. Layer 5 of Figure 10, Fine stripe lines 9s, 9t. An external electrode terminal 9e is formed on the sixth layer in FIG. 11.  As shown in the second layer in Figure 7 and the fourth layer in Figure 9, Since the ground plane is arranged on a wide area of the packaging substrate 2, Grounding of the substrate can be strengthened. Furthermore, Selection of wiring materials Silver-based conductor materials.  As shown in Figure 2, As shown in Figures 4 and 5, The recessed portion 11 a and the bottom portion 11 af are located below the bottom of the lowest recessed portion of the packaging substrate 2, Via a bonding material 20 such as solder, The lower semiconductor wafer 3a is fixed. The lower semiconductor wafer 3a is as shown in FIG. 5, The two semiconductor wafers 3a are fixed side by side. That is, Although not shown, However, an electrode provided over substantially the entire area under the semiconductor wafer 3a is connected to the wafer mounting portion 9d in a tight contact state. This electrode becomes the first reference power supply potential (ground potential). The lower semiconductor wafer 3a is higher than the upper semiconductor wafer 3b, The calorific value during movement is large. And these heats are rapidly conducted from most closely-arranged conductors 9b to the conductor layer 9f. Use -14-(10) (10) 200421567 for heat dissipation.  Simultaneously, The semiconductor wafer 3a is mounted by TAB (Tape Automated Bonding) technology. that is, As shown in Figure 15, The semiconductor wafer 3a supported on the carrier tape 21 via the metal lead 22 is cut at the middle portion of the lead 22, Simultaneously, It is fixed to the bottom 11af of the lower recessed portion 11a via the bonding material 20. At this time, The outer end of the lead 22 is a wiring 9 connected to a bottom 11bf provided in the upper recessed portion lib via a bonding material 20. that is,  Via lead 22, The wiring 9 is electrically connected to the bottom surface of the middle-level recessed portion extending to the step portion of the multi-level recessed portion.  As shown in Figures 2 to 5, The upper semiconductor wafer 3b is inserted into the upper recess lib, It is mounted by flip chip connection. The upper semiconductor wafer 3b is via a bump electrode, that is, Is electrically connected to the lead 22 via the ball 25 (see FIG. 2), Alternatively, it is electrically connected to the wiring 9 provided at the bottom 11bf of the upper recessed portion lib via the ball 26 (see FIG. 4). As shown in Figure 4, Compared with the height above the line 9 of the bottom 11bf of the upper recess lib, The upper surface of the lead 22 connected to the wiring 9 is high. therefore, As the ball 26 bonded to the wiring 9, a ball thicker than the ball 25 bonded to the lead 22 is used. This height difference corresponds to the height of the thickness of the lead 22 plus the thickness of the bonding material 23, E.g, About 100 μm. The balls 25 and 26 are made of solder or gold.  Simultaneously, Although not particularly detailed, However, an insulating layer is provided on the upper semiconductor wafer 3b. Wiring is provided on this insulation layer, An electrode fixing portion 9c is provided to fix the electrode 5a of the wafer component 5 by wiring. And here a pair of electrode fixing portions 9c, • 15 · (11) (11) 200421567 electrode 5a of the wafer component 5 is fixed via the bonding material 10. Simultaneously, The height of the upper surface of the upper semiconductor wafer 3b located above the recess 11 It is substantially the same height as the surface of the packaging substrate 2. the result, The wafer component 5 can fix one electrode 5a to the electrode fixing portion 9c 'on the upper semiconductor wafer 3b, and the other electrode 5a to the electrode fixing portion 9c on the surface of the packaging substrate 2. The wafer component 5 can be mounted between the upper semiconductor wafer 3b and the package substrate 2. the result, The mounting efficiency of the wafer component 5 can be improved.  Simultaneously, A part of the electrodes of the upper semiconductor wafer 3b, In particular, the ground electrode is as shown in Figure 2. Via ball 25, Lead 22, Joint material 23, Wiring 9. Conductor 9b, Wiring 9 (wafer mounting portion 9d), Conductor 9b, It is electrically connected to the conductor layer 9f. Simultaneously, This path also becomes the path for transferring heat.  The insulating resin forming the sealing portion 6 is buried around or under the upper semiconductor wafer 3b, that is, Also bury the space with the lower semiconductor wafer 3a, It has a so-called bottom seal structure.  The semiconductor device 1 according to the first embodiment is a power amplifier module 1 configured as described above. The power amplification module 1 of the first embodiment is as shown in FIG. 12, Dividing the two frequency bands into two amplifier circuits to amplify, Each amplifier circuit is amplified in 3 stages, At this time, the amplifier circuits of each stage are controlled by the control circuit of the upper-layer control semiconductor wafer 3b.  The two frequency bands are, For example, GSM (Global System Mobile Communication) The frequency band is 880 ~ 915 MHz. While the other is DCS (Digital Communication System 1800), Band use 1710 ~ 1785 MHz, It is a module corresponding to these two methods.  (12) (12) 200421567 GSM mode amplification system, There is a first amplification stage 13 between the input terminal [Pin (GSM)] and the output terminal [Pout (GSM)]. 2nd amplification stage 14, Final magnification level 15, DCS amplification system, There is a first amplifier stage 16 between the input terminal [Pin (DCS)] and the output terminal [Pout (DCS)]. 2nd amplification stage 17, Final magnification level 18, Each amplifier stage is controlled by a control circuit 19 connected to a control terminal (Vclt). Although not shown,  The transistor (amplifying element) of the first embodiment uses a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). At this time, The control circuit 19 controls the bias voltage applied to the gates of the MOSFETs in each amplifier stage. To control the output of P out (GSM), Power of P out (DCS).  These circuits are applied with a second reference power supply voltage (Vdd).  The operating current of the final amplification stage is large, Therefore, the semiconductor wafer equipped with the transistor of the last amplification stage is more expensive than the semiconductor wafer equipped with the transistor of the first amplification stage. Its calorific value is much greater. The operating current of the second amplification stage is also larger than that of the transistor of the first amplification stage. Therefore, the amount of heat generated is also larger than that of the first amplifier stage. therefore, In the first embodiment, one of the lower semiconductor wafers 3a is a semiconductor wafer equipped with transistors of the second amplification stage and the last stage for GSM. The other side of the lower semiconductor wafer 3a is a semiconductor wafer equipped with transistors of the second amplification stage and the last stage for DCS, On the other hand, the bottom portion 11 af of the concave portion 11 a below the packaging substrate 2 is tightly mounted. On the other hand, a single chip is used to assemble a semiconductor chip that has a relatively small amount of heat and constitutes the first amplifier stage for GSM and DCS and the control circuit 19, It serves as the upper semiconductor wafer 3b.  Each amplification stage is composed of a transistor, Structures such as bias circuits or input matching circuits -17- (13) (13) 200421567. These circuits are made up of capacitive elements, It consists of a resistance element and an inductor.  therefore, By using a specified number of chip resistors, Chip capacitors and chip inductors, Then, the circuit shown in FIG. 12 can be formed.  Secondly, Referring again to the schematic diagrams of FIGS. 13 to 19, A method for manufacturing the power amplifier module 1 according to the first embodiment will be described. Fig. 13 is a schematic perspective view of a wiring mother substrate for manufacturing a semiconductor device according to the first embodiment;  FIG. 14 is a schematic cross-sectional view of a product forming portion of the wiring mother substrate,  Fig. 15 is a schematic cross-sectional view of the product forming portion on which a semiconductor wafer is mounted, FIG. 16 is a schematic cross-sectional view of the above-described product forming portion on which the semiconductor wafer is mounted in an overlapping manner. Fig. 17 is a schematic cross-sectional view of the product forming portion on which the wafer component is mounted, FIG. 18 is a schematic cross-sectional view of the product forming portion forming the insulating resin layer for forming a sealing portion, Fig. 19 is a cross-sectional view of a semiconductor device formed by cutting a wiring mother substrate.  First of all, As shown in Figure 13, The above-mentioned wiring mother substrate 30 is prepared. Fig. 14 is an enlarged sectional view showing the product forming portion 31. Since then, To Figure 18, The description will be made with reference to the single product forming section 31. In the figure, The part between a pair of two dotted lines is the product forming part 31.  As shown in Figure 14 A recessed portion 11 (two-layer recessed portion) as described above is formed in the center of the surface of each product forming portion 31. therefore, As shown in Figure 15,  The lead wire 22 is cut from the carrier tape 21 at a dotted line portion, The semiconductor wafer 3a is separated from the carrier tape 21, Simultaneously, An electrode portion (not shown) under the semiconductor wafer 3a in the lower layer is fixed to the bottom 11af of the recessed portion 11a below the recessed portion 11 via the bonding material 20. Simultaneously, The outer end of the lead 22 is connected to the wiring 9 provided at the bottom 11bf of the upper recessed portion 11b via the bonding material 23.  -18- (14) (14) 200421567 Then, As shown in Figure 16, Insert the upper semiconductor wafer 3b into the upper recess lib, The upper semiconductor wafer 3b is connected via a ball 25 and a ball 26 (see FIG. 4) to the wiring 9 mounted on the bottom 11bf formed in the upper recessed portion lib by a guide wafer method. In this state, The upper surface of the upper semiconductor wafer 3b and the surface 2a of the packaging substrate 2 are substantially at the same height.  then, As shown in Figure 17, On the upper semiconductor wafer 3b, A chip component 5 is mounted on a surface 2 a of the packaging substrate 2. The wafer component 5 connects the electrodes 5a on both ends to the upper surface of the semiconductor wafer 3b provided on the upper layer or the electrode fixing portion 9c on the surface 2a of the packaging substrate 2 via the bonding material 10.  At this time, Since the upper surface of the upper semiconductor wafer 3b and the surface of the packaging substrate 2 are substantially at the same height, therefore, One electrode 5a of the wafer component 5 can be fixed to the electrode fixing portion 9c on the upper semiconductor wafer 3b, The other electrode 5a is fixed to an electrode fixing portion 9c on the surface of the packaging substrate 2. With this, The area in which the wafer component 5 is mounted can be expanded. the result, Can carry more chip parts5, If it is equipped with a limited number of chip parts, The size of the packaging substrate 2 can be reduced, The power amplification module 1 can also be miniaturized.  then, As shown in Figure 18, An insulating resin layer 28 having a predetermined thickness is formed on the surface 2a side of the packaging substrate 2 to cover the wafer component 5 described above.  The insulating resin layer forming the insulating resin layer 28 may be buried around or under the upper semiconductor wafer 3b, that is, It is also possible to bury the space with the lower semiconductor wafer 3a, It has a so-called bottom seal structure.  -19- (15) (15) 200421567 Then, Along the cutting line 3 2a in Fig. 13, 3 2b Cut the wiring mother substrate 30 together with the insulating resin layer 28, Thereby, a plurality of semiconductor devices (power amplifier modules) 1 as shown in FIG. 19 can be manufactured simultaneously.  Fig. 20 is a schematic sectional view showing a mounted state of the completed semiconductor device 1. The mounting substrate 40 such as a mother substrate is constituted by, for example, a PCB (priiited circuit board), The back of the surface and its opposite, And its internal wiring 40a, Simultaneously, The predetermined wiring 40a is electrically connected together via a conductor 40b filled in a through hole. This mounting substrate 40 corresponds to the conductive layer 9f and the external electrode terminal 9e of the first embodiment. There is a wiring area 40e composed of the wiring 40a. the result, When mounting the semiconductor device 1, The external electrode terminal 9e and the conductor layer 9f can be connected to the wiring region 40e of the mounting substrate 40 via a bonding material 41 such as solder. The heat generated in the lower semiconductor wafer 3a can pass through the bonding material 20, Wafer mounting section 9d, Conductor 9b, Conductor layer 9f, Bonding material 41, Rapid conduction to the wiring area 40e,  For cooling.  The semiconductor device 1 of the first embodiment has the following effects.  (1) Because in the recessed portion 11 provided on the surface 2a side of the packaging substrate 2, The semiconductor wafers 3a, 3b, therefore, Compared with a structure in which semiconductor wafers are arranged in a plane, Can increase installation density.  (2) Because in the recessed portion 11 provided on the surface 2a side of the packaging substrate 2, The semiconductor wafers 3a, 3b, therefore, Compared with a structure in which semiconductor wafers are arranged in a plane, The area of the packaging substrate 2 can be reduced, The miniaturization of the semiconductor device 1 is achieved.  (3) Because the upper semiconductor wafer 3b is also equipped with wafer zero -20 · (16) (16) 200421567 pieces 5, Therefore, the mounting density can be increased or the size of the semiconductor device 1 can be reduced. The electrodes of the wafer component 5 mounted on the upper semiconductor wafer 3b may also be used. It is connected to the internal wiring of the upper semiconductor wafer 3b.  (4) Because the upper surface of the upper semiconductor wafer 3b and the surface 2a of the packaging substrate 2 are substantially the same height, Therefore, one electrode 5a of the wafer component 5 can be fixed to the electrode fixing portion 9c of the upper semiconductor wafer 3b. The other electrode 5a is fixed to the electrode fixing portion 9c on the surface 2a of the packaging substrate 2, The wiring of the upper semiconductor wafer 3b and the wiring of the surface 2a of the packaging substrate 2 are connected via the wafer component 5. Simultaneously,  The boundary part between the upper semiconductor wafer 3b and the packaging substrate 2 may be equipped with a chip component 5, Therefore, the mounting density can be further increased or the size of the semiconductor device 1 can be reduced.  (5) Because you can pass the ball 25 balls 26, Even the wiring 9 or the conductor 9b inside the packaging substrate 2, Lead the ground of the upper semiconductor wafer 3b to the conductor layer 9f at a short distance, Therefore, the impedance of the ground of the upper semiconductor wafer 3b can be reduced.  (6) With the above (5), Since the wiring 9 or the conductor 9b in the packaging substrate 2 is formed of a metal (formed with a metal paste) having good thermal conductivity, therefore, The upper semiconductor wafer 3b also has good heat dissipation properties.  (7) The lower semiconductor wafer 3a is tightly connected to the bottom of the recess 11 of the packaging substrate 2, At the same time, a plurality of conductors 9b are closely arranged at the bottom to transfer heat to the conductor layer 9f. therefore, Even if the heat generation amount of the semiconductor wafer 3a in the lower layer is large, 1 is stable operation.  (8) On the packaging substrate 2, Because the number of through-holes through the entire layer (17) (17) 200421567 will be reduced, Can ensure a large area of the wiring area of the inner layer, It is possible to increase the wiring density of the substrate. This also enables miniaturization of the packaging substrate 2.  (9) Each wiring layer consists of a conductor layer 9f which becomes the first reference power source (ground potential), Connected to a low impedance state through a plurality of through holes 9a and conductors 9b,  Can strengthen the grounding of the entire substrate, therefore, The semiconductor device 1 can operate stably.  (10) Since the semiconductor wafer 3a in the lower layer is a semiconductor wafer 3a including a transistor constituting the power amplifier module 1, Let the upper semiconductor wafer 3b be a semiconductor wafer containing transistors that constitute the first amplifier stage or control circuit 19, So it can provide small size, High installation density, A power amplifier module 1 capable of stable operation.  (Embodiment 2) Figure 21 is a schematic cross-sectional view showing a semiconductor device according to another embodiment (Embodiment 2) of the present invention. The semiconductor device 1 according to the second embodiment is the same as the first embodiment. Is to apply this invention to contain: Semiconductor wafer 3a (first mounting part) with high heat generation such as power amplifier module, The semiconductor device 1 is a semiconductor wafer 3b (second mounting component) having a smaller heat generation amount than the semiconductor wafer 3a.  The semiconductor device 1 of the second embodiment is The recess 11 provided on the surface 2a of the packaging substrate 2 adopts a single-layer structure. At the bottom of this recess, Similar to the first embodiment, A structure in which the semiconductor wafer 3 a is closely attached via the bonding material 20.  The upper surface of the mounted semiconductor wafer 3a, The height of the surface -22- (18) (18) 200421567 2a of the packaging substrate 2 is substantially the same. At this time, To make the heights the same, A good thermal conductivity is provided under the semiconductor wafer 3a. A layer of adhesive with good electrical conductivity (for example, a thickness of about 50 μm), By adjusting the thickness of this cement, In order to adjust the height of the semiconductor wafer 3a. This method can also be applied to the first embodiment.  Simultaneously, An intermediate wiring board 45 is mounted on the upper surface of the semiconductor wafer 3a and the surface 2a of the packaging substrate 2 (for electrical connection and mounting on the surface, Substrate of electrical parts on the back: Plug into the middle wiring board), A semiconductor wafer 3b is mounted on the intermediate wiring board 45 in a flip-chip manner. Simultaneously, On the surface 2a of the packaging substrate 2, As in the first embodiment, a chip component 5 (a second mounting component) is mounted.  The upper and lower electrodes of the intermediate wiring board 45 are electrically connected through wiring provided on the surface and the inside. The wiring between the above-mentioned first mounting parts and the package substrate is electrically connected via the intermediate wiring board 45. that is, The intermediate wiring board 45 has electrodes 45a on the top and bottom,  45b or wiring 45c. The semiconductor wafer 3b located above has an electrode 3e on the lower side and a protruding electrode (bump electrode) 3f on its surface. The protruding electrode 3f of the semiconductor wafer 3b is an electrode 45a or a wiring 45c mounted on the upper surface of the intermediate wiring board 45 in a flip-chip manner.  The semiconductor wafer 3a mounted on the bottom of the recess 11 has electrodes 3s on it, At the same time there is a protruding electrode (bulk electrode) 3t on its surface. and, These protruding electrodes 3t are electrodes 45b connected below the intermediate wiring board 45. The middle wiring board 45 is larger than the recessed portion 11, An electrode 45b provided on the intermediate wiring board 45 protruding from the recessed portion 11 is an electrode 2e connected to the surface 2a of the package substrate 2 (19) (19) 200421567 via the protruding electrode 2f. The protruding electrode 2f is provided in advance on the electrode 2e. Each of these parts is mounted by reflow treatment of the bonding material or the protruding electrode once or several times.  Although not shown, but, Due to the bottom seal between the overlapping parts, Can improve usability or reliability. Simultaneously, Alternatively, it may be on the surface 2a of the packaging substrate 2, To cover wafer parts 5, Semiconductor wafer 3a,  3b, The intermediate wiring board 45 forms a sealing portion 6 in a shape.  In the second embodiment, The back surface 2b of the packaging substrate 2 is provided with a conductor layer 9f serving as a first reference power source, which also has a heat dissipation function. The electrodes provided under the semiconductor wafer 3a (first mounting part) located below are provided through the bonding material 20, Wafer mounting section 9d, The conductor 9b is electrically connected to the conductor layer 9f °. The package substrate 2 according to the second embodiment is smaller than the package substrate 2 according to the first embodiment. Can reduce the number of dielectric and conductor layers (wiring layers), The manufacturing cost of the semiconductor device 1 can be reduced.  The semiconductor wafer 3a of the semiconductor device 1 according to the second embodiment,  3b, The degree of freedom in wiring connection of the packaging substrate 2 is large, Can respond to complex bias circuits, Matching circuits, etc. It has the effect of improving product performance.  The semiconductor device 1 of the second embodiment has the same effects as those of the first embodiment.  (Embodiment 3) FIG. 22 is a schematic cross-sectional view of a (20) (20) 200421567 semiconductor device showing another embodiment (Embodiment 3) of the present invention. Fig. 23 is a partially enlarged sectional view showing an electrode rewiring structure of an upper semiconductor wafer mounted on a semiconductor integrated circuit device according to the third embodiment.  The semiconductor device 1 according to the third embodiment is the same as the first embodiment.  Applying this invention to, contain: Semiconductor chip 3a (first mounting part) with high heat generation such as power amplifier module, A semiconductor device 1 having a semiconductor wafer 3b (second mounting component) having a smaller heat generation amount than the semiconductor wafer 3a.  In the semiconductor device 1 of the third embodiment, a semiconductor wafer 3b is used instead of the intermediate wiring board of the semiconductor device 1 of the second embodiment. that is, In the semiconductor wafer 3b, a wiring layer 50 is further disposed under the electrode, Here, the surface of the wiring layer 50 is further provided with a bump electrode (bump electrode) 51.  Because of the rearrangement on the surface of the semiconductor wafer 3b, Each of the rearranged protruding electrodes 51 can be connected to an electrode 3s on the semiconductor wafer 3a mounted on the bottom of the recessed portion 11, Or the electrode 2e of the surface 2a of the packaging substrate 2.  The rearranged bump electrode 51 and the rearranged wiring layer 50 are as shown in FIG. Fig. 23 is a diagram schematically showing a part of the semiconductor wafer 3b. On the surface portion of the semiconductor substrate portion 53 constituting the semiconductor wafer 3b, An electrode pad 52 is provided to cover the periphery of the electrode pad 52 with an insulating protective film 54.  This electrode pad 52 is traditionally used as an external electrode terminal, It is, for example, a part where wire bonding is performed.  In the third embodiment, A rewiring 55 made of a conductor connected at one end to the electrode pad 52 is selectively provided on the insulating protective film 54. Simultaneously,  An insulating film 56 that selectively covers the rewiring 55 is formed on the insulating protective film 54. The other end of the electrode pad 52 is exposed, A rearranged bump electrode 51 composed of bump electrodes -25- (21) (21) 200421567 (bump electrode) is formed in this portion. The rewiring 55 can be formed in a desired pattern on the insulating protective film 54.  On the back surface 2b of the packaging substrate 2 in this embodiment 3 ', a conductor layer 9f, which serves as a first reference power source, is also provided. The electrode provided under the semiconductor wafer 3a (first mounting part) located below is via a bonding material 20, Wafer mounting section 9d, The conductor 9b is electrically connected to the conductor layer 9f.  The semiconductor device 1 of the third embodiment does not require an intermediate wiring board. Can be thinned. because, No intermediate wiring board 45 is required, Therefore, manufacturing can be further reduced! cost.  The semiconductor device 1 of the third embodiment has the same effect of improving the performance as the second embodiment.  The semiconductor device 1 of the third embodiment also has the same effects as the first embodiment.  (Embodiment 4) Fig. 24 is a schematic cross-sectional view showing a semiconductor device according to another embodiment (Embodiment 4) of the present invention.  The semiconductor device 1 according to the fourth embodiment is the semiconductor device 1 according to the first embodiment. The electrodes 3s of the semiconductor wafer 3a mounted on the bottom 11f of the recessed portion 11a of the recessed portion (two-level recessed portion) 11 are electrically connected by a conductive metal wire 7, And set. Wiring 9 bf at the bottom 11 of the upper recess lib. At the same time, the electrodes of the semiconductor wafer 3b are electrically connected to wirings 9bf at the bottom 11bf of the upper recessed portion 11b via a ball 25. The structure of other parts is the same as that of the semiconductor device 1 of the first embodiment. -26-(22) (22) 200421567 In the third embodiment, a back surface 2b of the packaging substrate 2 is provided with a conductive layer 9f that serves as a first reference power source, and is provided on the lower semiconductor wafer 3a (the 1 Mounting parts) The electrodes below are electrically connected to the conductor layer 9f via the bonding material 20, the chip mounting portion 9d, and the conductor 9b. At the same time, the electrodes of the semiconductor wafer 3b located above are also electrically connected to the conductor layer 9f via the ball 25, the wiring 9, the conductor 9b, the wiring 9, and the conductor 9b. The semiconductor device 1 of the fourth embodiment has the same effects as those of the first embodiment. (Embodiment 5) Figure 25 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 5) of the present invention. The semiconductor device 1 according to the fifth embodiment is the semiconductor device 1 according to the first embodiment. The concave portion 11 includes the lowermost concave portion 11x, the middle concave portion lly, and the uppermost concave portion 11z. The lowermost recessed portion 11x is the same as the lower recessed portion 11a of the fourth embodiment, and the semiconductor wafer 3a (the first mounting component) is tightly mounted on the lowest recessed portion 11x via the bonding material 20. At the same time, the electrode 3s on the semiconductor wafer 3a is electrically connected to the conductive layer 9f provided on the bottom of the middle-level recessed portion (the bottom of the first middle-level recessed portion of the stepped portion of the multi-level recessed portion) via the metal wire 7 as in the fourth embodiment. The lower periphery of the semiconductor wafer 3b (the first mounting part) located on the upper side is placed, and the bottom of the uppermost recess llz is located at a position lower than the first middle recess -27- (23) (23) 200421567. 2 bottom of the middle recess), and fixed through the bonding material 61. The electrode 3u on the semiconductor wafer 3b is electrically connected to the wiring 9 provided at the bottom of the uppermost recessed portion 11z (the bottom of the second middle-layer recessed portion) via a conductive metal wire 7. At the same time, a chip component 5 is mounted on the surface 2a of the packaging substrate 2 with the same structure as that of the first embodiment. At the same time, a sealing portion 6 is provided on the surface 2a of the packaging substrate 2 to cover the semiconductor wafers 3a, 3b or the wafer component 5. The space between the semiconductor wafer 3a and the semiconductor wafer 3b is also filled with an insulating resin constituting the sealing portion 6. In the fifth embodiment, the back surface 2b of the packaging substrate 2 is provided with a conductive layer 9f having a heat dissipation function and serving as a first reference power source. The material 20, the chip mounting portion 9d, and the conductor 9b are electrically connected to the conductor layer 9f. At the same time, the electrodes of the semiconductor wafer 3b located above are also electrically connected to the conductor layer 9f via the metal wires 7, the wires 9, the conductors 9b, and the conductors 9b. The semiconductor device 1 according to the fifth embodiment has the same effects as those of the first embodiment. In addition, the semiconductor wafers 3a, 3b do not need to have positional precision in the height direction of the packaging substrate 2, and have the effect that they can be easily assembled. The invention completed by the present inventors has been specifically described based on the embodiments, but the present invention is not limited to the embodiments described above, and various changes can be made without departing from the scope of the invention. The present invention can be widely applied to a hybrid integrated circuit device in which a plurality of semiconductor wafers are mounted on the surface side of a packaging substrate in multiple layers, and a structure of the wafer components is mounted. At this time, the transistor mounted on the semiconductor wafer may be other insulating gate transistors such as silicon oxide film gate type and nitride film, and other silicon transistors such as bipolar transistors or various transistors made of compounds. can. The effects that can be obtained by the representative of the inventions disclosed in this application are listed below. (1) By increasing the mounting density of mounted components, miniaturization of semiconductor devices can be achieved. (2) It is possible to provide a semiconductor device capable of securing a large area of the inner layer wiring of a package substrate. (3) A semiconductor device capable of achieving stabilization of the first reference potential (ground potential) can be provided. (4) A semiconductor device capable of improving the heat dissipation property of a semiconductor wafer having a large amount of heat can be provided. (5) A semiconductor device capable of stable operation can be provided. (6) Power amplifier modules can be provided for stable operation. As described above, the semiconductor device of the present invention can consider the heat dissipation property and mount a plurality of semiconductor wafers having different heat generation amounts on the packaging substrate, respectively. Therefore, the semiconductor device can operate stably. At the same time, when semiconductor chips are mounted separately, semiconductor chips are mounted in an overlapping manner ', so that miniaturization of semiconductor devices can be achieved, and it is most suitable for high-frequency integrated circuit devices for portable telephones. Therefore, when the present invention is applied to a power amplifier module, it can provide a small, lightweight, and stable power amplifier module. [Brief description of the figure] -29 · (25) (25) 200421567 Figure 1 shows A plan view of the appearance of a semiconductor device (power amplification module) according to an embodiment (Embodiment 1) of the present invention. FIG. 2 is a cross-sectional view showing the internal structure of the semiconductor device. Fig. 3 is an enlarged plan view of the semiconductor device with the sealed body removed. Fig. 4 is a sectional view taken along line Y-Y in Fig. 3; Fig. 5 is a plan view of the semiconductor device in which a sealed body and an upper semiconductor wafer are removed. Fig. 6 is a schematic view showing a first-layer wiring pattern of the package substrate for the semiconductor device. Fig. 7 is a schematic diagram showing a second layer wiring pattern of the above-mentioned package substrate. Fig. 8 is a schematic diagram showing a third layer wiring pattern of the above-mentioned package substrate. Fig. 9 is a schematic diagram showing a fourth layer wiring pattern of the above-mentioned package substrate. Fig. 10 is a schematic diagram showing a fifth layer wiring pattern of the above-mentioned package substrate. Fig. 11 is a schematic view showing a sixth-layer wiring pattern seen through the back surface of the packaging substrate from the upper side. Fig. 12 is a block diagram showing a circuit structure of a semiconductor device according to the first embodiment. Fig. 13 is a schematic perspective view of a wiring mother substrate for manufacturing a semiconductor device according to the first embodiment. 30- (26) (26) 200421567 Fig. 14 is a schematic sectional view of a product forming portion of the wiring mother substrate. Fig. 15 is a schematic cross-sectional view of the product forming portion on which the semiconductor wafer is mounted. Fig. 16 is a schematic cross-sectional view of the above-mentioned product forming portion on which the semiconductor wafer is mounted in an overlapping manner. Fig. 17 is a schematic cross-sectional view of the product forming portion on which the wafer component is mounted. Fig. 18 is a schematic cross-sectional view of the above-mentioned product forming portion forming the insulating resin layer for forming a sealing portion. Fig. 19 is a cross-sectional view of a semiconductor device formed by cutting a wiring mother substrate. Fig. 20 is a schematic cross-sectional view showing a mounted state of the semiconductor device according to the first embodiment. Fig. 21 is a schematic cross-sectional view showing a semiconductor device according to another embodiment (Embodiment 2) of the present invention. Fig. 22 is a schematic cross-sectional view showing a semiconductor device according to another embodiment (Embodiment 3) of the present invention. Fig. 23 is a partially enlarged sectional view showing an electrode rewiring structure of an upper semiconductor wafer mounted on the semiconductor integrated circuit device according to the third embodiment. Fig. 24 is a schematic cross-sectional view showing a semiconductor device according to another embodiment (Embodiment 4) of the present invention. Fig. 25 is a schematic cross-sectional view of a semiconductor device according to another embodiment (Embodiment 5) of the present invention (31)-(27) (27) 200421567. [Comparison table of main components] 1: Semiconductor device 2: Packaging substrate 2a: Front surface 2b: Back surface 2f, 3f, 3t: Bump electrodes 2e, 3e, 3s, 5a: Electrodes 2h, 2i ·· L 3a, 3b: Semiconductor wafer 5: Wafer part 6: Sealing part 7: Metal wire 9: Wiring 9a: Through hole 9b: Conductor 9c: Electrode fixing part 9d: Wafer mounting part 9e: External electrode terminal 9f: Conductor layer 10: Bonding material 11: Recess 11a: Lower recess -32- (28) (28) 200421567 lib: Upper recesses llaf, llbf ... Bottom 1 9: Control circuit 21: Carrier tape 22: Leads 23, 41, 61: Bonding materials 25, 26 : Ball 30: Wiring mother substrate 3 1: Product forming portions 32 a and 32 b: Cutting line 40: Mounting substrates 40 a and 45 c: Wiring 40 b · Conductor 4 0: Wiring area 45: Intermediate wiring boards 45 a and 45 b: Electrode 5 0: Redistribution of wiring layer 5 1: Redistribution of protruding electrode 52: Electrode pad 53: Semiconductor substrate portion 54: Insulating protective film 55: Redistribution 56: Insulating film-33 ·

Claims (1)

200421567 Ο) 拾、申請專利範圍 1· 一種半導體裝置，其特徵爲，具備有： 具有成爲表面及其相反側的安裝面的背面具有配線的 封裝用基板； 由主動元件構成，且成上下重疊狀搭載於上述封裝用 基板的複數個第1安裝零件； 設在上述封裝用基板背面的複數個外部電極端子；以 及 設在上述封裝用基板的表面側，被覆上面第1安裝零 件的絕緣性樹脂構成的密封部， 位於下方的上述第1安裝零件是密接安裝在上述封裝 用基板， 位於下方的上述第1安裝零件是發熱量較位於上方的 上述第1安裝零件的發熱量大的零件。 2·如申請專利範圍第1項所述之半導體裝置，其中 具有由被動元件構成，且搭載於上述封裝用基板表面 的複數個第2安裝零件。 3·如申請專利範圍第1項所述之半導體裝置，其中 上述複數個第1安裝零件是配置在設於上述封裝用基 板表面的凹部內， 位於上述凹部內上方的上述第1安裝零件的上面與上 述封裝用基板的表面大致上同高。 4.如申請專利範圍第3項所述之半導體裝置，其中 上述第2安裝零件搭載於上述位於上方的第1安裝零 (2) (2)200421567 件的上面。 5·如申請專利範圍第3項所述之半導體裝置，其中 上述第2安裝零件搭載於，上述位於上方的第1安裝 零件的上面到上述封裝用基板的表面。 6·如申請專利範圍第3項所述之半導體裝置，其中 上述凹部是多層次凹部， 位於下方的上述第1安裝零件是固定在最下位的凹部 底，上述位於下方的第1安裝零件上面的電極是經由導電 性引線，成電氣方式連接在延伸於多層次凹部的台階部分 的中層凹部底上面的配線， 上述位於上方的第1安裝零件的電極是電氣方式連接 在上述引線。 7·如申請專利範圍第3項所述之半導體裝置，其中 上述凹部是多層次凹部， 位於下方的上述第1安裝零件是固定在最下位的凹部 底，上述位於下方的第1安裝零件上面的電極是經由導電 性引線，成電氣方式連接在延伸於多層次凹部的台階部分 的中層凹部底上面的配線， 上述位於上方的第1安裝零件的電極，是經由突起電 極電氣方式連接在上述引線及設於中層凹部底的配線， 連接在設於上述中層凹部底的配線的上述突起電極的 厚度，較連接在上述引線的上述突起電極的厚度爲厚。 8.如申請專利範圍第6項所述之半導體裝置，其中 上述位於上方的第1安裝零件的電極，是經由導電性 -35· 200421567 Ο) 的球連接在上述引線。 9·如申請專利範圍第3項所述之半導體裝置，其中 在上述封裝用基板的表面、背面、凹部底及內部分別 設有規定圖案的配線，同時，此等配線的一部分是經由塡 充在設於封裝用基板的孔內導體，成電氣方式相連接。 10·如申請專利範圍第1項所述之半導體裝置，其中 在上述封裝用基板的背面，設有兼具散熱功能的成爲 第1基準電源的導體層，設在上述位於下方的第1安裝零 件下面的電極，成電氣方式連接在上述導體層。 11·如申請專利範圍第10項所述之半導體裝置，其中 上述位於下方的第1安裝零件的下面電極，是經由塡 充在複數個通孔的上述導體連接在上述導體層。 12.如申請專利範圍第1〇項所述之半導體裝置，其中 上述位於上方的第1安裝零件的電極的一部分，是電 氣方式連接在上述導體層。 13· —種半導體裝置，其特徵爲，具備有： 具有成爲表面及其相反側的安裝面的背面，同時在上 述表面有凹部，且有配線的封裝用基板； 由主動元件構成，且成上下重疊狀搭載於上述凹部內 的複數個第1安裝零件； 由被動元件構成，搭載於上述封裝用基板的表面及上 述位於上方的第1安裝零件上面的複數個第2安裝零件； 設在上述封裝用基板背面的複數個外部電極端子； 設在上述封裝用基板背面，兼具散熱功能的成爲第1 -36- (4) (4)200421567 基準電源的導體層；以及 設在上述封裝用基板的表面側，被覆上面第1及第2 安裝零件的絕緣性樹脂構成的密封部， 位於上述凹部內上方的上述第1安裝零件的上面，與 上述封裝用基板的表面大致上同高， 位於下方的上述第1安裝零件，是密接安裝在上述封 裝用基板， 位於下方的上述第1安裝零件，是發熱量較位於上方 的上述第1安裝零件的發熱量大的零件， 上述位於下方的第1安裝零件的下面電極，是經由塡 充在通孔的導體電氣方式連接在上述導體層， 上述位於上方的第1安裝零件的電極的一部分，是電 氣方式連接在上述導體層。 14·如申請專利範圍第13項所述之半導體裝置，其中 上述凹部是多層次凹部， 位於下方的上述第1安裝零件是固定在最下位的凹部 底，上述位於下方的第1安裝零件的上面的電極是經由導 電性引線，成電氣方式連接在延伸於多層次凹部的台階部 分的台階凹部底上面的配線， 上述位於上方的第1安裝零件的電極，是經由導電性 的球電氣方式連接在上述引線。 15. —種半導體裝置，其特徵爲，具備有： 具有成爲表面及其相反側的安裝面的背面具有配線的 封裝用基板； -37- (5) (5)200421567 由主動元件構成，且成上下重疊狀搭載於上述封裝用 基板的複數個第1安裝零件；以及 由被動元件構成，且搭載於上述封裝用基板的表面的 複數個第2安裝零件； 在位於下方的第1安裝零件與位於上方的第1安裝零 件間，夾裝有上下面分別有電極的中間配線板，上述中間 配線板的上下面的電極是經由設在內部的配線成電氣方式 相連接，而藉由上述中間配線板將位於上下的上述第1安 裝零件及封裝用基板的配線電氣方式連接在一起。 16·如申請專利範圍第15項所述之半導體裝置，其中 位於下方的上述第1安裝零件，是配置在設於上述封 裝用基板的表面的凹部內， 位於下方的上述第1安裝零件的上面，與上述封裝用 基板的表面大致上同高。 17. 如申請專利範圍第15項所述之半導體裝置，其中 在上述封裝用基板的背面，設有兼具散熱功能的成爲 第1基準電源的導體層，設在上述位於下方的第1安裝零 件下面的電極，是電氣方式連接在上述導體層。 18. —種半導體裝置，其特徵爲，具備有： 具有成爲表面及其相反側的安裝面的背面具有配線的 封裝用基板； 由主動元件構成，且成上下重疊狀搭載於上述凹部內 的複數個第1安裝零件；以及 由被動元件構成，搭載於上述封裝用基板表面的複數 -38 - (6) (6)200421567 個第2安裝零件， 位於下方的上述第1安裝零件，經由設在下面的電極 搭載於上述封裝用基板， 位於上方的上述第1安裝零件，經由接合材將設在下 面的電極分別連接在上述封裝用基板，及上述位於下方的 第1安裝零件的電極。 19. 如申請專利範圍第18項所述之半導體裝置，其中 位於下方的上述第1安裝零件，配置在設於上述封裝 用基板的表面的凹部內， 位於下方的上述第1安裝零件的上面，與上述封裝用 基板的表面大致上同高， 在上述封裝用基板的背面，設有兼具散熱功能的成爲 第1基準電源的導體層，設在上述位於下方的第1安裝零 件下面的電極，是電氣方式連接在上述導體層 20. —種半導體裝置，其特徵爲，具備有： 具有成爲表面及其相反側的安裝面的背面具有配線的 封裝用基板； 由主動元件構成，且成上下重疊狀搭載於設在上述封 裝用基板表面的凹部內的複數個第1安裝零件； 由被動元件構成，搭載於上述封裝用基板的表面的複 數個第2安裝零件； 設在上述封裝用基板背面的複數個外部電極端子；以 及 設在上述封裝用基板的表面側，被覆上述第1及第2 -39· (7) (7)200421567 安裝零件的絕緣性樹脂構成的密封部， 上述凹部是多層次凹部，位於下方的上述第1安裝零 件，是經由下面電極固定在最下位的凹部底，上述位於下 方的第1安裝零件的上面的電極，是經由導電性引線，成 電氣方式連接在延伸於多層次凹部的台階部分的中層凹部 底上面的配線， 位於下方的第1安裝零件的電極，是經由突起電極電 氣方式連接在上述引線及設於中層凹部底的配線， 位於下方的上述第1安裝零件，是發熱量較位於上方 的上述第1安裝零件的發熱量大的零件。 21·如申請專利範圍第20項所述之半導體裝置，其中 在上述封裝用基板的背面，設有兼具散熱功能的成爲 第1基準電源的導體層， 上述封裝用基板的最下位凹部底設有複數個通孔，同 時在該通孔塡充有導體， 上述位於下方的上述第1安裝零件的下面電極，是經 由上述導體電氣方式連接在上述導體層。 22. —種半導體裝置，其特徵爲，具備有： 具有成爲表面及其相反側的安裝面的背面具有配線的 封裝用基板； 由主動元件構成，且成上下重疊狀搭載於設在上述封 裝用基板表面的凹部內的複數個第1安裝零件； 由被動元件構成，搭載於上述封裝用基板的表面的複 數個第2安裝零件； •40- 200421567 ⑻ 設在上述封裝用基板背面的複數個外部電極端子；以 及 設在上述封裝用基板的表面側，被覆上述第1及第2 安裝零件的絕緣性樹脂構成的密封部， 上述凹部是多層次凹部，位於下方的上述第1安裝零 件，是經由下面電極固定在最下位的凹部底，上述位於下 方的第1安裝零件的上面的電極，是經由導電性引線，成 電氣方式連接在延伸於多層次凹部的台階部分的第1中層 凹部底上面的配線， 位於上方的上述第1安裝零件的下面周邊，是連接在 位於較上述第1中層凹部底爲上方的第2中層凹部底， 位於上方的第1安裝零件上面的電極，是經由導電性 引線，連接設於上述第2中層凹部底的配線， 位於下方的上述第1安裝零件，是發熱量較位於上方 的上述第1安裝零件的發熱量大的零件。 23·如申請專利範圍第22項所述之半導體裝置，其中 在上述封裝用基板的背面，設有兼具散熱功能的成爲 第1基準電源的導體層， 上述封裝用基板的最下位凹部底設有複數個通孔，同 時在該通孔塡充有導體， 上述位於下方的上述第1安裝零件的下面電極，是經 由上述導體電氣方式連接在上述導體層。 -41 -200421567 〇) Patent application scope 1. A semiconductor device, comprising: a packaging substrate having wiring on the back and a mounting surface on the opposite side, and a mounting surface on the opposite side; a semiconductor substrate, which is composed of an active device and overlaps vertically A plurality of first mounting components mounted on the packaging substrate; a plurality of external electrode terminals provided on a back surface of the packaging substrate; and an insulating resin provided on a front side of the packaging substrate and covering the first mounting components In the sealing portion, the first mounting component located below is closely mounted on the packaging substrate, and the first mounting component located below is a component having a larger amount of heat than the first mounting component located above. 2. The semiconductor device according to item 1 of the scope of patent application, wherein the semiconductor device includes a plurality of second mounting parts made of a passive element and mounted on the surface of the packaging substrate. 3. The semiconductor device according to item 1 of the scope of patent application, wherein the plurality of first mounting parts are arranged in a recessed portion provided on the surface of the packaging substrate, and above the first mounting part located above the recessed portion. It is substantially the same height as the surface of the above-mentioned packaging substrate. 4. The semiconductor device according to item 3 of the scope of patent application, wherein the second mounting part is mounted on the above-mentioned first mounting zero (2) (2) 200421567. 5. The semiconductor device according to item 3 of the scope of patent application, wherein the second mounting component is mounted on the upper surface of the first mounting component positioned above to the surface of the packaging substrate. 6. The semiconductor device according to item 3 of the scope of the patent application, wherein the recessed portion is a multi-level recessed portion, the first mounting component located below is fixed to the bottom of the lowest recessed portion, and the first mounting component located above is positioned above the first mounting component located below. The electrodes are electrically connected to the bottom surface of the middle-level recessed portion extending through the stepped portion of the multi-level recessed portion through the conductive lead, and the electrode of the first mounting part located above is electrically connected to the lead. 7. The semiconductor device according to item 3 of the scope of patent application, wherein the recessed portion is a multi-level recessed portion, the first mounting component located below is fixed to the bottom of the lowest recessed portion, and the first mounting component located above is positioned above the first mounting component located below. The electrode is a wiring electrically connected to the bottom of the middle recessed portion extending from the stepped portion of the multi-layered recessed portion through a conductive lead. The electrode of the first mounting part located above is electrically connected to the lead and the lead through a protruding electrode. The thickness of the wiring provided on the bottom of the middle-level recessed portion is greater than the thickness of the protruding electrode connected to the wiring provided on the bottom of the middle-level recessed portion. 8. The semiconductor device according to item 6 of the scope of patent application, wherein the electrode of the first mounting part located above is connected to the lead wire via a conductive -35 · 200421567 〇) ball. 9. The semiconductor device according to item 3 of the scope of patent application, wherein a predetermined pattern of wiring is provided on the surface, the back surface, the bottom of the recess, and the inside of the packaging substrate, and a part of these wirings is filled through The conductors provided in the holes of the package substrate are electrically connected. 10. The semiconductor device according to item 1 of the scope of application for a patent, wherein a conductive layer serving as a first reference power source having a heat dissipation function is provided on a back surface of the packaging substrate, and the first mounting part is positioned below The lower electrode is electrically connected to the above-mentioned conductor layer. 11. The semiconductor device according to item 10 of the scope of patent application, wherein the lower electrode of the first mounting part located below is connected to the conductor layer through the conductor filled in a plurality of through holes. 12. The semiconductor device according to item 10 of the scope of patent application, wherein a part of the electrode of the above-mentioned first mounting part is electrically connected to the conductor layer. 13. · A semiconductor device, comprising: a back substrate having a back surface that is a front surface and a mounting surface on the opposite side thereof, a recessed portion on the surface, and a wiring substrate; A plurality of first mounting parts mounted on the recess in an overlapping manner; a plurality of second mounting parts mounted on the surface of the packaging substrate and on the first mounting part located above; A plurality of external electrode terminals on the back of the substrate; a conductor layer provided on the back of the above-mentioned packaging substrate and having a heat dissipation function to become the first-36- (4) (4) 200421567 reference power source; and On the surface side, a sealing portion made of an insulating resin covering the first and second mounting parts is located on the upper surface of the first mounting part above the recessed portion, and is substantially the same height as the surface of the packaging substrate, and is located below. The first mounting component is closely mounted on the packaging substrate, and the first mounting component located below is heat-generating. The component having a larger amount of heat than the first mounting component located above, the lower electrode of the first mounting component located below is electrically connected to the conductor layer through a conductor filled in a through hole, and the first 1 A part of the electrode of the mounting part is electrically connected to the conductor layer. 14. The semiconductor device according to item 13 of the scope of patent application, wherein the recessed portion is a multi-level recessed portion, the first mounting component located below is the bottom of the recessed portion fixed at the bottom, and the top of the first mounting component located below The electrode is electrically connected to the bottom surface of the step recessed portion extending from the stepped portion of the multi-layered recessed portion via a conductive lead, and the electrode of the first mounting part located above is electrically connected to the conductive ball via a conductive ball. Above the lead. 15. A semiconductor device comprising: a packaging substrate having a wiring on a back surface having a mounting surface on a front surface and a mounting surface opposite to the mounting surface; -37- (5) (5) 200421567 composed of an active device, and A plurality of first mounting parts mounted on the packaging substrate in a vertically overlapping manner; and a plurality of second mounting parts composed of passive elements and mounted on the surface of the packaging substrate; the first mounting part located below and the Between the first mounting parts above, an intermediate wiring board having electrodes on the upper and lower sides is sandwiched. The electrodes on the upper and lower sides of the intermediate wiring board are electrically connected via the wiring provided inside, and the intermediate wiring board is used for the above. The wirings of the above-mentioned first mounting parts and the package substrate are electrically connected together. 16. The semiconductor device according to item 15 of the scope of patent application, wherein the first mounting part located below is disposed in a recess provided on the surface of the packaging substrate, and is located above the first mounting part located below. It is substantially the same height as the surface of the above-mentioned packaging substrate. 17. The semiconductor device according to item 15 of the scope of patent application, wherein a conductive layer serving as a first reference power source having a heat dissipation function is provided on the back surface of the above-mentioned package substrate, and the first mounting part located below is provided. The lower electrode is electrically connected to the conductor layer. 18. A semiconductor device comprising: a packaging substrate having wiring on a back surface having a mounting surface on a surface and a mounting surface on the opposite side thereof; a plurality of semiconductor devices mounted on the recessed portion in an up-and-down manner; A plurality of first mounting parts made of passive components and mounted on the surface of the above-mentioned package substrate -38-(6) (6) 200421567 second mounting parts, the first mounting parts located below are provided below The electrodes are mounted on the packaging substrate, the first mounting component positioned above, and the electrodes provided below are connected to the packaging substrate via the bonding material, and the electrodes of the first mounting component positioned below, respectively. 19. The semiconductor device according to item 18 of the scope of patent application, wherein the first mounting part located below is disposed in a recess provided on the surface of the packaging substrate, and is located above the first mounting part below, It is approximately the same height as the surface of the packaging substrate, and a conductive layer serving as a first reference power source with a heat dissipation function is provided on the back of the packaging substrate, and an electrode is provided below the first mounting component located below. A semiconductor device electrically connected to the above-mentioned conductor layer 20. A semiconductor device, comprising: a packaging substrate having a wiring on a back surface having a mounting surface on the opposite side to the mounting surface; A plurality of first mounting parts mounted in a recess on the surface of the packaging substrate; a plurality of second mounting parts mounted on the surface of the packaging substrate formed of a passive element; A plurality of external electrode terminals; and provided on the surface side of the packaging substrate, covering the first and second -39 · (7) (7) 200421567 The sealing part made of insulating resin for mounting parts. The recessed part is a multi-level recessed part. The first mounting part located below is fixed to the bottom of the recessed part through the lower electrode, and the above is located below. The electrode on the upper surface of the first mounting part is electrically connected to the bottom surface of the middle recessed portion extending from the step portion of the multi-level recessed portion through the conductive lead. The electrode on the first mounting part located below is provided through the protrusion. The electrode is electrically connected to the lead and the wiring provided at the bottom of the middle recess. The first mounting component located below is a component having a larger amount of heat than the first mounting component located above. 21. The semiconductor device according to item 20 of the scope of application for a patent, wherein a conductive layer serving as a first reference power source having a heat dissipation function is provided on a back surface of the packaging substrate, and a bottommost recess of the packaging substrate is provided at the bottom There are a plurality of through holes, and a conductor is filled in the through hole 同时. The lower electrode of the first mounting part located below is electrically connected to the conductor layer through the conductor. 22. A semiconductor device comprising: a packaging substrate having wiring on a back surface having a mounting surface on a surface and a mounting surface on the opposite side thereof; and a semiconductor device which is composed of an active device and is mounted on the packaging for being stacked on top of each other. A plurality of first mounting parts in a recess on the substrate surface; a plurality of second mounting parts made of passive components and mounted on the surface of the above-mentioned packaging substrate; • 40- 200421567 ⑻ a plurality of exteriors provided on the back of the above-mentioned packaging substrate An electrode terminal; and a sealing portion made of an insulating resin provided on the surface side of the packaging substrate and covering the first and second mounting parts. The recessed part is a multi-level recessed part, and the first mounting part located below is provided through The lower electrode is fixed to the bottom of the lowest recessed portion, and the electrode on the upper surface of the first mounting part is electrically connected to the bottom of the first middle recessed portion extending through the stepped portion of the multi-level recessed portion through conductive leads. The wiring is located on the lower periphery of the first mounting part above, and is connected to The bottom of the first middle-level recess is the bottom of the second middle-level recess. The electrode on the top of the first mounting part is connected to the wiring provided on the bottom of the second middle-level recess through a conductive lead, and the first mounting is located below. The component is a component that generates a larger amount of heat than the first mounting component located above. 23. The semiconductor device according to item 22 of the scope of application for a patent, wherein a conductive layer serving as a first reference power source having a heat dissipation function is provided on a back surface of the packaging substrate, and a lowermost recess of the packaging substrate is provided at the bottom There are a plurality of through holes, and a conductor is filled in the through hole 同时. The lower electrode of the first mounting part located below is electrically connected to the conductor layer through the conductor. -41-
TW092108566A 2003-02-17 2003-04-14 Semiconductor device TW200421567A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396266B (en) * 2008-07-16 2013-05-11 Sharp Kk Semiconductor device and display device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291246A (en) * 1993-03-31 1994-10-18 Toppan Printing Co Ltd Multi-chip semiconductor device
JPH06334113A (en) * 1993-05-21 1994-12-02 Sony Corp Multichip module
JP3426842B2 (en) * 1996-04-16 2003-07-14 京セラ株式会社 High frequency power amplifier
JP3744649B2 (en) * 1997-05-26 2006-02-15 ソニー株式会社 Semiconductor package and manufacturing method thereof
JP3499202B2 (en) * 2000-10-16 2004-02-23 沖電気工業株式会社 Method for manufacturing semiconductor device
JP2002343930A (en) * 2001-05-16 2002-11-29 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396266B (en) * 2008-07-16 2013-05-11 Sharp Kk Semiconductor device and display device

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