TW200402859A - Elastic bump structure and its manufacturing method - Google Patents
Elastic bump structure and its manufacturing method Download PDFInfo
- Publication number
- TW200402859A TW200402859A TW92121169A TW92121169A TW200402859A TW 200402859 A TW200402859 A TW 200402859A TW 92121169 A TW92121169 A TW 92121169A TW 92121169 A TW92121169 A TW 92121169A TW 200402859 A TW200402859 A TW 200402859A
- Authority
- TW
- Taiwan
- Prior art keywords
- bump
- polymer
- metal layer
- patent application
- scope
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
200402859 五、發明說明(1) 【發明所屬之技術領域】 本發明是關於一種彈性凸塊結構及其製造方法,特別 是關於一種應用於覆晶構裝之彈性凸塊結構及其製造方 法。 【先前技術】 隨著電子產品同步朝向輕、薄、短、小、高速化與高 機能化之發展赵勢’而使得半導體元件構裝技術對於增加 元件可靠度、密度以及減少元件尺寸方面的要求不斷提 咼,因此傳統打線接合(w i r e b 〇 n d i n g )逐漸被覆晶構裝 (flip-chip)技術所取代。 覆晶構裝技術係以晶片與基板的接合面形成接合塾 (^ad)或是凸塊(bump)以取代習知構裝技術所使用的導線 架(lead frame)。透過直接壓合晶片與基板的接合面之間 =凸塊及接合墊來達成電路導通,可降低晶片與基板間的 =子訊號傳輪距離,適用於高速電子元件的封裝。習知的 ,晶構裝方法,係於晶片及基板的表面形成凸塊“韻幻等 合結構,然後在基板表面塗佈接著劑;再將晶片及基板 ^面的凸塊經過對位壓合以完成覆晶構裝結構。在晶片與 i2接著劑加以接合時,由於兩者具有嚴重的熱膨 ^ ^ I 4兴,當溫度產生變化時,熱應力的影響容易使晶 社μ 土反的凸塊接點產生變形。因此發展出彈性導電凸塊 祖國第5 5 0 82 28號專利所揭露之内容,係以高分 以形成彈枓t兀件之接點處形成凸塊,再覆以金屬包覆層 少 ¥電凸塊’藉此降低接點的熱膨脹係數差異,200402859 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an elastic bump structure and a manufacturing method thereof, and particularly to an elastic bump structure and a manufacturing method thereof applied to a flip-chip structure. [Previous technology] As electronic products move toward light, thin, short, small, high-speed, and high-performance development, Zhao Shi 'makes semiconductor component mounting technology requirements for increasing component reliability, density, and reducing component size. As the technology continues to increase, traditional wire bonding is gradually being replaced by flip-chip technology. The flip-chip mounting technology uses a bonding surface (^ ad) or a bump to form a bonding surface between the wafer and the substrate to replace the lead frame used in the conventional mounting technology. The circuit conduction is achieved by directly bonding the = bumps and bonding pads between the bonding surface of the wafer and the substrate, which can reduce the = sub-signal wheel distance between the wafer and the substrate, which is suitable for packaging high-speed electronic components. Conventionally, the crystal structure mounting method is to form bumps on the surface of the wafer and the substrate, and then apply a bonding agent to the surface of the substrate. Then, the bumps on the wafer and the substrate are aligned and pressed. In order to complete the flip-chip mounting structure, when the wafer and the i2 adhesive are bonded, because the two have severe thermal expansion, the thermal stress will easily make the crystal soil of the crystal society inverse when the temperature changes. The bump contact is deformed. Therefore, the content disclosed in the patent of the elastic conductive bump motherland No. 5 5 0 82 28 is developed. A high score is used to form a bump at the contact of the elastic element. The metal cladding layer is less ¥ electric bumps, thereby reducing the difference in thermal expansion coefficients of the contacts,
200402859 五、發明說明(2) 減少熱應力的影響 另外,為了減少接著劑、美拓 差異以及增加接點的強度,可^膠f間的熱膨脹係數 性填充粒子,填充粒子可補償膠=此入適當的非導心 脹係數差異所產生的體積變化量:=化時,因熱: 點強度。而在細間距接合 亚=加覆晶構裝 的導電粒子’而達成異方性(垂兄/C中添加細: 細間距的情況下,導電粒 直/向)的導電;但是在= 短路的情形,使其所能應用接點之倒面而產 【發明内容】 .用之線見和間距受限。度生 構及技術的問題,本發明提供-種彈、 應用於覆晶構裝製程。Ϊίϊ凸塊結 件表,之彈性凸塊結構提供垂直之電性 係错由電子元 構由高分子凸塊與金屬層所組成,藉由金居彈性凸塊結 絕接點之間因異方性導電接著劑之導電粒子=設計來阻 與細間距而產生的短路現象。 來木、細線寬 本發明揭露一種彈性凸塊結構及其 披覆於高分子凸塊之金屬層,以隔絕其 係設計 直接阻隔異方性導電接著劑之導電粒子,7电性導通, :粒子聚集而產生的短路現象。其彈性 士=點間因導 電子兀件表面的複數個導電接點,以提供恭二冓係形成於 )=他外部電子元件之電性連接。此彈性:::與基板 下表面及連接兩者之側面,其;表面、— 、毛子元件表面 $ 6頁 200402859 五、發明說明(3) 之導電接點, 接點以形成垂 全披覆金屬層 的形狀可為圓 應用此彈 寬與細間距的 結構之電子元 具有複數個接 亦具有複數個 形成於電子元 凸塊與金屬層 墊,下表面貼 由一個或一個 電性連 塊之側 且異方 以接著 此 造方法 再以光 馬分子 面,下 子凸塊 面延伸 接,以 面未完 性導電 基板與 外,本 ,係於 微影技 凸塊, 表面貼 ,金屬 至導通 金屬層 直電性 ,以隔 形、六 性凸塊 目的。 件和異 合墊以 導電接 件表面 所組成 合於導 以上之 提供電 全披覆 接著劑 電子元 發明更 上述之 術於電 其具有 合於導 層覆蓋 導電接 披覆於 連接, 絕其側 面體形 結構所 其覆晶 方性導 作為基 點 ° 如 的導電 ,其上 電接點 侧面延 子元件 金屬層 則塗佈 件。 包含彈 電子元 子元件 一上表 電接點 於上表 點形成 上表面 其中, 向的電 或其他 形成之 構裝係 電接著 板的導 上所述 接點, 表面接 ,金屬 伸至導 與基板 ,以隔 於基板 性凸塊 件表面 表面的 面、一 ;最後 面再緩 垂直電 ,經由側面延伸 高分子凸塊之側 氣導通,其高分 立體形狀。 覆晶構裝,可達 由基板、包含彈 劑所形成,基板 電線路;電子元 之複數個彈性凸 彈性凸塊結構由 合於基板表面的 層係披覆於上表 通邊導電接點形 之電性連接,高 絕其側向的電氣 與電子元件之接 結構及其覆晶構 形成複數個導電 導電接點上形成 下表面及連接兩 ,彼覆一金屬層 由一個或一個以 性連接,高分子 至導電 面未完 子凸塊 成細線 性凸塊 之表面 件表面 塊結構 高分子 接合 面再經 成垂直 分子凸 導通, 合區域 裝的製 接點; 複數個 者之側 於高分 上之側 凸塊之 〇200402859 V. Description of the invention (2) Reducing the effects of thermal stress In addition, in order to reduce the difference between the adhesive and the Metopo and increase the strength of the contact, the thermal expansion coefficient of the particles can be filled with particles, and the filled particles can compensate the glue. Volume change due to an appropriate non-conducting dilatation coefficient difference: = Heat during heating: Point strength. And in the fine-pitch bonding sub = conductive crystal particles superimposed on the crystal structure 'to achieve anisotropy (addition of fine in / C: fine-pitch, in the case of fine-pitch, conductive particles straight / direction); Under the circumstances, it can produce the reverse side of the contact which can be applied. [Summary of the Invention]. The use of lines and spacing is limited. To solve the problems of structure and technology, the present invention provides a kind of bullet, which is applied to the flip-chip structure manufacturing process. ΪίϊBump junction table, the elastic bump structure provides vertical electrical faults. The electronic element structure is composed of polymer bumps and metal layers. The gold bumps of the elastic bump junctions are caused by different directions The conductive particles of the conductive conductive adhesive = designed to prevent short circuit caused by fine pitch. Laimu, thin line width The present invention discloses an elastic bump structure and a metal layer covered with a polymer bump to isolate conductive particles that are designed to directly block anisotropic conductive adhesives, 7 electrically conductive, particles: The short circuit phenomenon caused by aggregation. Its elasticity is equal to the number of conductive contacts on the surface of the conductive electronic element to provide the electrical connection between the external electronic components. This elasticity ::: the bottom surface of the substrate and the side that connects the two, its; the surface,-, the surface of the hair element $ 6,200,402,859 5. The conductive contact of the invention description (3), the contact forms a fully covered metal The shape of the layer can be a circle. The electronic element with this elastic width and fine pitch structure has a plurality of connections and also a plurality of bumps formed on the electronic element bumps and the metal layer pad. The lower surface is affixed to the side of one or one electrically connected block. And the other side is followed by this manufacturing method and then the light horse molecular surface and the sub-bump surface are extended to connect the unfinished conductive substrate and the outer surface. This is based on the lithography technology bump, the surface is pasted, and the metal to the conductive metal layer is straight Electricity, for the purpose of spacer and hexasex bumps. The element and the hybrid pad are composed of the surface of the conductive contact and are provided with a conductive full coating adhesive. The electronic element invented the above-mentioned technique in the electric device and has a conductive layer covering the conductive conductive coating on the connection, and the side thereof. The crystal structure of the body structure is used as the base point, and the metal layer of the side contact element on the side of the electrical contact is coated. Containing the elastic electron element sub-element, an upper surface electrical contact is formed on the upper surface point, wherein a directed electrical or other formed structure is an electrical contact with the guide on the board, the surface is connected, and the metal is extended to the conductive contact. The substrate is separated from the surface of the surface of the substrate-shaped bump piece by a surface, and the rear surface is slowly vertical, and the side of the polymer bump extending through the side is gas-conducted, and its high-dimensional three-dimensional shape. Flip-chip structure, which can be formed by the substrate, including the ammunition, and the electrical circuit of the substrate; the plurality of elastic convex elastic bump structures of the electronic element are covered with a layer on the surface of the substrate and covered with conductive contacts on the upper side of the upper surface. The electrical connection is highly insulated from the lateral electrical and electronic component connection structure and its flip-chip structure. A plurality of conductive conductive contacts are formed on the lower surface and the two are connected. One metal layer is covered by one or one. , The polymer to the conductive surface of the incomplete sub bumps into fine linear bumps on the surface piece surface block structure polymer bonding surface is then turned into a vertical molecular convex conduction, combined with the area of the system to make contacts; a plurality of the side on the high score Of the side bumps 〇
第7頁 200402859 五 發明說明(4) 侧面係未完全披覆金屬層,以隔絕其側向的带$、曾、 利用接著劑將完成彈性凸塊結構的電子元^ 通。再 即形成覆晶構裝結構。 一 土反結合, 為使對本發明的目的、構造特徵及其 了解,茲配合圖示詳細說明如下·· ^的 【實施方式】Page 7 200402859 V. Description of the invention (4) The side system is not completely covered with a metal layer to isolate the lateral bands of $, 曾, and 接着. The adhesive will complete the electronic elements of the elastic bump structure. Then a flip-chip structure is formed. First, soil anti-combination, in order to understand the purpose, structural characteristics and the invention of the present invention, the detailed description with the illustration is as follows:
本發明所揭露之彈性凸塊結構及其製造方法,係# 彈性凸塊與其所披覆的金屬層設計,來阻絕接點之間错由 向電性連接,以解決細線寬與細間距之覆晶構裝所容的側 生的短路問題。彈性凸塊結構係由高分子凸塊與金屬易產 組成,配合不同的製程與設計,高分子凸塊的形狀可層所 形、六面體形或其他立體形狀,其高分子凸塊之側面為圓 全披覆金屬層,以隔絕其側向的電氣導通。 未完The elastic bump structure disclosed in the present invention and the manufacturing method thereof are designed by the #elastic bump and the metal layer covered by it to prevent the electrical connection between the contacts from being misdirected, so as to solve the problem of fine line width and fine pitch. The short circuit problem that the crystal structure can accommodate. The elastic bump structure is composed of polymer bumps and metal that are easy to produce. With different processes and designs, the shape of the polymer bumps can be layered, hexahedral, or other three-dimensional shapes. The sides of the polymer bumps are The metal layer is completely rounded to isolate its lateral electrical conduction. Unfinished
本發明之較佳實施例,係於電子元件表面的複數 電接點形成複數個彈性凸塊結構。並以六面體形狀1^導 子凸塊為例,說明高分子凸塊的金屬層披覆情形。之鬲分 請參考第1 A圖,其為本發明第/實施例之剖 思圖,其包含:一晶片丨〇 〇,其表面具有複數個導電接點^ 111,並於導電接點n i之周圍披覆保護膜120 ;導電接點 111則貼合彈性凸塊結構,並藉著彈性凸塊結構產生垂直 的電性連接。彈性凸塊結構係包含下金屬層丨丨2、高分子 凸塊11 0、金屬層,為防止接點氧化以及增加金屬層與高 分子絕緣塊1 1 0之附著力,其金屬層由黏著金屬層丨丨3盘金 屬層114所組成。導電接點Ul表面係依序貼附下金屬層In a preferred embodiment of the present invention, the plurality of electrical contacts on the surface of the electronic component form a plurality of elastic bump structures. Taking the hexahedron-shaped 1 ^ guide bump as an example, the metal layer coating of the polymer bump will be described. Please refer to FIG. 1A for a detailed description, which is a cross-sectional view of the first / embodiment of the present invention, which includes: a wafer, the surface of which has a plurality of conductive contacts ^ 111, and The surroundings are covered with a protective film 120; the conductive contacts 111 are attached to the elastic bump structure, and a vertical electrical connection is generated by the elastic bump structure. The elastic bump structure includes a lower metal layer, a polymer bump, a metal layer, and a metal layer. In order to prevent contact oxidation and increase the adhesion between the metal layer and the polymer insulation block, the metal layer consists of an adhesive metal. Layer 丨 丨 3 disk metal layer 114. The surface of the conductive contact Ul is sequentially attached with a lower metal layer
200402859 五、發明說明(5) 112、咼分子凸塊11〇、黏著金屬層113與金屬層114,高分 子凸塊110係成六面體形狀,其具有一上表面、一下表面 及四個侧面。高分子凸塊之下表面貼合於下金屬層112, 金屬層披覆於上表面再經由兩個相對之侧面延伸至導通導 電接點11 1以形成垂直電性連接,另外相對之兩個側面未 披覆金屬層,以隔絕其側向的電氣導通。其中,複數個彈 f生凸塊排列時,其彼覆之金屬層不相鄰於其鄰接之 塊。200402859 V. Description of the invention (5) 112, fluorene molecular bumps 110, adhesive metal layer 113 and metal layer 114, polymer bumps 110 are in the shape of a hexahedron, which has an upper surface, a lower surface and four sides. . The lower surface of the polymer bump is attached to the lower metal layer 112, the metal layer covers the upper surface and then extends to the conductive contact 11 1 through two opposite sides to form a vertical electrical connection, and the other two opposite sides The metal layer is not covered to isolate its lateral electrical continuity. Among them, when a plurality of elastic bumps are arranged, the metal layers overlying them are not adjacent to the adjacent blocks.
請參考第1B圖,其為本發明第一實施例之彈性凸塊释 ,的斜視示意圖。本發明之特徵點係在於金屬層的設計, ^彈性凸塊結構係包含下金屬層112、高分子凸塊11〇、系 =金屬層U3與金屬層114,如第1B圖所示,黏著金屬層 1金屬層114所組成的金屬層以跨接方式覆蓋於高分^ ^塊110之兩個側®,另外兩個相對侧面則未披覆金屬 層,以隔絕其側向的電氣導通。 構的:t考:1C圖’其為本發明第二實施例之彈性凸塊與 ϊ =視赤意圖。*了有效防止封裝時所使用之異方性堯 含/的導電粒子造成的短路,除了黏著金屬層Please refer to FIG. 1B, which is a schematic perspective view of an elastic bump according to the first embodiment of the present invention. The characteristic point of the present invention lies in the design of the metal layer. The elastic bump structure includes a lower metal layer 112, a polymer bump 110, a metal layer U3, and a metal layer 114. As shown in FIG. 1B, the metal is adhered. The metal layer composed of the layer 1 metal layer 114 covers the two sides of the high-scoring block 110 in a bridged manner, and the other two opposite sides are not covered with the metal layer to isolate the lateral electrical conduction. Structure: t test: Figure 1C 'This is the elastic bump and ϊ = apparent intent of the second embodiment of the present invention. * Effectively prevents short circuit caused by anisotropic particles used in packaging, except for the adhesion of metal layers
Γ堍;Γπ=14所組成的金屬層以跨接方式覆蓋於高分巧 之兩個側面之外,金屬層所披覆之區域亦可較高 =縮1微米至5微米,其内縮尺寸可配合· 兒粒子的直彳至來決定。 此外,配合 同設計,如第一 3,的凸塊排列金屬層披覆之側面可做不 貝施例的金屬層披覆之兩個侧面亦可為相Γ 堍; Γπ = 14 The metal layer composed of 14 covers the two sides of Gao Fangqiao in a bridging manner. The area covered by the metal layer can also be higher = 1 micron to 5 micron, its shrinkage It can be decided according to the arrival of the particles. In addition, with the same design, such as the first 3, the sides of the metal layer coating of the bump arrangement can be used as the two sides of the metal layer coating.
^ 9頁 200402859 五、發明說明(6) 鄰的兩侧面,或是金屬層由高分子凸塊之上表面坡覆至高 分子凸塊之任意三個侧面,並延伸至導通導電接點。^ Page 9 200402859 V. Description of the invention (6) The two adjacent sides, or the metal layer is covered from the upper surface of the polymer bump to any three sides of the polymer bump, and extends to the conductive contact.
請參考第2 A圖,其為本發明第三實施例之剖面結構示 意圖,其包含··一晶片1 〇 〇,其表面具有複數個導電接點 111 ’並於導電接點111之周圍坡覆保護膜120。導電接點 111表面係依序貼附下金屬層11 2、高分子凸塊丨丨〇、章 金屬層11 3與金屬層11 4,高分子凸塊11 0係成二 $者 狀,其具有〜上表面、一下表面及四個側面。言^形 之下表面貼合於下金屬層112,金屬層披覆於上〇刀子凸塊 由三個侧面延伸至導通導電接點11 1以形成垂 ^面再經 接,其中之一側面未坡覆金屬層,以隔絕复 兔性連 通。 則向的電氣導 請參考第2B圖,其為本發明第三實施例之 構的斜視示意圖。其彈性凸塊結構係包含下6麗性凸塊結 高分子凸塊11 0以及黏著金屬層11 3與金屬層^ 4層11 2、 圖所示黏者金屬層113與金屬層114所纟且成的八。如弟1B 於高分子凸塊丨丨〇之三個側面,另外之一侧、金屬層覆蓋 層,以隔絕其側向的電氣導通。 坡覆金屬Please refer to FIG. 2A, which is a schematic cross-sectional structure diagram of a third embodiment of the present invention, which includes a wafer 100, the surface of which has a plurality of conductive contacts 111 ', and is sloped around the conductive contacts 111. Protective film 120. The surface of the conductive contact 111 is sequentially attached with the lower metal layer 11 2. The polymer bump 丨 丨 〇, the metal layer 11 3 and the metal layer 11 4. The polymer bump 110 is in the shape of two, which has ~ Upper surface, lower surface and four sides. The lower surface is attached to the lower metal layer 112, and the metal layer is coated on the upper blade. The knife bump extends from three sides to the conductive contact 11 1 to form a vertical surface and then is connected. One of the sides is not connected. The slope is covered with a metal layer to isolate the rabbits. Please refer to FIG. 2B for a schematic view of the electrical conduction of the third embodiment of the present invention. The elastic bump structure includes the following 6 bumps, high-molecular bumps, polymer bumps 110, and an adhesive metal layer 11 3 and a metal layer ^ 4 layer 11 2. The adhesive metal layer 113 and the metal layer 114 shown in FIG. Into eight. For example, Brother 1B is on the three sides of the polymer bump, and the other side is covered with a metal layer to isolate its lateral electrical conduction. Sloping metal
請參考第2C圖,其為本發明第四實施例 構的斜視示意圖。其中金屬層所彼覆之區域,性凸塊結 之邊緣内縮1微米至5微米。 乂阿分子凸塊 本發明可根據電子元件表面不同的凸 來決疋金屬層披附的情形。 歹】與設計, 請參考第3圖,其為雙排凸塊之晶片上視 200402859 五、發明說明(7) 係於晶片表面以交錯式排列形成雙排,針對此雙排凸塊可 作各種設計以隔絕其鄰接面的側向電氣導通。 請參考第3 A圖,其為本發明第五實施例之雙排彈性凸 塊結構斜視示意圖,其彈性凸塊結構係包含下金屬層 112、高分子凸塊110以及黏著金屬層113與金屬層114,如 第3A圖所示,黏著金屬層113與金屬層114所組成的金屬層 覆蓋於高分子凸塊11 0之一側面,金屬層所覆蓋之侧面未 鄰接其他凸塊,而鄰接其他凸塊之三側面則未彼覆金屬 層,以隔絕其側向的電氣導通。 請參考第3B圖,其為本發明第六實施例之雙排彈性凸 塊結構斜視示意圖。其黏著金屬層11 3與金屬層11 4所組成 的金屬層覆蓋於高分子凸塊11 0之兩侧面,且凸塊係以未 彼覆金屬層之側面鄰接於另一凸塊,金屬層所披覆之區域 較高分子凸塊11 0之邊緣内縮1微米至5微米。 請參考第3C圖,其為本發明第七實施例之雙排彈性凸塊結 構斜視示意圖。其黏著金屬層11 3與金屬層11 4所組成的金 屬層覆蓋於高分子凸塊11 0之一側面,金屬層所坡覆之區 域較高分子凸塊11 0之邊緣内縮1微米至5微米。 請參考第4圖,其為本發明實施例之製作流程圖,首 先,於晶片表面形成複數個導電接點(步驟3 1 0 );其次, 於晶片表面形成保護膜並露出導電接點區域(步驟3 2 0 ); 於導電接點表面形成下金屬層(步驟3 3 0 );以光微影技術 於晶片表面的導電接點上形成六面體形狀之複數個高分子 凸塊(步驟340),高分子凸塊具有一上表面、一下表面及Please refer to FIG. 2C, which is a schematic perspective view of a fourth embodiment of the present invention. In the area covered by the metal layer, the edge of the sexual bump junction shrinks by 1 micrometer to 5 micrometers.乂 A molecular bump The present invention can determine the situation of the metal layer being covered according to different protrusions on the surface of the electronic component.歹] and design, please refer to Figure 3, which is a wafer with double rows of bumps. 200402859 V. Description of the invention (7) The double rows of bumps can be formed in a staggered arrangement on the surface of the wafer. Designed to isolate the lateral electrical continuity of its abutting faces. Please refer to FIG. 3A, which is a schematic oblique view of a dual-row elastic bump structure according to a fifth embodiment of the present invention. The elastic bump structure includes a lower metal layer 112, a polymer bump 110, an adhesive metal layer 113, and a metal layer. 114, as shown in FIG. 3A, the metal layer composed of the adhesive metal layer 113 and the metal layer 114 covers one side of the polymer bump 110, and the side covered by the metal layer does not adjoin other bumps, but adjoins other bumps. The three sides of the block are not covered with a metal layer to isolate their lateral electrical conduction. Please refer to FIG. 3B, which is a schematic perspective view of a double-row elastic bump structure according to a sixth embodiment of the present invention. The metal layer composed of the adhesive metal layer 11 3 and the metal layer 11 4 covers both sides of the polymer bump 110, and the bump is adjacent to another bump with the side not covered with the metal layer. The edges of the higher molecular bumps 110 covered in the covered area shrink within 1 micrometer to 5 micrometers. Please refer to FIG. 3C, which is a schematic perspective view of a double-row elastic bump structure according to a seventh embodiment of the present invention. The metal layer composed of the adhesive metal layer 11 3 and the metal layer 11 4 covers one side of the polymer bump 110, and the area covered by the metal layer is higher than the edge of the molecular bump 110 by 1 micrometer to 5 Microns. Please refer to FIG. 4, which is a manufacturing flow chart of an embodiment of the present invention. First, a plurality of conductive contacts are formed on the surface of the wafer (step 3 10); second, a protective film is formed on the surface of the wafer and the conductive contact area is exposed ( Step 3 2 0); forming a lower metal layer on the surface of the conductive contact (step 3 3 0); using photolithography to form a plurality of polymer bumps in the shape of a hexahedron on the conductive contact on the surface of the wafer (step 340 ), The polymer bump has an upper surface, a lower surface and
第11頁 200402859 五、發明說明(8) 四個側面,1 覆-黏著金屬心f貼合於導電接點上方之下金屬層;披 於高分子凸塊心刀子凸塊ί步驟35〇) ’·披覆一金屬層 金屬層輿金屬層乂 ,接:?合光微影技術蝕刻黏著 成垂直電性再經由側面延伸至導通導電接點形 個側面坡覆八;^據不同的設計,高分子凸塊之一至二 侧向的電氣導通。 趿覆孟屬層,以隔絕其 另外,配合本發明的製造方法, 面製作高分子保護層、接地金 J兀件表 機構。 蚁嘈共接點良率之測試 請參考第5Α圖,其為本發明第八實施之立 圖,晶片1 〇 〇,其表面具有複數個導電接點丨1 i =兩 接點111之周圍彼覆保護膜! 2 0。導電接 ,亚;、4包 塊結構,係、包含下金屬層112、高分 與金屬層m,其中黏著金屬層113與金屬層二延: 至保護膜120,可直接作為接點良率之測試機構,避免進 仃接點良率測試時,測試探針和凸塊的對位鱼滑題, =可減少探針對於凸塊的料。㈣金屬層⑴與金屬層 =4所延伸而成的接點良率之測試機構可於彈性凸塊綠構 =中一併完成,並且於製作高分子凸塊11〇之步驟時, :::晶:10。表面製作南分子保護層14〇,以保護其他線 路與表面電子元件。 請參考第5B圖,其為本發明第九實施例之剖面示意Page 11 200402859 V. Description of the invention (8) Four sides, 1 covering-adhesive metal core f attached to the metal layer above and below the conductive contact; covered with polymer bumps, core knife bumps, step 35)) · Cover a metal layer with a metal layer and a metal layer, then: Synoptic lithography technology etches and adheres to vertical electrical conductivity and then extends to the side of the conductive contacts through the sides. Each side slope covers eight; ^ According to different designs, one to two of the polymer bumps are electrically connected laterally. Covering the mongolian layer to isolate it In addition, in accordance with the manufacturing method of the present invention, a polymer protective layer and a grounded metal component mechanism are fabricated. For the test of the yield of ant noise common contact, please refer to FIG. 5A, which is an elevation view of the eighth implementation of the present invention. The wafer 100 has a plurality of conductive contacts on its surface. Cover with protective film! 2 0. Conductive connection, sub-, 4-pack structure, including lower metal layer 112, high score and metal layer m, of which the adhesive metal layer 113 and the metal layer are extended: to the protective film 120, which can be directly used as the contact yield The testing organization avoids the problem of the alignment of the test probe and the bump during the yield test of the contact, which can reduce the material of the probe for the bump. ㈣Metal layer⑴ and the metal layer = 4 extend the contact yield test mechanism to complete the elastic bump green structure = zhong together, and in the step of making the polymer bump 110, ::: Crystal: 10. A south molecular protective layer 14 is formed on the surface to protect other circuits and surface electronic components. Please refer to FIG. 5B, which is a schematic cross-sectional view of a ninth embodiment of the present invention.
200402859 五、發明說明(9) 圖’亦I於電子元件表面加上接地金屬遮蔽層,以防止電 磁干擾等效應。如第5A圖所示,高分子保護層14〇係覆蓋 ^屬遮=層130,先在導電接點ui表面製作上金屬層112 守门日才‘作金屬遮蔽層130,並與基板上接地之導電接 ά墊連接’再於製作高分子凸塊η 〇之步驟時,於晶片1 〇 〇 表面製作鬲分子保護層140。其中同時且利用同一道光罩 所製作之具有高度差異的高分子凸塊丨丨〇與高分子保護層 140,可藉由具有不同穿透率區域之光罩對正型感光高分 子層曝光,再進行一次顯影來完成。 、應用本發明的彈性凸塊結構所形成之覆晶構裝,可達 成細線寬與細間距的目的。 租茶考第6圖,其為本發明第一應用例之結構示意 圖。其覆晶構裝係由基板2 〇 〇、包含彈性凸塊結構之晶"片 1〇〇和異方性導電接著劑22 0所形成,異方性導\接著 22 0含有導電粒子221,基板2〇〇之表面具有複數個接/墊 2曾1 0以作為基板2 〇 0的導電線路;晶片丨〇 〇表面具有複數個 =接點111。如上所述之複數個彈性凸塊結構形成於晶 片100表面的導電接點ln並壓合於複數個接合 電性導通。高分子凸塊110之上表面接合於基板2 0 0表7面的 接合墊210,下表面貼合於導電接點⑴,黏著金屬層、 U屬層U4所組成之金屬層係彼覆於上表面再經二個 或一個以上之侧面延伸至導通導電接點形成垂直電性 接’以提供晶片1 0 0與基板2 〇 〇之電性連接。里 2、酋、 著劑22 0則塗佈於基板2〇〇與晶片1〇〇之接合區域以進¥行電接接200402859 V. Description of the invention (9) Figure ‘I’ also adds a ground metal shielding layer on the surface of the electronic component to prevent electromagnetic interference and other effects. As shown in FIG. 5A, the polymer protective layer 14 is a covering layer 130. First, a metal layer 112 is made on the surface of the conductive contact ui, and the gate is only used as the metal shielding layer 130, and is grounded to the substrate. When the conductive pad is connected, the molecular protective layer 140 is formed on the surface of the wafer 1000 when the polymer bump η is formed. Among them, the polymer bumps with high differences made at the same time and using the same photomask and the polymer protective layer 140 can be exposed to the positive photosensitive polymer layer through photomasks with different transmittance regions, and then Perform one development to complete. 2. The flip-chip structure formed by applying the elastic bump structure of the present invention can achieve the purposes of fine line width and fine pitch. Fig. 6 of the tea rental test is a schematic structural view of a first application example of the present invention. The flip-chip structure is formed by a substrate 2000, a crystal including an elastic bump structure "sheet 100", and an anisotropic conductive adhesive 22 0, and the anisotropic conductive film 22 contains conductive particles 221, The surface of the substrate 2000 has a plurality of contacts / pads 2 which have been used as the conductive circuit of the substrate 2000; the surface of the wafer 100 has a plurality of = contacts 111. As described above, the plurality of elastic bump structures are formed on the conductive contacts ln on the surface of the wafer 100 and are pressed to the plurality of joints for electrical conduction. The upper surface of the polymer bump 110 is bonded to the bonding pad 210 on the 7th surface of the substrate 200, and the lower surface is bonded to the conductive contact ⑴. A metal layer composed of an adhesive metal layer and a U-based layer U4 is overlaid on top of each other. The surface is extended to the conducting contact through two or more sides to form a vertical electrical connection, so as to provide the electrical connection between the wafer 100 and the substrate 2000. Lane 2, chief, and coating agent 220 are coated on the bonding area between the substrate 200 and the wafer 100 for electrical connection.
第13頁 200402859 五、發明說明(10) _ 2高分子凸塊110之側面未完全 結構係以未彼覆金屬層之側 Y屬層译丨生凸塊 向之電性連接。 设孓另一凸塊,以隔絕側 覆晶構裝的製造方法,請參考 -一庵田丨々制yd、古 弟7圖’其為本發明第 複數個接合墊以作為基板 ^基板,/、表面形成 提供一 s Η ,豆矣 電線路(步驟410);其次, 塊(步驟420),彈性凸塊由點形成禝數個彈性凸 其具有-上表面、-下ΛυΛ塊與金屬層所形成, ;覆於上表面再經由側:延伸至導;Ϊ = 係 性連接,該高分子凸塊之側面係未完=垂直電 絕其側向的電氣導通。鈇後, 覆五屬層,以 =劑⑽43。);再使導電凸布:方::毛 接合塾(步驟440 ),令彈性凸塊:人之 的接合墊,下表面貼人導帝 接口於基板表面 板之電性連接。最德^ ^ 以提供電子元件與基 與基板(步賴),即形成覆晶構接者劑鳴元件 本發明所使用之接著劑可選煜 導電性接著劑,電子方性導電接著劑或非 可選自有機美板、陶咨# 之日日顯不器驅動晶片,基板 基板咬表化:ΐ璃基板、石夕基板、神化鎵 土表面有乳化層之金屬基板。 冬 明:=::;=上:不述脫::其並非用 精神和範圍内,當可作些許之更^:不Page 13 200402859 V. Description of the invention (10) _ 2 The side of the polymer bump 110 is not completely structured. The side is not covered with a metal layer. Let ’s set another bump to isolate the side-on-chip structure manufacturing method, please refer to the figure of YID, YID, Gudi 7 ′, which is the number of bonding pads of the present invention as the substrate ^ substrate, The surface formation provides a sΗ, 矣 矣 electric circuit (step 410); secondly, the block (step 420), the elastic bump is formed by points, and the elastic bump has-an upper surface,-a lower ΛυΛ block and a metal layer. Form,; cover the upper surface and then pass through the side: extend to conduction; Ϊ = system connection, the side of the polymer bump is incomplete = vertical electrical insulation of its lateral electrical conduction. After that, it was covered with five genus layers with = 43. ); Then, the conductive convex cloth: square :: wool is bonded (step 440), so that the elastic bump: a bonding pad of a person, and a lower surface is pasted by a human guide interface to the substrate surface and the board is electrically connected. The most excellent ^ ^ to provide electronic components and substrates and substrates (step Lai), that is to form a flip-chip structure of the adhesive element, the adhesive used in the present invention can be selected from conductive adhesive, electronic conductive adhesive or non It can be selected from the organic beauty board, Tao Shi # day display device driver chip, substrate substrate bit surface: glass substrate, Shi Xi substrate, metal substrate with an emulsified layer on the surface of the deified gallium soil. Dong Ming: = ::; = 上: Do not talk about :: It is not used within the spirit and scope, it can be made a little bit more ^: No
第14頁 ^ ·; 200402859Page 14 ^ ·; 200402859
第15頁 200402859 圖式簡單說明 第1圖為單排凸塊之晶片之上視圖; 第1 A圖為本發明第一實施例之剖面結構示意圖; 第1 B圖為本發明第一實施例之彈性凸塊結構的斜視示意 意 示 視 斜 的 構 結 塊 凸 性 TJcaL 之 例 施 實 二 第 明 發 本 為 圖 ;C f 丄 圖第 意 示 視 •,斜 圖的 意構 示結 構塊 結凸 面性 剖彈 之之 JJ, ΙΠΊ 施施 實實 三三 ^第 明明 發發 本本 為為 圖圖 ;A B 2 2 圖$^欣弟 意 示 視 斜 的 .構 結 塊 凸 性 crtuL 之 例 施 實 四 第 明 發 本 為 圖 ;C 2 圖第 意 示 視 斜 構 結 塊 凸 性 tTcuu IF 雙 之 例 施 實 五 第 明 發 本 為 圖 A 3 圖Λ-/Γ弟从弟 圖 視 上 片 晶 之 塊 凸 hr 雙 為 圖 意 示 視 斜 構 結 塊 凸 性 彈 Ltr 雙 之 例 施 實 六 第 明 發 本 為 圖 ;B 3 圖第 意 示 視 斜 構 結 塊 凸 性 σ&ρ hr 雙 之 例 施 實 七 第 明 發 本 為 圖 ;G 3 圖从乐 施 實 明 發 本 為 圖 ;4 圖第 圖 程 流 作 製 之 圖圖 意意 示示 構構 結結 面面 JnJ, JnJ. 之之 施施 實實 八九 明明 發發 本本 為為 圖圖 A B 5 5 圖 意 示 構 結 合 接 之 例 用 應 - 第 明 發 本 為 圖 及 圖 程 流 作 製 之 例 用 應 1 第 明 發 本 為 圖 說 號 符 式 第16頁 200402859 圖式簡單說明 100 晶片 110 高分子凸塊 111 導電接點 112 下金屬層 113 黏著金屬層 114 金屬層 120 保護膜 130 接地金屬遮蔽層 140 高分子保護層 200 基板 210 接合墊 220 異方性導電接著劑 221 導電粒子 步驟3 1 0 步驟3 2 0 域 步驟3 3 0 步驟3 4 0 成六面體 步驟3 5 0 步驟3 6 0 步驟3 7 0 步驟4 1 0 作為基板 於晶片表面形成複數個導電接點 於晶片表面形成保護膜並露出導電接點區 _ 於導電接點表面形成下金屬層 以光微影技術於晶片表面的導電接點上形 形狀之複數個高分子凸塊 披覆一黏著金屬層於高分子凸塊 彼覆一金屬層於高分子凸塊 配合光微影技術蝕刻黏著金屬層與金屬層 提供一基板,其表面形成複數個接合塾以 的導電線路Page 15 200402859 Brief description of the drawings. Figure 1 is a top view of a wafer with a single row of bumps. Figure 1 A is a schematic cross-sectional structure diagram of the first embodiment of the present invention. Figure 1 B is a diagram of the first embodiment of the present invention. The oblique view of the elastic bump structure is a schematic illustration of the oblique structure of the convex block TJcaL. The second embodiment is shown in the figure; C f JJ, ΙΠΊ of the sexual bombardment Shi Shishi San San ^ Di Mingfa issued the book as a picture; AB 2 2 Figure ^ Xindi intended to be seen obliquely. Examples of building a convex crtuL Example 4 Figure 2 shows the picture; C 2 shows the example of the oblique agglomeration convexity tTcuu IF double. Example 5 The picture shows the picture A 3 Figure Λ- / Γ from the picture of the younger brother The block convex hr double is an example of an oblique block convex convex Ltr double. The sixth embodiment is shown in the figure; B 3 is an example of the oblique block convex convexity σ & ρ hr double. Shi Shi Seventh Mingfa is a picture; G 3 is from Oxfam Shiming Figures; 4 Figures, Figures, Figures, and Flow Charts are intended to show the structure of the structure JnJ, JnJ. The example application should be-the first Mingfa version is a diagram and the flow chart of the example application should be used. The 1st Mingfa version is a pictorial symbol. Page 16 200402859 The diagram is a simple explanation. 100 chip 110 polymer bump 111 conductive contact 112 Lower metal layer 113 Adhesive metal layer 114 Metal layer 120 Protective film 130 Ground metal shielding layer 140 Polymer protective layer 200 Substrate 210 Bonding pad 220 Anisotropic conductive adhesive 221 Conductive particles Step 3 1 0 Step 3 2 0 Domain step 3 3 0 Step 3 4 0 Hexahedron Step 3 5 0 Step 3 6 0 Step 3 7 0 Step 4 1 0 Form a plurality of conductive contacts on the surface of the wafer as a substrate to form a protective film on the surface of the wafer and expose the conductive contact area_ 于The lower metal layer is formed on the surface of the conductive contact. A plurality of polymer bumps shaped on the conductive contacts on the wafer surface by photolithography are coated with an adhesive metal layer on the polymer bump. Coating a metal layer with a polymer bump photolithography etching adhesive metal layer and the metal layer providing a substrate having a surface to form a plurality of conductive traces engagement Sook
第17頁 200402859 圖式簡單說明 步驟42 0 提供一晶片,其表面的複數個導電接點形 成複數個彈性凸塊 步驟43 0 於基板表面塗佈異方性導電接著劑 步驟440 使導電凸塊對準壓合於基板表面之接合墊 步驟4 5 0 固化異方性導電接著劑以接合元件與基板Page 17 200402859 Brief description of the diagram Step 42 0 Provide a wafer with a plurality of conductive contacts on the surface to form a plurality of elastic bumps Step 43 0 Apply an anisotropic conductive adhesive on the surface of the substrate Step 440 Make the conductive bumps pair Step of quasi-pressing the bonding pad on the substrate surface 4 5 0 Curing the anisotropic conductive adhesive to bond the component to the substrate
第18頁Page 18
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92121169A TWI251918B (en) | 2003-08-01 | 2003-08-01 | Elastic bump structure and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW92121169A TWI251918B (en) | 2003-08-01 | 2003-08-01 | Elastic bump structure and its manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200402859A true TW200402859A (en) | 2004-02-16 |
TWI251918B TWI251918B (en) | 2006-03-21 |
Family
ID=37453813
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW92121169A TWI251918B (en) | 2003-08-01 | 2003-08-01 | Elastic bump structure and its manufacturing method |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI251918B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100477140C (en) * | 2006-05-19 | 2009-04-08 | 台湾薄膜电晶体液晶显示器产业协会 | Packing component of semiconductor and preparing method thereof |
US8164187B2 (en) | 2004-12-14 | 2012-04-24 | Taiwan Tft Lcd Association | Flip chip device and manufacturing method thereof |
-
2003
- 2003-08-01 TW TW92121169A patent/TWI251918B/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164187B2 (en) | 2004-12-14 | 2012-04-24 | Taiwan Tft Lcd Association | Flip chip device and manufacturing method thereof |
CN100477140C (en) * | 2006-05-19 | 2009-04-08 | 台湾薄膜电晶体液晶显示器产业协会 | Packing component of semiconductor and preparing method thereof |
Also Published As
Publication number | Publication date |
---|---|
TWI251918B (en) | 2006-03-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2596960B2 (en) | Connection structure | |
TW464927B (en) | Metal bump with an insulating sidewall and method of fabricating thereof | |
TWI317164B (en) | Contact structure having a compliant bump and a testing area and manufacturing method for the same | |
JPH1140522A (en) | Semiconductor wafer and manufacture thereof, semiconductor chip and manufacture thereof, and ic card with the semiconductor chip | |
TWI255466B (en) | Polymer-matrix conductive film and method for fabricating the same | |
TWI262347B (en) | Electrical conducting structure and liquid crystal display device comprising the same | |
JP3832102B2 (en) | Manufacturing method of semiconductor device | |
TW201225231A (en) | Bonding pad structure and integrated cicruit comprise a pluirality of bonding pad structures | |
JPS63160352A (en) | Method for packaging semiconductor device | |
TW201241978A (en) | Flip chip device | |
JP2002141459A (en) | Semiconductor device and its manufacturing method | |
TWI246175B (en) | Bonding structure of device packaging | |
TW200402859A (en) | Elastic bump structure and its manufacturing method | |
JPH04362925A (en) | Wiring board | |
TWI352408B (en) | Chip, chip manufacturing method, and chip packagin | |
JPH01140753A (en) | Three-dimensional semiconductor device | |
KR940027134A (en) | Manufacturing method of semiconductor integrated circuit device | |
TW200908246A (en) | Adhesion structure for a package apparatus | |
JP3596572B2 (en) | Board connection method | |
TWI287265B (en) | Flip chip device | |
TWI285947B (en) | Packaging structure by using micro-capsule adhesive material and its packaging method | |
JPH0440277Y2 (en) | ||
TWI269421B (en) | Chip package structure and deformable compliant bump structure thereof | |
TWI236068B (en) | Structure for increasing interconnect reliability and method fabricating thereof | |
TWI286381B (en) | Multi-chip integrated module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |