TW200304188A - Semiconductor component and manufacturing method - Google Patents

Abstract

The present invention is a vertical type deep trench semiconductor component and two manufacturing methods thereof. Both manufacturing methods are implanting ions slantly into the semiconductor substrate passing through the trench sidewall to form the mainbody region and source region. The field oxide and photolighography adhesive in the trench are used for ion-implanting mask during ion implantation. The pn junction among the mainbody region and drain region and/or drift region can be aligned or self-aligned by using this way.

Description

200304188 V. Description of the invention (1) The content of the present invention includes two methods for manufacturing a semiconductor device that can be controlled by field effect, and such a semiconductor device having the characteristics of the scope of the patent application No.6. For designing a new generation of vertical high-power semiconductor components, reduction ratio on-resistance is of great importance. By reducing the on-resistance, the static loss power can be reduced on the one hand, and high-power semiconductor components can be made to have a larger current density. Therefore, much smaller semiconductor components can be used for the same total current. The width of the brake in the direction of the shrinking component and the body component is higher than that of the conductor group. The ratio of the channels on the vertical product of the semiconducting semiconductor structure with the upper and lower halves in the trench with the inner half of the inner thickness of the body area to the high power half resistance is proportional to the upper half. In the lower half of the trench, one method of lowering the dielectric in the trench and the quality of the substrate in the trench is smaller than the on-resistance Ron. The semiconductor device is a trench-type planar cell structure. In the trench type, the trench is disposed in the semiconductor substrate, that is, in the electrode. Since such a semiconductor device is large per unit area, the specific resistance can be greatly reduced. In terms of components, the resistance caused by the drift region occupies the entire turn-on current. In order to reduce the influence of the drift region on the entire on-resistance, the semiconductor structure has a deep trench. Of these trenches and / or channel regions, the lower half penetrates deeper into the drift region (with a stepped dielectric, because the dielectric in the trench is greater than the thickness in the upper half of the trench, the gate electrode thickness will naturally be greater than in the trench The thickness of the upper half of the groove. The half forms the gate oxide for channel control. The hafnium oxide formed by the dielectric is used to make the gate electrode and the semiconductor

Page 5 V. Description of the invention (2) Edge 0 This semiconductor device with deep trenches and stepped gate electrodes and oxides in the trenches is a known technology #, for example, in German patent DE 1 9935442 C1 mentioned. This method of semiconductor components is at 〇〇〇1 / 〇1484. ^ This type of semiconductor component contains a parasitic input capacitor that must be recharged during each switching process. Because this recharging process requires current, switching losses will occur, especially when low-voltage semiconductor components are used and switching times are frequent. This parasitic capacitance = consists of a gate-source capacitor cGS and a gate-drain capacitor Cgd. Gate-source capacitors for metal-oxide-semiconductor structures in "Power Semiconductor Devices," (Power Modules), PWS Publishing Company, p. 38-383, and Figure 7 μ, by β • Erya Baliga The explanation of the gate is that the capacitor CGS is composed of an overlapped capacitor between the polycrystalline silicon: C: at the gate, and a capacitor formed by the two layers of the channel region and the gate electrode. It is also called It is a feedback capacitor or Miller: CGD capacitors are mainly composed of gate oxide capacitors, while idle oxide capacitors with deep passive body components are composed of a wide area in the upper half of the electrode = two t. At present In the known method for manufacturing such a semiconductor device (manufacturing method proposed in the national patent DE 1 9935442 (: 丨)), it is usually via ^ 200304188 V. Description of the invention (3) Precise control of the multi-pole groove type through the front of the wafer The gate electrode can reach at least the step between the half of the foot and the top. If this is done, the ion implantation of the gate electrode semiconductor component must reach a sufficient depth. The inside of the trench is located in the body area. The free gate-drain capacitor is used to generate the trench etching of the body to switch on and off the close to the drift region, which needs to be applied so that it is below, which also causes the depth of the total input capacitance region and source region of the gate electrode. Positive depth. When the advance amount of gate oxide is set to overlap a large proportion. The problem can be penetrated through to ensure. The result of the gate and field drift region. It is difficult to pass the gate In the upper oxide of the gate electrode of the electrical trench. The non-drift region is therefore an object of the present invention to propose a semiconductor device with a lower input capacitance and a method for manufacturing such a semiconductor device. The manufacturing method of the features of the scope 1 and 3, and the object of the present invention of the semiconductor group having the features of the scope of the patent application 丨 6 of the present invention. The side wall of the trench performs ion implantation and necessary outward diffusion operation on the 2? Region. The channel contour of the body region and the source region formed by this = formula can be 2 = Edges are self-correcting (the first case), ★ is via "No, two 赭 11 (the first case). 帛 One is through the same edge (for example, one of the two edges or in the groove) One side of the field oxide that is etched down) injects ions into the body and source regions of the poem, and then uses

Page 7 200304188

The body ions diffuse out. In the second case, the ions for the source region are implanted through one side of the auxiliary layer or field oxide, and after the auxiliary layer or field oxide is etched down, the ions for the body region are implanted. Ions are implanted via ^ auxiliary layers or field oxides. In the second case, it is best to adjust the source-to-electrode capacitance to the minimum, and adjust the channel length to be small. The manufacturing method disclosed in the published specification of German Patent DE 1 97202 1 5 A1 is to manufacture a semiconductor device by injecting a dopant material through a side wall of a trench, so as to adjust the threshold voltage of the semiconductor device. Because this method implants the doping material only once, it can only form the source region, but not the body region. / The method proposed in the US patent US 6274437 B1 also only performs an ion implantation operation through the trench side wall. Therefore, neither the method proposed in US patent US 6274437 B1 or German patent DE 1 972 02 15 A1 can solve the problem described in the above (that is, the problem to be solved by the present invention). After the body region is formed, it is better to etch the field oxide disposed on the sidewall of the trench slightly downward, so that the etched down step between the field oxide and the gate oxide is at Slightly lower than the position of the pn junction between the body region and the drift region appearing on the sidewall of the trench. Etching the field oxide down is a technique that can be precisely controlled, that is, the position of the steps can be determined very accurately. After the position of the junction close to the trench sidewall can be determined through the ion implantation parameters, the field can be interposed by appropriate downward etching. Page 8 200304188 V. Description of the invention (5) Electrode oxide and gate The steps between the halides are below the ridges. That's it. In order to minimize the overlap between the gate electrode and the drift region, the purpose of minimizing %% ^ is achieved. Valley of Injustice The aforementioned step does not need to be exactly a horizontal step,

If a step can be a step-like structure, its position is between the gate and the dielectric (field oxide). For manufacturing technology, this step should be made at least at the corners and edges, and 4 is less inclined. Four steps are described below. The next step of manufacturing the source region and the body region is to remove the auxiliary layer remaining in the trench in two ways. ; == Injection Exposure in the upper half of the trench is "material oxide". = And the contact area of the body area. / * θ is really full and a source region is formed at the same time. The type doped doped regions are: Chang Cheng =: The hetero region is usually arsenic, antimony, etc. can also be used as n-type doped erbium / boron ions. However, the prerequisites for phosphorus, sulfur, and ions are (special i ions (such as arsenic and boron ion dopant implantation dose when the same ion implantation mask is used), so boron will be larger than arsenic 7 = Boron. Because the diffusion coefficient of boron diffuses into the semiconductor substrate at a much faster rate than arsenic, 200304188 V. Description of the invention (6). Form f A doped layer doped only with boron ions. Although in the source region It also contains less ions, but the concentration of boron ions is much lower than the concentration of arsenic, so it can be ignored. Ion implantation is usually performed at an implantation angle greater than 0, and this / main input f degree will already be The angle required to avoid the tunneling effect (ChanneHng —Effekten) is calculated. The injection angle is preferably 45 degrees (from the first surface). However, as long as it is between 30 degrees and 60 degrees, The angles are all feasible main angles. If it is to form a very flat contour in the sidewall region of the trench (or a very deep body region and source region, the angle between 15 degrees and 75 degrees is 5 Feasible attention angle. It is best to use-so-called I ^ on I ^ method to carry out oblique ion implantation to ensure that the upper half of all trench sidewalls have ion implantation. The auxiliary layer in the photolithography is usually composed of-layer photoresist In addition to constructing an auxiliary layer using a material suitable for use as an ion implantation mask. For example, a gate electrode can be used as an auxiliary layer. In an advantageous embodiment of the present invention, the gate electrode is deposited. Material: The two electrodes will not cover the entire source region slightly downwards from the trench electrode. In this way, the purpose of the gate-source capacitor is reduced.

The cross-sectional shape of the groove is usually square or trapezoidal, but U can also be used.

£, invention description (7) or V-shaped section. The grooves are arranged on one surface or in a square ▼ -shaped or grid-like shape in the first shape. The shape is set in the semiconductor substrate, and a hexagon, a circle, or an ellipse extends from the first surface into a half. The conducting body region and / or the source region are preferably connected by forming a conductive contact. In one advantageous embodiment, the body contact region and / or the source contact region grooves of the two substrates are contacted into the semiconductor substrate. In one advantageous embodiment, the semiconductor substrate can be placed in a stripe shape and a grid shape at an angle perpendicular to the substrate body. The shape can also be produced by a manufacturing method that can be a rectangular wave shape. Only the side wall ion implantation proposed by the present invention is formed by performing .m on the surface. The doping distribution of the source region is gate-shaped (inverted u-shaped). Therefore, according to the method of the present invention, the body The contact ion implantation of the region can eliminate the need to correct the stripe-shaped trenches, but can set the body contact regions perpendicular to the trenches' and preserve the entire effective area of the semiconductor device. By abandoning the groove strip, the leading amount of the ion implantation edge of the body contact ion implantation can make the cell gate much smaller. Another possible way is to implant the body contact region without masking. In this case, the insulating layer between the source region and the gate electrode in the upper half of the trench must be directed toward the body. Etch down to the trench. Here, the source wiring of the source region can be made via the trench sidewall. << Because silicon dioxide (Si 02) is not only easy to manufacture, but also has low production costs, it is here that silicon dioxide (Si02) is used as the material for the insulating layer and / or the dielectric.

Page 11 200304188 V. Description of the invention (8)

Theoretically, the dielectric is placed in the trench. The ^ T rot oxide layer is made of [oxidized stone as the second material and four edge materials or methods provided on the surface, such as nitriding 1. ·, also can be used Other thin films made of silicon dioxide and silicon nitride, but in terms of: vacuum, or dioxin I method = oxide stone as the gate, oxidation and dioxin μ heat treatment, it is recommended to use silicon dioxide as the dielectric And anti-corrosion oxidation = layer = fruit is the best, so a field of several micrometers can be ignored is the half-piercing voltage of different closed electrodes in different polar parts. The thickness of the insulating layer of the insulating layer provided on the side wall is slightly thicker than that of the electric layer in the layer. There is usually a layer of thickness j to ensure that the gate-drain capacitance can be kept small. The field oxide and the insulated gate electrode t are removed, and it can be used to clear the drift region, just like in the so-called compensation. Semiconductor group ^ heterolayer-like. Therefore, compared with a semiconductor device without a stepped ^ invention, it will have a higher impact, especially in the body region, preferably in the thickness of the trench is usually the degree of the dioxide dioxide. It is set at 20nm to 2 / zm in the lower half of the trench, and tens of nm to 100nm in the upper half of the trench. It is best to use polycrystalline silicon as the material for the gate electrode. Qian 2 conductive material is used to make the gate electrode, such as metal 丨-other similar materials, although this political material is invited, Sheng Gu # ^ metal, or its electrical characteristics. Fang Yiyi Branch is not as good as using highly doped polycrystalline silicon in terms of fabrication technology, physical properties, and conductivity. Page 12 200304188 V. Description of the invention (9) Conductor: Yes = I The method is to semiconductor The device is made into a vertical semi-manufacturing point: the semiconductor device is then made into other shapes, such as === UP-Drain semiconductor device. On the same side of the top half, the polar region, the gate electrode, and the gate electrode are all from the semiconductor substrate below the drift region; the side = vertical flow, but the main advantageous embodiment and- For step improvement, please refer to the other application scopes of the patent application in the subordinate word and the description of the following drawings. Partial cross-sectional views of the Mw guide should be taken by the electric oxide semiconductor field effect guide. The first one in the first picture is a single crystal Shi Xi wafer. The surface of the semiconductor substrate ⑴ is called the wafer front side. The second surface 5 of the semiconductor substrate 被 is referred to as the back surface of the solar panel. Semiconductor substrate (v-(2):: ί (:): often ... the outer body region ⑷ is immediately adjacent to the drift region ，, and the two are described in the following: The interface defines a Qiu junction (21). A strongly n-doped source region (?) Is also provided on the front side of the wafer (2) and the body region (5). A metal oxide semiconductor manufactured by trench technology The component has a groove (8). The groove (8) is located in the semiconductor substrate (丨), and the range starts from the front side of the wafer (2), passes through the source region (7) and the body region (6), and extends into the drift region. (5). In addition, a gate electrode (9) extending vertically from the front side of the wafer (2) into the groove (8) is provided. The gate electrode (9) passes through the dielectric (18, 19) and the sidewall of the groove (丨 〇) and the bottom of the trench (11) are insulated. The trench (8) here is a deep trench called German patent DE 1 9935442 π, and its range extends to the drift region (5). For easy observation and explanation, The section of a trench is enlarged and drawn in the drawing (la). Since the gate electrode (9) and the dielectric (18, 19) in the trench (8) have a step (15), it is located at half of the trench I The thickness of the dielectric in the portion (16) is much larger than the thickness of the dielectric in the upper half (17) of the trench. In contrast, the thickness of the gate electrode (9) in the upper half (17) of the trench is much larger than that of the lower electrode (16) The thickness of the gate electrode (9). If the gate electrode (9) is connected to a positive gate potential, the portion of the body (6) that is tightly pressed against the groove (8) will be invaded by carriers. A channel (20) is formed. If a drain-source voltage is connected between the lead-out lines (D, S), an outflow from the source region (9) is generated, passing through the channel (20), the drift region (5), and the drain. Polar area (4), the current that finally reaches the drain lead (D). However, a prerequisite for this situation is that the position of the step (15) needs to be located in the body area (6) and drift 200304188 V. Invention Note that the position below the pn junction (21) between the regions (5) or slightly above the pn junction. In the semiconductor device of the present invention, the position of the step (1 5) is corrected to exactly The pn junction (21) is located on the same plane, or slightly lower than the pn junction (2 1). This corrective action can be taken from The dynamic correction is performed by the upper edge of the field oxide (18) derived from the step (15) when the body region (6) and / or the source region (7) are manufactured. ) Is connected to the drain lead (D) through a large-area drain metallization layer (12) provided on the back surface (3) of the wafer. There is a source metallization layer (1 3) on the front surface (2) of the wafer The source metallization layer 3) forms a conductive contact with the source region (7) and the body region (6) via a shunt. The metallization layer (13) and the gate electrode (9) are separated by an anticorrosive oxide layer (丨 4) which insulates the two. There are a variety of materials that can be used to make the anticorrosive oxide layer (14), for example, borophosphosilicate glass "to plutonium. The source metallization layer (13) is connected to the source lead (s) on the front side of the wafer (2), the gate electrode (9) is connected to the gate lead (G). In the arrangement of the semiconductor substrate (1), the area covered by the gate electrode (9), the body region (6), and the source region (7) is a trench. The trench metal oxide semiconductor f-effect transistor (MOSFET) has a cell field (ZF) composed of many cells, while the cross-section of the figure shows only two cells. Each cell contains a single cell Crystal: The load line of many single transistors in parallel forms a metal oxide semiconductor field effect transistor (MOSFET). In addition to the cell field (ZF), the first

Page 15 200304188 Part of the oxide semiconductor field effect transistor (MOSFET) fringe region (RB). Although there are grooves in the edge region (RB), the cells in the edge region (RB) do not contribute to the total current. The following two examples illustrate two methods for manufacturing the semiconductor device of the first figure proposed by the present invention. The first manufacturing method (second figure) ... The seed manufacturing method includes the following steps. The second figure uses the same reference numerals as the first figure. (a) First prepare an n-type doped semiconductor substrate (1). Then, the trench (8) is etched down from the front side (2) of the semiconductor substrate (0). (B) A layer of field oxide is added to the entire exposed surface of the front side (2) of the wafer by using a pedestal method. (1 8). (C) Forming an auxiliary layer (2 2), such as a photoresist, in the trench (8) in the trench (8) by using the> product method. The bottom of the trench (8) etches the auxiliary layer downward so that only a section of the photoresist pillar (22) is located in the trench. (D) The field oxide (8) is etched downward to oxidize the field electrode The upper edge (15) of the object (18) is at the same height as the top of the photoresist stub (22). (E) Boron ions and arsenic ions are then implanted into the semiconductor substrate (1) via ion implantation. The ion implantation step is When the ion implantation is performed by the oblique implantation method with an implantation angle of 45 degrees, the photoresist pillars (22) and the field oxides (18) provided in the trenches (8) are used as implantation masks. Arsenic and / or boron

Η Page 16 200304188

Therefore, two 1 are inserted into two surfaces (2) and a side wall (10) of the groove (8). In this example, the native impurity agent 1 is about 5 X 10 "cm-2, and the doping dose of boron is about JX cm. In order to allow the sidewall sidewalls (10) to be uniformly implanted with ions, so: The quadrant ion implantation method is used to perform the ion implantation work. The ions are then subjected to a diffusion step, the purpose of which is to expand the butterfly into the semiconductor substrate (1). This will form the next to the surface, and Strong n-type doped source region (7) on trench sidewall (10), and weak p-type doped body tightly on source region (7) and trench sidewall (10) Area C6). § After the ion implantation step and the diffusion step are completed, the photoresist stubs (22) remaining in the trench (8) are removed. Then, the field oxide (18) is etched downward until the field oxide is oxidized. The position of the upper edge (15) of the object (18) is lower than the junction (21) immediately next to the trench (8). (H), the house is oxidized by heating to form a gate oxide in the trench (8), and The trench (8) is filled with silicon. Then, the polycrystalline silicon overflowing on the wafer = surface (2) is removed by etching, leaving only the (9) in the trench (8). many Since the manufacturing method of the source metallization layer (1 3), the drain metallization layer (丨 2), and the passivation θ (1 4) are known techniques, the potential need not be explained here. Manufacturing method (third picture): The second manufacturing method proposed by the present invention has a part of manufacturing steps and

Page 17 200304188 V. Description of the invention (14) A manufacturing method is the same, that is to say, these two methods are all the way to the formation of the photoresist pillar (2 2) and the field oxide (1 8) (equivalent to the first (A)-(b)) of one method are all the same. Up to this step, the photoresist stubs (2 2) formed in the trenches (8) and the sidewalls (10) and the bottoms (11) of the trenches (8) are insulated by a field electrode with an insulating effect. (18). Here are the next steps. (A) Implanting arsenic ions with a doping dose of 5 X 1014-1 x 10 ΐ δ cm-2 into the semiconductor substrate (1) at an appropriate implantation angle (usually 45 degrees), and preferably using a quadrant ion implantation method. In this way, a strongly n-doped source region (7) can be formed next to the surface (2) and the sidewalls (10). (B) A photoresist stub (22) is then etched downward for masking in the subsequent field oxide etch step. The field oxide (丨 8) to be used as an ion implantation mask in the subsequent ion implantation step is etched down to the same length as the photoresist stub (2 2) etched down. After the height, boron ions with a doping dose of about 1013 cnr2 are implanted into the semiconductor substrate (1) at an appropriate implantation angle (usually 45 degrees). In this way, a weakly P-doped body region (6) immediately adjacent to the source region (7) and the trench (8) can be formed. (C) Next, the field oxide step (5) is etched down to a position lower than the edge of the pn junction (21) immediately above the trench. Due to the accuracy of the engraving of 22, the field oxide ⑽ must be etched down to a position below the 叩 junction (21). In this way, the minimum distance required between i) and the edge of the ρη junction (21) can be reduced to the lowest degree of privacy ', so as to reduce the gate-off capacitance. One

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The steps are the same as the first manufacturing method, that is, removing the photoresist (22) grooves (8), setting gate oxide (19) in the grooves (8), and forming a metallization layer ( 1 2, 1 3). In order to enable the source region (7) and the body region (6) to contact the source electrode (13), the contact region must have a high doping concentration. A common method is to directly set a highly doped contact region on the source region (7) and the body region (6) to form a contact-connected region. After the oblique ion implantation through the sidewall of the trench is completed, the source region (7) and the body region (6) will have a doping direction (inverted U shape) toward the surface (2). distributed. The body region (6) is a body contact region (23) required for forming contact contacts, and is arranged in a direction perpendicular to the strip-shaped cells and / or grooves (8). In the existing method of manufacturing a semiconductor device, the body contact area (23) is educed to be aligned in the direction of the cell and / or the groove (8). Therefore, the body contact area (8) and the groove (8) There must be a minimum spacing between them. The fourth figure shows an advantageous way of contacting the body region (6) in the semiconductor device of the first figure. In order to form the body contact region (2 3), boron ions with a high doping concentration should be implanted into the semiconductor substrate (1) under the condition of using an ion implantation mask perpendicular to the stripe grooves (8), Boron ions implanted into the semiconductor (1) will change the original doping profile of the source region (7) from the surface to the body region (6), but the prerequisite is that the implanted boron ions The p-type doping formed at the dopant / dopant concentration at this site needs to be significantly larger than the n-type doping of the original source region (7) there. The source region tab (24) is located in the body contact region (23).

200304188

The position of the tight groove (8) above the channel (20) within the range. These source regions are connected

(24) Connected to each other from the side via the source region covered by the ion implantation mask of the body region. The body contact region can also be passed through the surface (2) to the source region (3) without masking. (23) Perform ion implantation. In order to form the contact of the source region (7), the gate oxide (19) and the gate electrode (9) located in the trench (8) must be etched down until the source region (7) can be removed from The contact is formed on the side through the groove sidewall (10). However, this embodiment is not drawn in the fourth. The application range of the manufacturing method of the present invention is not limited to the embodiment shown in the first figure-4, but can be produced through the exchange of conductive types (type 11 and Ps) / and changing the doping concentration, etc. Semiconductor components. Although the embodiments described above are all semiconductor devices of trench type metal oxide semiconductor field effect transistor (MOSFET), the application range of the manufacturing method of the present invention is not limited to the manufacturing of such semiconductor devices, but may be Used in the manufacture of trench IGBTs. In summary, it can be known that using the method of the present invention, that is, in the case of using a field oxide as a mask, injecting a dopant material through a trench sidewall by oblique ion implantation can be very simple, but But it is very effective to control the position of the gate electrode step to be slightly lower than Qiu Jie between the body area and the drift area.

200304188 V. Description of the invention (17) The above-mentioned embodiments are only used to explain the principle and practical application of the present invention, but only a few changes by professionals can greatly expand the application mode and scope of the present invention. iim Page 21 200304188 Brief description of the drawings The first picture: a semiconductor device constituting a trench type gold transistor (MOSFET) according to the present invention = a cross-sectional view of a semiconductor field effect T. First image U) ··· It is an enlarged view of a part of a groove (a). The second diagrams (a) to (h): how to manufacture the semiconductor device of the first diagram is partially broken. (A) The two-heart manufacturing method. (A) to (c) The fourth figure of the second method of manufacturing the semiconductor device of the second-figure manufacturing method is shown in the fourth figure. It is the first sectional view of the manufacturing body-source contact. Description of component symbols 1 semiconductor device 4 non-polar region 7 source region 1 0 trench sidewall 1 3 source metallization layer 1 6 lower half of the trench 1 9 gate oxide 2 2 photoresist stub 2 Front side of the wafer 5 Drift region 8 Trench 11 Trench bottom 14 Anticorrosive oxide layer 1 7 Upper half of the trench 20 channels 23 Body contact area 3 Back side of the wafer 6 Body area 9 Gate electrode 1 2 Non-polar metallization layer 1 5 Step 1 8 field polar oxide 21pn junction 2 4 source area connection page 22200304188 The diagram briefly illustrates D and pole lead S source lead G gate lead ZF cell field RB edge region Iϋ · page 23

Claims (1)

200304188 VI. Scope of patent application 1 · A method for manufacturing a semiconductor component that can be controlled by field effect, the gate electrode (9) of the semiconductor component is arranged in the trench (8), and the dielectric component (18, 19) and other components The parts are insulated. The steps of this manufacturing method are as follows: (a) Prepare a semiconductor substrate of the first conductivity type (0, and then etch out at least the semiconductor substrate (丨) from the first surface (2) downward. A groove (8); (b) covering the side wall (10) and the bottom (丨 丨) of the groove (8) with an insulation (18); '(c) the groove (8) with an auxiliary layer (22) 8) the lower half (16) is filled; (d) the part of the insulating layer (18) not covered by the auxiliary layer (22) is removed; (e) the insulating layer remaining in the trench (8) (18) and / or the auxiliary layer (22) are used as ion implantation masks, and the first and second conductive ions are implanted into the semiconductor substrate (1) through the trench sidewall (10) and reserved for the source region (7). 2. The manufacturing method according to any one of the aforementioned patent applications, characterized in that: The type ions are expanded outward from the body region (6) to form the body region (6). ', 3. A method for manufacturing a semiconductor device that can be controlled by field effects, and a gate electrode ((9) of the semiconductor device is provided in a trench (8), and insulated from other parts through the dielectric (18, 19). The steps of this manufacturing method are as follows: (A) Prepare a semiconductor substrate (1) of the first conductivity type, and then from the first surface (2) at least one (8) is etched from the semiconductor substrate (1) upward and downward; Page 24 200304188 VI. Patent application scope (B) Cover the trench (8) with an insulating layer (18) on the side wall (10) and bottom (u); (c) use an auxiliary layer (22) to cover the trench (8) The lower half (16) is filled; (D) The portion of the insulating layer (ι8) not covered by the auxiliary layer (22) is removed; (E) The insulation remaining in the trench (8) The layer (18) and / or the auxiliary layer (22) are used as an ion implantation mask to inject the first conductive type ions into the semiconductor substrate (1) via the trench sidewall (10) to form a source region (7) . (F) etching down the remaining insulating layer (丨 8); (G) using the insulating layer (18) and / or the auxiliary layer (22) remaining in the trench (8) as an ion implantation mask, Two kinds of conductive ions are implanted into the semiconductor substrate (1) through the trench sidewall (0) to form a body region (6) next to the source region (7). 4. The manufacturing method according to item 3 of the scope of patent application, characterized in that the auxiliary layer (22) is further etched downward before step (G), and the insulating layer (18) is not covered by the auxiliary layer (22). Partially removed. 5. The manufacturing method according to any one of the aforementioned patent applications, which is characterized in that after the body region (7) is formed, the insulating layer (18) is etched downward to directly etch the upper edge of the layer (18) (15) The pn junction (21) slightly lower than or slightly higher than the body region (6) and the half f edge U) hits the position of the groove preparation wall (10). i 6. The manufacturing method according to any one of the foregoing patent claims, characterized in that after the step of ion implantation is completed, the following steps are performed: 1 is-a-removing the auxiliary layer (22);-in the trench ( 8) Another original-ratio insulation is provided on the exposed side wall (10) 200304188 VI. Patent application layer (18) Thin insulation layer (19);:-Fill the trench (8) with a suitable conductive material (9); Λ The contact forming the gate electrode is conductive The method of forming a body contact region (23) of the body through the ion is to inject the second surface (2) into the semiconductor substrate (1) to form a body contact region (23) to generate a body region (6). The auxiliary layer (22) of any item in the range is composed of a photoresist. It is characterized by the following: 8. If the scope of application for patent is item # 5-9. If any of the electric type ions in the scope of the aforementioned application for patent uses Shishen ion as the first kind of injector, λλ * 'is characterized For: 10. The manufacturing method of item, its electric ion. The characteristics are as follows: 1. Any of the foregoing methods in the scope of the above-mentioned application patents uses rotten ions as the second type of implantation1. As described above, the manufacturing method of the Du-type conductive ion implantation item in the scope of the application for patents is characterized by: The dose is an order of magnitude higher. The manufacturing method of the implant of at least two kinds of conductive ions is as follows: 12 · As mentioned in the previous application 200304188 The first conductivity type ions and / or the second conductivity type ions are in a range of 15 to 75 degrees (especially 30 to 60 degrees, and preferably 45 degrees) to the first surface (2). Angled way to inject. 13. The manufacturing method according to any one of claims 4 to 4, wherein the ion implantation step is performed by a quadrant ion implantation method. 14. The manufacturing method according to any one of the foregoing patent claims, characterized in that: the first conductive type ion is shielded by a mask on the first surface (2), the semiconductor component (1)), To form a body contact region (23), which is formed by the body contact region (23) that is perpendicular to and aligned with the groove (8).疋 15. The manufacturing method according to any one of the aforementioned patent application scopes, which specifically forms a body contact region (23), and the second conductive type ion is masked by a large surface ==. A surface ⑴ is injected into the semiconducting product and does not m), and the material forming the gate electrode (9) is downward (where the piece electrode region (7) and the trench sidewall (10) border. Endogenous source 16 · A component that can be set in a semiconductor substrate: 〃Thousands of conductors of the first conductivity type-having at least one drain region (4, 5) and at least one source region (7), at least one setting Between the drain region (4, the body region (6), 5 of the two conductivity types) and the source region (7) Page 27, 200304188 VI. Patent application scope-at least one trench that extends from the first surface (2) through the source region (7), the body region (6), and extends into the drain region (4, 5) (8), °°-at least one gate electrode (9), the gate electrode (9) is arranged in the groove (8), and is insulated from the semiconductor substrate (1) by a dielectric (18, i 9), The dielectric in the upper half of the trench (17) is a thinner gate oxide (19), and the dielectric in the lower half (16) of the trench is a thicker field oxide (18), and There is a step (15) at the junction of the field oxide (18). The characteristic of the dagger-type conductor assembly is that the body region (6) is at least: The contact position is based on a step-like step (15). (1) From the above, the port P of the soil (10) as described in item 16 of the aforementioned patent application range is covered by the gate electrode (9). 1 In 8. Second ΐ: The semiconductor group of the first or the second item of the patent scope, which is characterized by. Grid opening, ϋ 2) in the layout design, the trench ⑻ is made into a strip: ⑺, or It has a rectangular wave shape. Status and features: Semiconductor components in any of the 16th to 18th of the scope of patent application, a ⑵) of this article: The contact of the body area (6) is turned on, so the body contact area is set, next to the The direction of the contact area (23) is perpendicular to the groove ⑻ and is perpendicular to the groove (8). Page 28 200304188 VI. Patent application scope 2 〇 ^ As for any one of the items in the patent scope 16--19 The semiconductor device is characterized in that the thickness of the field oxide (18) is between 20 nm and 2 / z, and the thickness of the gate halide U9) is between several nm and 0mm. For a semiconductor device of any one of the 16th to the 20th patent scope of the patent application, the gate electrode (9) contains polycrystalline silicon, and the insulating layer (18, 19) contains silicon oxide (Si). 2). ^ 3 5-Tick 2 A semiconductor device according to any one of the 16th to 21st scope of the patent application, where 1 is a semiconductor device made into a vertical semiconductor device. 〃 2 3 In particular, if the semiconductor device according to any of claims 16-21 is applied for, the semiconductor device is made into an up_j type semiconductor device. Page 29