SU993444A1 - Pseudorandom sequence generator - Google Patents

Description

The invention relates to a pulse technology and can be used to form test sequences for monitoring and diagnosing malfunctions of digital automatics, telemechanics, and computing equipment.

A device for generating pseudo-random signals of a complex structure, comprising a clock, a pseudo-generator, is known. Before the random sequence, the AND element, the electronic key, the clock counter, the NOT element, the decoder, the cycle counter and the trigger, allow us to generate repetitively repeated periods of pseudo-random behavior that are shifted one relative to the other for a given time interval 11.

The disadvantage of this device is the impossibility of forming a pseudo-random sequence in the opposite direction and blocking the output signals of the device: on separate segments of the sequence,

The closest in technical essence to the present invention is a 17 pseudo-random sequence generator, comprising a generator

Tov pulses. And element, the first input of which is connected to the output of the clock generator, computing the counter, the counting input of which is connected to the output of the element And, a group of elements And whose output1 are the generator outputs, h-bit reverse shift register, the installation input | connected to the bus installation, the synchronization input is connected to the output of the element AND, and the outputs are connected to the first inputs of the group of elements AND, the first and the second modulo-two adders, whose inputs are connected to the outputs of the reverse shift register, and the outputs are connected respectively with. The first and second information inputs of the reverse shift register are 2. . .

A disadvantage of this device is its limited functionality, because when using a pseudo-random generator as a source of input test effects of controlled devices, in a number of cases it is not directly used by the generator code sequence. This is because, in these devices, uncertainties arise due to the simultaneous change of several input actions, the appearance of forbidden combinations at the inputs of monitored devices and other reasons. Sometimes, to check the correct functioning of devices, it is necessary to repeat certain sections. Sequence of generator codes (conversion circuits), therefore, when monitoring, it is advisable to use not the entire pseudo-random code sequence, but its individual sections, formed in the forward or backward direction, with or without blocking generator, for this, it is first necessary to compile a program for checking the monitored devices, determining the order and nature of the formation separate portions of the pseudorandom sequence. Perform this program by changing the functions manually performed by the generator, as in the known devices., Mp / long and practically impossible due to the high rate of change of the test actions of the monitored devices.

The purpose of the invention is to automate the process of forming the programmed sections of the generated sequence.

The goal is achieved by the fact that the pseudorandom sequence generator., Which contains a clock pulse generator, the output of which is connected to the first element of the AND element, the output of which is connected | To the counting input of the counting counter, and the synchronizing input of the n (bit reverse shift register, whose installation input is connected to the installation bus, the first and second information inputs are connected, respectively, through the first and second modulo two adders with the corresponding outputs of the n-bit reversing the shift register, the outputs of which are also connected to the first 1 and inputs of the AND block, are additionally introduced a buffer storage unit, a register: shift and a control block, the first input of which is connected to the installation bus, the second input is connected by the clock output, the third input is connected with the output of the subtracting counter, and the fourth input is connected to the first output of the shift register :, the first output of the control unit is connected with the second input of the And element, the second output is connected to the read input of the buffer storage unit,. an installation input of which is connected to the installation bus, which controls the output of the buffer storage unit

It is connected to the inputs of the record of the deducting counter and the shift register, and the first and second group of outputs are connected to the information inputs of the deducting counter and the shift register

respectively, with the second and

the third outputs of the shift register are connected to the control input of the n-bit reverse shift register and to the second inputs of the block of elements I.

The drawing shows a functional diagram of the generator of pseudo-random sequences.

The pseudo-random sequence generator contains a block of 1 elements AND, G1-bit reversive perjiCTp 2 shift, adders 3 and 4 modulo 2, element 5, subtractive counter 6, shift register 7, generator 8 clock ig-pulses,

control unit 9, buffer storage unit 10, installation bus 11, bus 12 information inputs, write bus 13. . .

The drawing also shows an example of executing a buffer storage unit 10, which contains a random access memory unit 14, with an address checker 15, an OR element 16, and a pulse shaper 17.

The control unit 9 is executed on D-triggers.

The generator works as follows.

Before the start of work, a program is formed to form the output pseudo-random sequence of codes as a sequence of control words. Each control word has a (n + 3) bit, where n is the register size 2. The first control word of the A1 ... APs contain a binary code for the length and length of a pseudo-random sequence in which the generator performs one of the possible operations provided for in the operation code. The operation code is contained in (n + 1), (n + 2), (n + 3) -th digits of the control word. (Ao4-t. Ati ,,) .- Digit А „4.1 contains the end of program sign. in the last control of the program word, and in the remaining words Af ,. 1. The discharge determines the direction of the formation of a segment of a pseudo-random sequence: in the forward direction at А ti + 2 1 and in the opposite direction at An + 2 0. The discharge, А & .3, determines the state of the generator output. If A 1 / then the output is generated by generated-. torus sequence of codes. Eoni (An + ji 0, then the logical O level is maintained at the output, and the sequence of codes generated by the generator does not reach the consumer. 5 (masked).

The compiled program is loaded into block 10, where it is stored and can be reused. Before loading the program with a signal on bus 11, the counter is zeroed.

15 addresses of the block 10 On the bus 12, the first control word of the program is supplied and is written to the zero memory cell by a signal on the bus 13. The signal from the bus 13 via the OR element

16 enters the counting input of the counter 15 and, with its falling front, transfers it to the next state. Similarly, in block 14, the remaining control words of the program are recorded. After loading the program with a signal

on bus 11, counter 15 is reset again and register 2 and control block 9 are reset to initial states. At the output of the control unit 9, a signal is generated, inputted to the readout input of the unit 10. The information inputs of the unit 10 receive the first control word from the zero memory cell. The signal from the output of the driver 17, delayed relative to the signal at the read resolution input of block 14, rewrites the first n bits of the control word (e) to the subtracting counter b, a (n + 1), (n + 2), (n + 3) bits (operation code) - to register 7 After the control word from the block / 10 is finished reading, the first output of the control block 9 shows a signal allowing the passage of pulses from the generator 8 clock pulses through the element 5 to the input of the synchronization register 2 and on the counting input subtractive counter 6. When this is, depending on the signal At the shift direction of the register 2, the information in the register 2 is shifted in the forward or backward direction, and a pseudo-random sequence of codes is generated in the forward or backward direction. Depending on the state of the third register 7, the generated code sequence is fed to the output of the device or blocked by. block of elements And 1. Each pulse; at the output of the element And 5 reduces the co-held by the subtracting counter b by one. After L register shifts 2, the counter b is zeroed, at its output Z a signal is generated, which enters control unit 9. As a result, the output of control block 9 is a signal that prohibits the passage of pulses through element 5. This ends the formation of the first segment of the pseudo-random sequence / codes corresponding to the second control word npoipaMivH. After this, control block 9 generates a signal to the read enable input of block 10, and the second control

the program word is rewritten to 6 and the register 7. An ikovy segment of a pseudo-random sequence of codes of code is formed in accordance with the operation code recorded in register 7 with a length of & codes listed; in counter 6, etc. The control of the program's words is read in order from block 10 until the last control word passes through the end of the program, which blocks in block 9 of the control the issuance of read permission signals to block 10.

Thus, introducing into the generator 15 pseudorandom sequences of control block 9, register 7 and block 10 allows organizing automatic generator operation according to a previously developed program, the possibility of composing an output sequence of codes from individual segments of a pseudorandom sequence formed in the forward or reverse direction, blocking

25 or without blocking the output of the device, which makes it possible to more effectively use the generator to monitor and diagnose digital devices.

thirty

Claims (1)

Invention Formula A pseudorandom sequence generator containing a clock pulse generator, the output of which is connected to the first input of an elec- ment And, the output of which is connected to the counting input of the subtractive counter, and to the synchronizing BXOKLp-bit reversing register 40 shift, the installation input of which is connected to the installation bus, the first and second information connections are connected, respectively, through the first and second modulo-two adders 45 corresponding, the outputs of the h-bit reversible shift register, the outputs of which are also connected to. the first inputs of the block of elements And, about tl and cha with the fact that / JQ in order to automate the process of forming the programmed sections of the generated sequence, a buffer storage unit is added to it, relistr shift f and the control unit, the first input of which is connected to the installation bus, the second input is connected to the output of the clock pulse generator / the third input is connected to the end of the subtractive counter, and the fourth input is connected to the first output of the shift register; the first output of the control unit is connected to the second input of the element; And, the secondary output is connected to the input with a buffer seam of its unit, the installation input of which is connected