SU953734A1 - Pulse train frequency controllable divider - Google Patents

Description

(54) CONTROLLABLE DIVIDER OF FREQUENCY OF FOLLOWING PULSES

one

Lzobregenje refers to pulse technology and can be used in digital measuring equipment, in computing devices and in automation and telemechanics devices .:

A controlled pulse frequency divider is known, comprising a pulse counter on triggers, a match element, and an element OR 1

The disadvantage of this device is; low reliability of operation.

The closest to the technical noun-; Bone of the invention is a controlled pulse frequency divider,. containing a pulse counter, on Tpmre j pax with the first inputs of the corresponding match / match elements, the second inputs are connected to the control code code of the division factor, and the outputs are; to the corresponding inputs of the element OR 20 whose output is connected to a single trigger input whose zero output is connected to the information inputs of the trigger triggers of the video input counting

the input of which is connected to the input bus and the first input of the additional coincidence element, the second input of which is connected to the single output of the trigger, and the output to the zero input of the trigger 2.

A disadvantage of the known device is the low reliability of operation, due to the fact that after the end of the cycle of dividing the frequency of the input pulses and the pulse counter, the next input pulse does not change the state of the pulse counter, since the latter is blocked to the input to zero.

The purpose of the invention is to increase the reliability of the device.

Claims (2)

The goal is achieved by the fact that a controlled pulse frequency divider containing a pulse counter is triggered, the zero outputs of which are connected to the first inputs of the corresponding elements of the assembly, the second inputs of which are connected to the bus. We control the code of the coefficients of delNII, and the outputs - to the corresponding inputs of the first OR element, the output of which is connected to the single trigger input, the zero output of which is connected to the information inputs of the pulse counter triggers, the counting input of which is connected to the input bus, the second OR element is entered, the first the input is connected to the input bus, the remaining inputs are connected to the single outputs of the corresponding pulse counter triggers, and the output to the zero input of the trigger. The drawing shows a block diagram of the device. It contains a counter 1 pulses on triggers, trigger 2, elements 3 are matched, elements 4 and 5, OR, bus 6 controls the dividing factor code, b is the front bus 7, and exitsiny 8. In the initial state, all triggers of counter 1 trigger 2 are set to zero . On tires b, a code is set corresponding to the selected division factor, at the output of element 4 there is a level one, and at the output of element 5 it is level zero. Upon receipt of the input pulses, the device operates as follows. Counter 1 counts the input pulses until it sets a code that matches the division coefficient code. Prior to this, at least one of the elements of the match 3 has a unit level. When installed in the meter. 1 of the code, which coincides with the code of the division factor, at the outputs of all elements of the coincidence 3 there are zero levels in the vehicle, and therefore, the output of element 4 also has a zero level which will set trigger 2 into one state. At the same time, on the output bus 8, the splitter will receive a single-level signal, and the triggers of the counter 1 will be set to the zero state. The value of the signal at the output of element 5 is determined by the state of the triggers of counter 1 and the value of the input signal of the divider. Therefore, the zero level in the course of the element 5 in the Wits only when the input impedance of the divider has ended, and all the triggers of the counter 1 will be set to the zero state. In this case, the trigger 2 will also be set to the zero state, as a result of which the counter zeroing stops and the divider output pulse terminates. In the future, the engine works as described. As a result, pulses with a frequency proportional to the frequency of the input pulses and an inversely proportional number, whose code is set on the buses of the control code for dividing ratio, appear on the output bus of the divider 8. The use of a reset trigger of the secondary OR element for controlling resetting to the initial state, the inputs of which are connected to the divider input bus and to the single outputs of the trigger triggers of the counter, distinguishes the proposed frequency divider from the known one, as the possibility of a glider error that could occur may decrease. due to a violation of the operating conditions of the divider counter. As a result, the reliability of operation of such a frequency divider is increased, which makes it possible to increase the accuracy of the equipment in which such frequency dividers are used. Claims of the Controllable Pulse Frequency Divider, containing a pulse counter, on triggers, zero outputs of which are connected to the first inputs of the corresponding match elements, second inputs of which are connected to the coefficient control codes, and outputs to the corresponding inputs of the first OR element, whose output connected to a single trigger input, zero output — which is connected to information inputs of impugus counter triggers, the counting input of which is connected to the input bus, ex This is due to the fact that, in order to increase reliability in operation, a second OR element is introduced into it, the first input of which is connected to the input bus, the remaining inputs are connected to the single outputs of the corresponding pulse counter triggers, and the output has zero input of the trigger. Sources of information taken into account during the examination 1. USSR author's certificate number 456366, cl. H 03 K 21/36, 1972. 2. USSR author's certificate number 594585, cl. N OZ K 21/30, 1976. one R