SU875608A1 - Device for programmed delay of pulses - Google Patents

Description

and the duration of the input impulse, as well as the impossibility of changing the duration of the output delayed pulse, which in this device is always approximately equal to the duration of the input pulse.

The closest to the invention in its technical essence is a programmable pulse delay device comprising a generator, five triggers, an inverter, three AND elements, three AND-NES elements, and a DJ counter.

However, this device is characterized by the impossibility of changing the duration of the output delayed pulse, which in this device is always approximately equal to the duration of the input pulse. In addition, the accuracy of the reference front and rear edges of the output delayed pulse in a known device is equal to the period T of the pulse from the generator output. Equipment costs for the implementation of this device programmable pulse delay are also high. These disadvantages reduce the functionality and accuracy of the known device.

The purpose of the invention is to expand the functionality and improve the accuracy of the device programmable pulse delay.

The goal is achieved in that a programmable pulse delay device containing a generator, five triggers, an inverter, three AND elements, three AND-NOT elements and a counter, the first group of information inputs of which are connected to the group of information inputs of the device whose output is connected to the output of the third trigger , a register is entered and an AND-IL element, with the control input of the register of keys to. to the second control input of the device, the zero input to the zero input of the third and fourth triggers, the counter, to the first input. The first and second elements I and to the zero input of the device, the information inputs of the register are connected to the first group of information inputs of the counter, and the outputs to the second group of information inputs of the counter, the first control input of which is connected to the first control input of the device, the second control the input is to the output of the third element AND, the counting. input is to the output of the AND-OR element, and the output of the counter is connected to the counting inputs of the third and fourth triggers and to the first input of the third element AND, the second input of which is soy Inonii with the inverted output of the fourth flip-flop direct output of which is connected to the counting input of a fifth flip-flop inverse output is connected to vtoryky - nensoro and second inputs E

cops And, and a zero input with the output of the third NAND element, the first input of which is connected to the inverse output of the first trigger and to the third inputs of the second element AND of the second AND element, and the second input to the inverse output of the second trigger, to the third input of the first element AND to the third input of the first element AND-NOT, the first input of which is connected to the generator output, to the second information input of the AND-OR element and through the inverter to the first input of the second AND-NOT element and to the first information

the second input of the first AND-NOT element is connected to the second input of the second AND-NOT element and connected to the third control input of the device, and the output of the first AND-NOT element is connected to the recording input of the first trigger, which connects the input connected to the output of the first element AND, and the direct output to the first control input of the AND-OR element, the second control input of which is connected to the direct output of the second trigger, the recording input of which is connected to the output of the second AND-NAND element, and obnuyushchy entrance g with exit second item I.

Figure 1 shows the functional diagram of the device; figure 2 - diagram of the work; devices.

. The device for programmable pulse delay contains a generator 1, the output of which is connected to the first

the input of the first element AND-NOT 2, to the second information input of the element AND-OR 3 and through the inverter 4 to the first input of the second element AND-NOT 5 and to the first information input of the element AND-OR 3. The second input of the first AND input 2 is connected to the second input of the second element AND-HE 5 and is connected to the third control input of the device. The third input of the first element AND-NOT 2 is connected to the third input of the first element Ib, with the inverse output of the second trigger 7 and the second input of the third element AND-NOT 8. The output of the first element AND-NOT 2 is connected to the recording input of the first trigger 9, folded The input input of which is connected to the output of the first element Ib., the direct output to the first control input of the element AND-OR 3, and the inverse output to the first input of the third element AND-HE 8, to the third input of the second ele1 "And 10 and with the third input element AND-NOT 5. The output of the second e-item AND-NOT 5 is connected to the input in the record of the second trigger 7, the input of which is coupled to the output of the second AND 10, and the direct output to the second control input of the AND-OR 3 element, the output of Yotori which is connected to the counting input of the counter (a 11. The first control input of the counter 11 is connected to the control unit's control input terminal, and the second control input of the counter 11 is connected to the output of the third element And 12. The first group of information inputs of the counter 11 is connected to the information inputs of the register 13 and connected to the information inputs of the device. The second groups of information inputs of counter 11 are connected to the outputs of register 13. The output of counter 11 is connected to the counting input of the third trigger 14, to the counting input of the fourth trigger 15 and to the first input of the third element 12, the second input of which is connected to the inverse output of the fourth trigger 15. The forward output of the fourth trigger 15 is connected to the counting input of the fifth trigger 16, the zero input of which is connected to the output of the third of its element 8. AND 8. The inverse output of the fifth trigger 16 is connected to the second inputs of the first and second 10 elements AND The first input of the first element I 6 is connected by the first input of the second element I 10 with the balancing inputs of the counter 11, register 13, the third trigger 14, the fourth trigger 15 and connected to the biasing input of the device. The control input of the register 13 is connected to the second control input of the device. . The device works as follows. The null-in input of the device from the central control unit (not shown) receives a null signal, which sets the device to the zero state. Then on the counter 11 in the first group of information inputs., Associated with the information inputs of the device, the number a is recorded. ".1.,. where n is the number of bits of the counter 11, equal to the number of bits of the register 13; which is necessary for M (G time. delay the input pulse T - the period of the pulses from the output of the generator 1. Information is recorded on the counter 11 through the first group of information inputs produced When there is a signal at the first control input of the counter 11 After the information is written to counter 11, the number 2 - i - 1) is recorded at 13 data recourses in the device, where 1 ddr & amp. is the duration of the output delayed pulse. Recording information on the register 13 of the device's Q-information inputs is carried out when there is a signal at the control input of the register 13 connected to the second control input of the device, at the output signals of the generator 1 (Fig. 2a)) are pulses of a duration and following with a duty ratio equal to 2. When entering the third control input device of the input pulse (Fig. 2c), which must be delayed, the first 2 or second 5 I-NOT elements are triggered, which set the first 9 or second 7 triggers to one, respectively. e state. The operation of the first 2 or second 5 NAND elements is performed depending on how the leading edge of the input pulse is located in relation to the pulse sequence of generator 1. If the leading edge of the input pulse coincides with the level of the logical unit of the output pulse sequence of generator 1, then the first the AND-NE 2 element and the first trigger 9 are set to one. If the leading edge of the input pulse coincides with the logic level of the output pulse sequence of generator 1, then the second element is triggered. AND-NOT 5 and the second trigger 7 is set to one. Consider the operation of the device in the case of an input pulse (Fig. 2c), the leading edge of which coincides with the level of the logical unit of the output pulse sequence (Fig. 2a) of the generator 1. When such an input pulse arrives, the first AND-NO element 2 (Fig. 2d) is triggered. and the first trigger 9 is set to one (FIG. 2e, e). The logical zero level of the inverse output of the first trigger 9 blocks the operation of the second element AND-NOT 5 and maintains the second trigger 7 in the zero state. From the direct output of the first trigger 9 to the first control input of the AND-OR 3 element, the resolving level of the logical unit arrives. Therefore, the pulse sequence from the output of the inverter 4 (Fig. 2b) through the element AND-OR 3 (fkg.2zh) is fed to the counting input of the counter 11, and the delay time of the input pulse begins. Thus, the starting time of the input pulse delay in the proposed device is performed after a time equal to the half-cycle of the pulse sequence of the generator 1. In the known device, the starting time of the delay time of the generator is pulsed, i Counter 1-1 changes its state after the end of the input momentum.

act on his counting entry. When all the bits of the counter 11 are in the single state, then when another pulse arrives at the counting Bxojf, the output of the counter 11 generates an overflow signal (Fig. 2z, on the front side of which the third trigger 14 is set to one) (Fig. 2i) The overflow signal through the third element I 12 (Fig. 2m), to the second input of which the resolving level is fed from the inverse output of the fourth trigger 15 (Fig. 2 l), acts on the second control input of the counter 11, and on which information from register 13 to second information These inputs are recorded on the counter 11. The delayed pulse duration is set to 4. On the falling edge of the overflow signal, the fourth trigger 15 is set to one state (Fig. 2k), the logical zero level of which inversion (Fig.2l) blocks the passage of the signal from the counter 11. through the third element I 12. On the leading edge of the second overflow signal (Fig. 2z), the third trigger 14 is set to the zero state (Fig. 2i), and on the falling front the fourth trigger 15 changes its state from one to Nya Ullevi fig.2k {l).

Thus, at the output of the device, a pulse is formed, the delay time and the duration of which are determined by the information preliminarily recorded in counter 11 and register 1, respectively.

After the fourth trigger 15 transitions from a single state to a zero (fig. 2k, l), the fifth trigger 16 is set to a single state. The logical zero level of the inverse output of the first trigger 16 (fig.2n) through the first element Ib acts on the first trigger 9, transferring it from one state to zero (figd, e), and through the second element 10 to the second trigger 7, confirming its zero state.

After the first trigger 9 is set to the zero state (Fig. 2e, e), the third AND-HE element 8 is activated, and the fifth trigger 16 is transferred to the zero state (Fig. 2n).

The programmable delay device, the pulses, is brought back to the original 1 state. The output of the pulse is processed by the central control unit and after its completion records information to the counter 11 and register 13, setting new or repeating old values of the delay value and the duration of the output pulse relative to the input.

Introducing the register and the AND-OR element into the device allows one to obtain an output pulse of any predetermined duration. In this case, the accuracy of the beginning of the reference time of the input pulse delay is twice the output than in the known device, and is equal to the time equal to the half period of the generator pulse sequence.

Claims (3)

1. Authors certificate of the USSR 396822, cl. H 03 K 5/135, 08.23.71. 2. USSR author's certificate  573865, class H 03 K 5/153, 04/26/76. 3. Electronics. 1969, 4, p. 74-75 (prototype). HZ  nttlfn p p m ;; i p p dbixoff oh generator o & ymd B inverter j o