SU860042A1 - Signal sunchronization device - Google Patents

Description

one

The invention relates to computing and can be used in redundant discrete devices for synchronizing pulse distributors.

A device for synchronizing signals is known, which contains an output cg, a trigger, three installation cues for recording pulses on the input and additional triggers, an input key, two elements, and the second input of the output c. Is connected to a clock source, the zero inputs of the additional trigger are connected to the output bus and the input of the first installation socket, one input of which is connected through the element NOT to the source of synchronized pulses, and the other input to the source of clock pulses ti1.

A disadvantage of this device is its complexity, due to the presence of input and additional triggers, the three installation keys.

It is also known to have a reserved signal synchronization device containing in each channel triggers for recording, storing and issuing information, majority elements.

the AND and OR elements, the clock bus, the information input and the output, the single output of the output trigger and the clock signal bus are connected to the zero input of the recording trigger via the AND setting element, and the zero input of the trigger signal is connected to the clock signal bus. In addition, the main entrance of the majority

The 10th element of this channel is connected to the single input of the output trigger via the AND element, the additional output of the majority element, the input outputs of the recording triggers of other channels are connected to the inputs of which, the clock signal bus 2 is connected to the other input.

20 The disadvantage of this device is its hardware and functional complexity, due to the presence of three triggers, two of which are countable, four AND elements, two OR elements, a majority element with two outputs. In addition, the device has three input bus clock signals with time diagrams of operation. The closest to the proposed / technical entity is a device for synchronizing signals, containing in each channel a recording trigger, a storage trigger, a trigger for signals, a major element, elements I. And the clock pulses arrive at element I, the second input of which is connected to the trigger output storage, and the output of this element And is connected to the inputs of the majority elements of adjacent channels, the output of the majority element is connected to a single input of the trigger. The output of this trigger is connected to one input of the element I, to the second input of which received these pulses. The output of this element AND is the installation input into the recording and storage trigger and the output of the device 3. The disadvantages of this device are the complexity of the device, due to the need to synchronize information on the three clock inputs of the device, as well as asynchronous operation of the major elements through different inputs due to the presence of the AND scheme in the information receiving paths to the majority element from adjacent channels and lack such in the path of receiving information from its channel. The purpose of the invention is to simplify the device. This goal is achieved by the fact that a device for synchronizing signals, containing in each channel a major element and element AND, the output of which is connected to the course of a given channel, and the first input with a clock input of the device, contains in each channel a DV trigger, D whose input is connected to the information input of this device channel, V is the input to the device start input, and the synchronization input is connected to the device clock input, the major element inputs of each device channel are connected to the DV output of all channels of the device. roystva, and an output - to the second input element I. The drawing shows the proposed device Flowcharts. The device consists of three identical channels 1-3. Each channel contains an element 4, the output of which forms the output 5 of this channel of the device, the major element b, the DV trigger 7. The synchronization input C of the OV trigger 7 is connected to the cycles of input 8 of the device, the control V input is input 9 of the device’s start , and informational D-inlet - with the formational input 10 of this channel of the device. The first input is element 4 and 4 is connected to the clock input 8 of the device, the second is connected to the output of the major element b, one input of which is connected to the output of the DV flip-flop 7 of its channel and to the inputs of the majority elements of the adjacent channels, and the other OV -triggers 7 and the corresponding inputs of the majority elements of 6 adjacent channels. The device works as follows. The initial state of the DV flip-flop 7 of all channels is zero. At the outputs of the majority elements b, by virtue of this, there are zero signals and the element 4 of each channel is closed at the first input. The sequence of clock pulses from the clock input of the device does not pass to the outputs of the 5 channels of the device. After a signal is applied to the start input 9, the device 0 / -triggers 7 are prepared to change their state. Prior to the arrival of the signal from the information input 10 channel to the D input DV trigger 7, its state will not be changed. When a signal arrives at input 10 and when a clock pulse appears at the C-input DV-TpHrrepa 7, the DV trigger 7 is set to one state. The switching of the DV flip-flop 7 takes place at the falling edge of the pulse arriving at the C input. Since the appearance of the switching signal to unit pv-flip-flop 7 (unit level at input 10) in different channels can occur at different times, the switching of DV-flip-flop 7 in different channels can also occur at different points in time, but different target numbers periods of clock pulses. After switching on at least two DV-flip-flops 7, the major elements b are triggered, and the unit levels of the signals received at the first inputs of the AND 4 elements enable them to trigger, and the next clock pulses from the clock input 8 arrive through the elements AND 4 at the outputs 5 of the device synchronously all three channels. Since the switching of DV-flip-flops 7 takes place on the falling edge of the pulses at the C-input, the switching process of the DV-flip-flop 7 And the major element 6 occurs in the pause between adjacent clock pulses, which eliminates the appearance of defective units (fragments) at the outputs 5 pulses. After the DV flip-flop 7 is switched to one state, the device start-up input 9 sets the signal to zero, prohibiting the DV flip-flop switching 7. After that, the signal level at input 10 is indifferent. Synchronous shutdown of the clock sequence from the outputs of the device 5 is performed by sending signals of a single level

to the input 9 of the device start-up and the zero level to the inputs 10 of the device. In this case, the O-flip-flop 7 of each channel is set in the same way as the DV-triggers 7 described earlier in the one state. The delivery of clock pulses from the input 8 through the elements AND 4 to the outputs 5 of the device will stop only after turning off at least two of the three 0 / -triggers 7, which will cause the switching off of the majority elements 6 and suppress the operation of the elements 4.

The simplification of the device lies in the fact that instead of three clock sources, it uses only one clock source.

The proposed device makes it possible to use it as a channel frequency synchronizer, which is important when the master oscillators are initially turned on, and with pulse trigger signals on input 10, input 9 serves for a latch. It can be used for synchronous start of a digital computer.

Claims (3)

1. Author's certificate of the USSR W 457176, cl. H 03 K 5/13, 1973. 2. Authors certificate of the USSR, 520593, cl. G 06 F 11/00, 1974. 3.ABTopcKde certificate of the USSR No. 378830, cl. G 06 F 1/04, 1971 (prototype). JO) (