SU813768A1 - Selector of pulse trains by duration - Google Patents

Description

The invention relates to a pulse technique. A pulse selector selector containing a trigger is known, one input of which is connected to the output of the pulse shaper, and the other input through a delay element to the output of the pulse generator and the first input of the shift register, the second and third inputs of which are connected to the output of the trigger. The disadvantage of this device is limited the repetition frequency of selectable pulse stoves is permissible, due to the long zero reset of the shift register after the end of the previous burst of pulses, and the noise tolerance is not high enough ness. The closest in technical essence is the pulse train selector in duration, which contains an RS flip-flop, S is the input of which is connected to the summing input of the pulse counter and the device input, and R is the input with the reset input of the pulse counter and the output of the first element delay, the input of which is connected to one of the inputs of the decoder, the other inputs of which are connected to the outputs of the pulse counter, and the output connected to the output of the device, a three-channel selector of the maximum pulse duration, consisting of three elements erzhki, GI-OR element and pulse shaper whose output is connected to the input of the first element zescherzhki and its input connected to the output of the GI-OR element. The first input of the first element AND, which enters into the composition of the element ZI-OR, is connected through the second delay element to the output of the RS flip-flop, and the second input of the first element AND is connected to the first input of the second element AND, the first inputs of the second and third elements And - directly, and the second inputs through the delay elements connected to the outputs of the pulse counter 2. However, this device is characterized by a limited allowable repetition rate of the selectable series of pulses, due to the large initialization time of the device, as well as the relative complexity of the device, due to the use of a maximum duration of 3 adjustable delay elements in the selector.

The purpose of the invention is to expand the frequency range of the selected pulse series and simplify.

The goal is achieved by the fact that the device containing a pulse counter, the summing input of which is connected to the input bus and the 5th input of the RS flip-flop, the reset input | With the output of the first delay element, and the direct outputs through the decoder with the output bus, the pulse selector of maximum duration consisting of the second and third delay elements, pulse generator and element 2И-OR, the first input of which is. r; o directly, and the second input through the second delay element is connected to the direct output of the K-th digit of the pulse counter, the third input is connected to the inverse output of the K-th bit of the pulse counter, the fourth input –C output of the third delay element and the output through the pulse shaper with the input of the first delay element and the corresponding input of the decoder, an element I is entered, the first input of which is connected to the third input of element 2И-OR, the output - to the input of the third delay element, and the second input - with the output of the RS flip-flop, R input o is connected to the input of the first delay element.

The drawing shows a structural electrical circuit of the device.

The pulse train selector contains RS-flip-flop 1, a counter 2 pulses, a selector 3 of maximum duration two-channel delay elements 4-6, element 2IIII 7, shaper 8 pulses “decoder 9, element 10, S-input trigger 1 is connected to the input bus and CO input counter 2, the reset input of which is connected to the output of the delay element 4. The input of the delay element 4 is connected to the output of the imaging unit 8, the ft input of the RS flip-flop 1 and to one input of the decoder 9, the other inputs of which are connected to the outputs of the counter 2. Pr my trigger output 1 connect inn with the first input element And 10, the second input of which is connected to the inverse output of the R-bit: counter 2 and to the first input of the first element AND, which is part of the element 2И-OR 7, the second input of which is connected to the output through the delay element 5 element 10. Forward output: the discharge of counter 2 is connected to the first input of the second AND element included in element 2I-OR 7 directly, and to the second input through the delay element 6.

The device works as follows.

In the initial state, the trigger 1 and the counter 2 are in the zero state. Element AND 10 is closed at the first input by the inhibitory (low) potential of the direct output of the trigger 1 The first element AND, which is part of the element 2I-OR 7, is opened at the first input by the resolving (high) potential of the inverse output of the Kth digit of the counter 2 and closed at the second input by the low output potential of the delay element 5. The second element AND, which is part of element 2ILI 7, is closed at both inputs. The first pulse arriving at the input bus throws trigger 1 into one state, fixing the beginning of the stack. The number of pulses in the stack counts the counter 2. A high potential for the output of the trigger 1 is fed to the first input of the element 10, opened at the second input by the high potential of the inverse output of the kth discharge of the counter 2. the element 10 opens and the high potential from its output goes to the input delay element 5 to the first input of the selector 3 maximum duration. The signal from the output of the delay element 5 is fed to the second input of the element AND of the element 2I-OR 7, the first input of which receives the signal from the inverse output of the K-th discharge of counter 2. This ensures the detection of a break in the initial part of the burst before the first actuation of K- counter 2 counter. When the duration of the series, the pulses are equal to or greater than

 , - each input pulse, whose number is a multiple of 2, causes the switching of the K-th digit of counter 2. The pulses from the inverse and direct outputs of the K-th digit of counter 2 alternately feed to the second and third inputs of the selector 3 of maximum duration. With this impulses

From the direct output of the K-th discharge of counter 2 is fed to the delay element b and the first input of the second element AND element 2I-OR 7, and the pulses from the inverse output of the K-th discharge of counter 2 arrive at the first input of the first element And element 2I- OR 7, and through the element AND 10, at the first input of which the resolving potential is fed from the single output of trigger 1, to the delay element 5. In the absence of bits in the stack of pulse duration from the K-th discharge outputs of the 21G counter T, where T is the period pulse repetition in a pack. When discontinuities appear in a burst, the pulse duration from the K-th discharge outputs of counter 2 is increased by the duration of discontinuities Trdyr Ill,

m p "p rc setting selector

Claims (2)

1. USSR author's certificate number 573868, cl. H 03 K 5/18, 1977. 2. Authors certificate of the USSR 598229, cl. H 03 K 5/20, 1978.