SU798959A1 - Information displaying device - Google Patents

Description

one

The invention relates to devices for analyzing and displaying multiple repetitive fast processes used in various physical experiments, associated with the short duration of the information under investigation and characterized by a large amount of information recorded.

A device for displaying information containing two memory blocks, a delay unit to the input of which a recorded signal is fed, a driver of triggering signals, a signal from which is simultaneously fed to the first memory block, a temporal calibration block of the recorded process, a control unit and a process indication unit flj .

However, the known device does not allow to register a large number of single signals with a random distribution of amplitudes.

It is also known a device for displaying information comprising three memory blocks, the first of which is connected to the input signal buses, a control unit, an indicator and a phase discriminator associated with the control unit and a second memory unit that is connected to the unit

analysis connected to the control unit and the third memory block, which is connected with. control unit and indicator 2.

However, the known device does not allow to register a large number of single signals with a random distribution of amplitudes.

The purpose of the invention is to increase

0 device speed.

The goal is achieved by the fact that in a known device for displaying information, comparison schemes, a buffer register, a sum 5 torus, a code-voltage converter and an analog-to-digital converter connected to the control unit are entered, and an analog-to-digital converter is connected to the input signal buses,

0 by the first memory block, an adder connected to the buffer register, and a comparison circuit that is connected to the buffer register connected via a code-converter converter to the first memory block,

The drawing schematically shows a diagram of the proposed device for displaying information.

In this device, the bus 1 input signal. Connected to the first unit 2.

0

a memory which is connected to the control unit 3, the indicator 4 and the phase discriminator 5. The control unit 3 is connected to the second memory block b, the analysis block 7 and the third memory block 8. The phase discriminator 5 is connected in series to the second memory block b, block 7 analysis

the third memory block 8 and the indicator 4. An analog-to-digital converter 9 is connected to the input signal bus 1, connected to the adder 10 and the comparison circuit 11. The adder 10 is connected to the buffer register 12 connected to the code-voltage converter 13 and the comparison circuit 11. Next, the first memory block 2 is connected A / D converter 9, to comparison circuit 11 and code-voltage converter 13, the control unit is connected to analog-to-digital converter 9, accumulator 10, comparison circuit 11 and buffer register 12.

; The first memory block 2 contains a storage electron tube (ZELT) 14 connected to the read scan unit 15, the read backlight unit 16 (4i, switched power source 17, the write sweep unit 18, the write backlight unit 19, the delay unit 20, the signal grid 21 connected to a read amplifier 22.

The operation of the information display device is as follows.

At the beginning, the screen of the storage electron storage tube 14 is prepared for recording. For this, the control unit 3 commands the readout scanner 15 and the read illumination unit.

The switched power source 17 is shifted to the position corresponding to the preparation mode of the ZELT 14. At the same time, on the screen of the ZELT 14 a rectangular raster of the television type is displayed. Then, the control unit 3 switches the switched power source 17 to the recording mode, records the source code to the adder 10 and the buffer register 12. This code, generated by the voltage converter 13, gives the initial level of the write beam on the ZELT 14 target.

After that, the circuit is in standby mode,

The first test signal arriving at the system input comes from bus 1 to analog-to-digital converter 9, which converts the r1 amplitude of the signal into a digital code which goes to comparison circuit 11, where it is compared with the code / recorded in buffer register 12. If it turns out that the code received from analog-digital converter 9 is less than or equal to:

the code coming from the buffer register 12, then the comparison circuit 11 generates a trigger signal, which is fed to the trigger inputs of blocks 18 and 19 of the sweep and recording light, and also to one of the inputs of the control unit 3. This signal starts blocks 18 to 19, with On the ZELT 14 screen, this records the signal of the process under study, which enters the input of the ZELT 14 through the delay block 20, simultaneously with the code comparison process on the comparison circuit 11, the adder block 10 is supplied with a digital code from the analog-digital converter 9, where s incoming code from an initial recording beam level code. The resulting subtraction code is written into the buffer register 12 for comparison with the amplitude code of the next signal under study.

The control unit 3, using the signal received from the comparison circuit 11, generates a signal to control the voltage-code converter 13, to shift the recording beam, with a delay of the recording time, to a new position on the ZELT 14 target corresponding to the code written in buffer register 12 and simultaneous preparation of the device for the registration of the next process.

The registration of the next investigated signals is performed in a similar way with the subsequent transfer of the recording beam to a new target zone. Registration stops if the code from analog-to-digital converter 9 turns out to be greater than the code recorded in buffer register 12, which means that the signal received will not be recorded in the remaining working area of the target.

In this case, the comparison circuit 11 generates a write end signal according to which the control unit 3 puts the device into read mode.

Next, the readout process starts with the supply by the voltage unit 3 to the switched power source 17, which puts it into the readout mode. Then, from block 3, an erase and write command is sent to the second memory block b, after which the memory block b is ready for recording and is in standby mode.

The control unit 3 starts blocks 15 and 16. On the signal grid 21, read and transformed signals appear in the form of small amplitude pulses, the phase of which carries information about the amplitudes of discrete samples recorded on the ZELT screen of 14 signals. These pulses are fed to the input of the amplifier 22, from the output of which the generated signals are fed to the information input of the digital phase discriminator 5, the second input of which receives the pulses of the reference signal from the control unit 3.

The reference pulses set the origin of the phase shift of the information pulses. The digital phase discriminator 5 measures the phase shifts of information pulses by the method of sequential counting and outputs to the information input of the second memory block 6 a parallel binary code characterizing each discrete sampling of the amplitudes of the registered signals.

After the completion of the reading process of the first information array registered on the ZELT 14 screen, the ZELT 14 is switched to the preparation mode for recording the next information array.

The cyclical process of recording signals on the screen of the ZELT 14 and reading from it into the second memory block 6 ends after registration of the stream under study of one-off fast processes.

At the same time, in the second memory block 6, information is accumulated in the form of a series of binary numbers, which are digital equivalents of discrete samples of all registered single signals of the stream under study. At the end of the registration process, the system is put into analysis and playback mode. For this, the control unit 3 commands the transfer of the second memory unit 6 to the read mode. Reading the information together with the synchronization signals from the control unit 3 is fed to the input of analysis unit 7, which sequentially retrieves information, transforms it, analyzes it and generates information about the ordinates of the amplitude distribution of the stream of one-off fast processes. The process of displaying the registered information involves the operation of the device in two modes, i.e. the mode of indication of any of the registered single processes and the mode of indication of the amplitude distribution of the stream of single fast processes.

In the observation mode (indication) of the form according to the program specified by block 3, analysis block 7 selects information from any of the registered one-time fast processes from the second memory block 6, converts and writes to the third memory block 8. Upon completion of recording in the third memory block 8, the device is switched to the playback mode by a command from the control unit 3.

In the indication mode of the amplitude distribution, the information coming from the analysis unit 7 is recorded in the same way in the third memory block and is displayed in the playback mode on the screen of the display unit 4.

When playing on display unit 4, an image of the form of the amplitude distribution | of the studied flow of one-off fast processes (or the form of any of the registered one-time processes) appears.

Thus, the proposed system allows registering streams of one-time fast processes with a random distribution of amplitudes, which allows to significantly increase the information throughput and expand the scope of application of the proposed system. Moreover, the introduction of new nodes and connections allows to increase the speed of the device due to more complete use of the capacity of the first memory block.

Claims (2)

1. Authors certificate of the USSR 368557, cl. G 01 R 23/10, 1970. 2. USSR author's certificate 0 No. 512481, cl. G 06 K 15/18, 1974 (prototype).