SU542192A2 - Automatic Time Programmer - Google Patents

Description

vetstvenno. Recording information about subsequent time intervals is similar. At the end of the log, information about the time intervals using the controls of block 12 at the input of the comparison block 15 is set information about the number of subcycles, and at the input of the comparison block 16 - information about the number of complete cycles. In addition, information about the number of output signals in the sub-cycle is supplied to the installation input of the time interval counter 7, additional counters 13 and 14 are reset.

The processing of the specified time intervals begins on the Start command issued by block 12 to the first control input of the pulse generator 11 and to the counter, which goes from zero to first state. In this case, the signal from the output of the counter 7 arrives at the control inputs of the output keys b of the first time interval and opens them. The time registers 4 and the clock units 5 of the first time interval are connected respectively to the coincidence circuit 8 and to the controlled frequency divider 9. The division ratio of the controlled divider becomes equal to the number corresponding to the code recorded in device 5. The frequency received by the frequency divider 9 fills the counter 10 until the code issued by the counter 10 coincides with the code recorded in the corresponding time register 4, after which the circuit 8 outputs a pulse signal to the counter 7. The output keys 6 of the first the time interval is closed, and a signal from the output of the counting 7 opens the output keys 6 of the second time interval. The pulse signal of coincidence circuit 8 resets the counter 10 to zero. Then the clock pulses with the corresponding new repetition period begin to fill in the counter 10.

The remaining time intervals are processed similarly until the time when the switchings coincide with u {scrapping characterizing the length of the trigger by the specified block 12.

After the match, the transition to the processing of the first time interval irrespective of the total number of implemented intervals in the device, i.e. subcycle repeats. When the number of processed subcycles, which is fixed by the counter of sub cycles, becomes equal to 1; 1 and the number of sub cycles specified by block 12, comparison block 15 forms a pulse

the signal arriving at the control input of the counter 7, and allowing the testing of the last, previously unworkable time interval. After testing this time interval, one full cycle of operation is completed and, by the signal of the coincidence circuit 8, entering the counter 7, the counter 13 is reset to zero and the first unit is recorded in the counter 14.

The described work cycle is repeated until

until the code at the output of the counter 14 coincides with the code of the block 12 being inserted. After the match, the block 16 compares a pulse signal to the second control input of the pulse generator 11 and turns it off.

Use the proposed automatic

the programmer of the time intervals allows the OS to achieve long-term multi-cycle tests of various electronic devices, both climatic and difficult to operate.

u {klogramma work.

Claims (1)

1. USSR author's certificate, N1443386, M. class. G06F9 / 00, G 05 B19 / 18 from 1973