SU541175A1 - Device to control binary codes mod three - Google Patents

Description

one

The invention relates to the field of automation and computer technology and is intended to control binary codes.

A device for controlling binary codes by an odd module, containing a counter, a ring register and logic elements, is known. The monitored code can be fed to the device only sequentially by bits, and the need to use a ring register, a trigger and logic elements complicates the device.

The prototype of the invention is a device for monitoring binary codes modulo three, containing a counter modulo three, the inputs of which bits are connected to the outputs of the elements And, as well as a counting trigger. The speed of the device (the number of cycles of its operation) is proportional to the size of the code being converted.

The invention is a simplification of the device for controlling binary codes modulo three and improving its speed.

This is achieved by the fact that a device PI is entered into the device, the inputs of which are connected to the odd and even bits of the code being monitored, the output of the AND-NO element to the inputs of the first and second AND elements, the other inputs of which are connected to buses of odd and even Dov controlled code, respectively.

Diagram of the device shown in the drawing.

The device contains 1 for supplying odd and even bits of the monitored code at the same time, the AND-NOT 2 element, the AND 3 elements, the counter 4 modulo three, performed on the OR 5 elements, the triggers 6, the AND 7 element and the delay element 8. The device works as follows.

The values of the adjacent even and odd bits of the monitored code are given over the tires 1. The unit values of the odd bit (at the zero value of the adjacent even bit) correspond to the residual

"01, and the unit values of the even bit (at the zero value of the adjacent odd bit), corresponding to the remainder of the" 10, pass to the inputs of the counter 4 through the open elements AND 3, since the output of the AND-NE element 2 in these cases is a single signal.

The appearance of single signals at the same time on both women 1 corresponds to the remainder “00, while the output of the element IS NOT

2, a zero signal appears that blocks the AND 3 elements, thereby blocking the inputs of counter 4 from recording signals that distort the correct control result. Signals corresponding to residues "01

and "10, are fed to the inputs of the bits (flip-flops 6) of the counter 4 and recalculated therein. If the code “11” is generated in the counter, then the element AND 7 is opened, the single signal of which through the delay element 8 and the elements OR 5 sets the counter 4 to the state “00. The delay time of the signal on the element 8 must not be less than the duration of the pulses coming through And 3 elements.

As a result, in the counter 4 a number is formed equal to the remainder of dividing the monitored binary code by module three.

Since the proposed device analyzes the values of two bits of a code at the same time, it has twice as much speed as compared with the known devices of the same purpose at a lower cost of co-monitoring equipment.

Claims (1)

Invention Formula A device for monitoring binary codes modulo three, containing; its counter modulo three, the inputs of the first and second bits of which are connected to the outputs of the first and second elements AND, respectively, characterized in that, in order to simplify the device and increase its speed, it contains the element AND-NOT, the inputs of which are connected to the odd-numbered and even-digit bits of the monitored code, the output of the II-ILE element is connected to the inputs of the first to the second AND elements, the other inputs of which are connected to the odd-even-even buses This code, respectively. R