SU547718A1 - Electronic clock with automatically adjusted time scale - Google Patents

Description

(54) ELECTRONIC CLOCKS WITH AUTOMATICALLY CORRECTABLE

SCALE TIME

whole seconds to the required values (minutes, hours), indication and generation of autonomous time pulses at the intermediate output (for example, 1 Hz and 2 Gd) for operation of block 4 and 5, which are fed to one of the outputs of the corresponding blocks.

The second input of block 4 also receives seconds pulses of the exact time from the output of receiver 3, which extracts from the entire sequence of pulses arriving at its input, a pulse identifying doing a second, MKnyiy, or an hour (for example, a receiver separating the leading edge the sixth signal of the exact time corresponding to the whole hour).

The output time pulses (ms, ms, sec, min, hour,) generated by an autonomous clock must be out of phase to the signals of a single time (exact time). For this, the clock provides for the possibility of shifting all pulses of the channel dividing the frequency of fractions of a second in phase by a predetermined amount.

The magnitude of the phase error of the coupling of the pulses of an autonomous time relative to the leading edge of the received signals of a single time is determined in block 4.

As block 4, for example, an automatic phase control system can be used, in which the magnitude and sign of the phase mismatch is determined using a phase discriminator by automatically counting high frequency pulses of the oscillator 1 and converting the number of pulses into a code (for example, binary dec This is followed by the issuance of this code, which corresponds to the magnitude and sign of the phase mismatch between oscillations of the generator 1 and received from the channel of pulses of the exact time, to the encoder 5.

The delay, which is present in the received time pulses due to radio wave propagation and hardware delay, is determined in advance by calculation or experimentally and is also entered into the encoder 5, as a correction factor, for the necessary pre-second correction for working on the Advance command.

The autonomous time signals are shifted in phase by a forward or delay correction input device using the encoder 5 without directly affecting generator 1. This is achieved due to the fact that the encoder 5 converts the binary decimal information about the magnitude and error sign of the autonomous and single time coming from block 4, to the binary code identifying this mismatch. As the encryption elements can be used logic circuits, OR, AND, switches and transistors.

The code formed at the output of the encoder 5 in the form of 1 and O affects the setting inputs of the frequency divider of the shares of block 2,

Installing the binary counters of this divider to the required state and thereby changing the phase offset of the output pulse (for example, 1 Hz or 2 Hz) generated by block 2. With this method of correction, both the binary splitter counters are necessary and the state of the binary counters is checked 2, thereby eliminating the accumulation error in this block, and the correction step has a variable value corresponding to the input correction second.

Creation of a command The delay is performed by block 4 with a delay determined by the correction factor of the necessary second-rate correction to test the command Advance entered in the encoder 5, which eliminates the response of the automatic control system to the amendment.

To eliminate ambiguity within a second, receiver 3 extracts, for example, a minute pulse of exact time and phases the frequency dividers of fractions of seconds and seconds by setting them to zero, which ensures that during the initial installation, the autonomous clock is locked within 0.5 seconds.

After that, on the leading edge of the nearest second pulse of the exact time allocated by the receiver 3 (for example, corresponding to the whole hour), the magnitude and 3iiaK of the error occurring during the time elapsed between two sessions of the correction of block 2 are determined by known methods in Block 4. This value will characterize the hardware error in the impulse squeezing that occurs during long-term operation of the electronic clock due to the frequency instability of the generator 1.

So, for example, if, during a correction session, block 4 shows that the autonomous clock pulses are some time behind the exact time pulses, then it will form a command along the Alert circuit that determines the mismatch sign and code, identifying the mismatch value enters the encoder 5.

The indicated value and the error sign are stored in the RAM of unit 4 for the duration of one correction session. For example, discrete elements of a device converting a number-pulse code into a binary-decimal can be used as a memory.

After that, the leading edge of the nearest, for example, second pulse coming from block 2 to the correcting input of the tweeter 5, corrects the frequency dividers of the unit 2 by the said method via the output output of the encoder 5.

As a result of the introduced second correction, block 2 forms the front edge after correction that has been made, for example, the second output pulse tied to

a single time scale, taking into account automatically entered corrections and eliminated in the process of correcting the mismatch due to the instability of the generator 1.

In the case of the introduction of a delayed correction, block 4 forms a command on the circuit. Delay in the form of an additional pulse on the counter for whole seconds, and on the chain in Advance - the value of this delay in the form of an addition up to a full second. In the future, the algorithm for testing the introduced amendment is similar.

Claims (2)

1. US patent number 3855785, cl. 58-23 dated 1/9/70 2. Authors certificate of the USSR No. 356624, M.C. G04F5 / 00 dated 03.11.1972 (prototype). fts sa