SU534032A1 - Converter of parameters of two-element non-resonant electrical circuits into unified signals - Google Patents

Description

The rator is connected to the analog input of a discretely controlled divider, the first input of the logic circuit is connected via an amplifier to the output of the differentiator, the second to the output of the clock generator, the third to the output of the differential amplifier-limiter, and the outputs of the logic circuit are connected to the summing and output reading reverse buses counter.

FIG. 1 shows the flow chart of the proposed converter; in fig. 2 - Temporary stress diagrams at characteristic points of the circuit.

The converter contains a DC amplifier 1, a measured circuit 2, a reference element 3, an analog adder 4, a discretely controlled divider 5, a reversible counter

6.differential limiting amplifier

7, the integrator 8, the differentiator 9, the amplifier 10, the clock pulse generator 11 and the logic circuit 12, while the output of the DC amplifier 1, in the negative feedback circuit of which the supporting element 3 is connected, is connected to one input of the analog adder 4, the second the input of which is connected to the divider 5, the control inputs of the latter are connected to the outputs of the counter 6, and the analog input to the output of the integrator 8 and to one input of the amplifier-limiter; the output of the adder 4 is connected simultaneously through the differentiator 9 to the input of the amplifier 10 and to the second input of the amplifier 7, the output of which is connected via the measured circuit 2 to the input of the amplifier 1 and to the input of the integrator 8; the output of the amplifier 10, the generator 11 and the amplifier-limiter 7 are connected to the corresponding inputs of the circuit 12, two outputs of which are connected to the summing and subtracting tires of the reversing counter 6.

The operation of the converter is described on the example of the parameter transformation of a parallel RC circuit; as a supporting element in this case, a capacitor with a capacitance Co is included in the negative feedback UF1 circuit.

When the converter is turned on, the differential limiting amplifier 7, due to the large value of the gain, is in a saturated state and the voltage is removed from its output.

integrator 8, the voltage is removed -

and

(where Tn is the size of the integrator time constant 8;; / is the current time). This voltage is fed to the inverting input of the amplifier limiter 7 and to the input of the divider 5, the output voltage of which has the form -

and

(where Лг - divider transfer coefficient 5). At the same time, the voltage from the output of the amplifier-limiter 7 through the measured circuit 2 is fed to the input of the amplifier 1, covered by a parallel capacitive negative feedback through the supporting element 3; at VOIPT1, the voltage changes over time to the following law

With t

.

0)

CDRCy

where C and R are the dimensions of the capacitance and the resistance of the measured circuit 2;

Co is the size of the capacitance of the support element 3.

The voltage from the output of the amplifier 1 is fed to one input of the adder 4, the second input of which receives the voltage from the output of the divider 5. From the output of the adder 4, the voltage is removed

-RA- + o- + o-, (2)

It-OAOo

which enters the non-inverting input of the amplifier-limiter 7 and keeps it in a saturated state.

At the moment of changing the sign of the voltage difference at the inputs of the amplifier-limiter 7, the voltage at its voltage jumps to the value of - EO (changes sign) due to deep positive feedback through the circuit: output

limiting amplifier 7, measurable circuit 2, amplifier 1, adder 4, non-inverting input of limiting amplifier 7, and the process described above is repeated.

The period of the limiting amplifier generated at the output of 7 rectangular pulses can be determined by equalizing to zero the voltage difference at the inputs of the limiting amplifier 7.

l- ° (3)

t

 one

one

I-i

 RC

The pulses from the output of the amplifier limiter 40 7 are fed to the input of the integrator 8 and through measured circuit 2 to the input of the amplifier 1. The voltage at the output of the integrator 8:

(four)

IL

The voltage at the output of amplifier 1 in each half-cycle of the input signal is the sum of the constant component determined by the value of the measured capacitance C and the linearly variable component determined by the value of the measured resistance R:

U, (t)

(five)

i.

RCo

The voltage U. (t) is applied to the analog input of the divider 5, from the output of which, in the i clock cycle, the voltage is removed from the generator 11

ULO-T /.

(6)

Voltage / FVA is applied to one of the inputs of the adder 4, to the other input of which 65 is in antiphase with a linearly varying component defined by the value of the measured resistance R, sawtooth voltage f / sfO C output of the divider 5, the slope of which changes Each period of the clock pulses from the output of the generator 11. Thus, the voltage at the output of the adder 4 (with equal transmission ratios at its inputs) during the t clock cycle of the clock pulses of the generator 11 is determined by the expression and (() - г -т- / 0 - f, RC,. „) Voltage Ui (t ) is applied simultaneously to one input of the amplifier-limiter 7 and to the input of the differentiator 9. From the output of the differentiator 9, when operating in the linear mode, the voltage U is removed, (t): 1. ,, (8) оС - и, (t ± where-td is the constant of differentiator time 9.- 1 The first term of the expression (8) is the result of the effect on the input of differential voltage differentiator 9. Voltage t / 5 (O the output of the differentiator 9 is fed to the input of the amplifier 10, from which the signal is taken - d Ip U, (bo 1.1 g g ± V-1 where k is the gain of the amplifier 10. The voltage t / efQ from the output of the amplifier 10, clock pulses from the output of the generator 11 and the voltage ± Eo from the output of the amplifier-limiter 7 is fed to the corresponding inputs of the circuit 12, the output signal of which, depending on the polarity of the pulses arriving at its input appears on the summing, then on the subtractive steps of the counter 6. The voltage pulses taken from the output of the circuit 12 change the state of the counter 6, and consequently, the state of the divider 5 thus that the voltage at the output of the adder 4 becomes almost constant during each half-period of the rectangular impulses generated at the output of the limiting amplifier 7, i.e., if the condition i - P o - kg is met, the output of the adder 4 has only alternating sign rectangular voltage odds s, the amplitude of which is proportional to the capacitance C measured by chain 2, thus, the output of limiting amplifier 7 - alternating voltage of rectangular shape. the period of which is unambiguously determined by the value of the measured capacitance C: D 4 - tn. The number of pulses fixed at that moment in counter 6 is uniquely determined by the value of the measured solids R: The operation of the converter in the case of converting parameters of consecutive RC and 1-circuits and parallel RL-K & nvi is similar. When converting the parameters of a serial U C-circuit, the latter is included in the negative feedback circuit of amplifier 1, whose input is connected to a reference resistor with resistance Ro- The number of pulses recorded in this iB. Counter 6 is proportional to the measured capacitance: limiting amplifier 7 is proportional to the value of the measured resistance: T R. When converting the parameters of the parallel / L-circuit, the latter is connected to the input of amplifier 1, the negative feedback circuit of which includes The TC resistor with an OK code, fixed in counter 6, is proportional to the measured inductance: NI 4-V and the pulse period at the output of limiting amplifier 7 is proportional to the value of the measured resistance: - l. negative feedback of amplifier 1, to the input of which a reference inductance is connected with an inductance value. With this switch-on, the code recorded in counter 6 is proportional to the value of the measured sop otivleni: LA and the period of output pulses is proportional to the limiting amplifier 7, the measured value of the inductance: T.

Claims (2)

1.Avt. St. USSR №382232, cl. NOZK 13/20, 04.02.72. 2. Forward number 2077696 / 26-21, 25.11.74. П П О П f П П n n f П П П О П П //  P P P P P P P P P Vmd (-) 6 P P P P P P