SU529565A1 - Cycle sync device - Google Patents

Description

the control unit, while the output of the clock divider is connected to the inputs of the switching node, and through the node of the control control unit formation, the switching unit8 analyzing the sync group of the first type, the third OR element to the corresponding inputs of the control signaling unit, the decision unit and the receiving distributor phasing unit the second output of the switching node is connected via an analyzing sync group of the second type, connected to the control signal generating unit, and the first OR element to the second inputs of the nodes and the control node and decisive. Thus, the detection time of the third signal, transmitted as a sequence of alternating sync groups of TWO species, is reduced, since it carries out an interdependent search for these synchrograms. In the drawing, the structural electrical circuit of the device is given. The cycle synchronization device contains a sync group decoder 1, one output of which is connected via the analyzing node 2 of the first type sync group to the input of the first element OR 3, and through the second element OR 4, the control node 3 - to the input of deSHGtel 6 clock frequency, the second output of the decoder 1 is connected to the second input of the second element OR 4 and to the input of the analyzing node 7 of the synchronization group BTOpoi o, the output of the divider 6 is connected to the inputs of the switching node 8, consisting of elements AND 9 and 10, and through the node generating 11 control signals, consisting th of delay elements 12, 13, elements OR 14 and 15, trigger 16 and Elements 17 and 18, switching node 8, analyzing node 2 to the corresponding input of the node form 11 and further through the third element IL 1 9 to the corresponding the inputs of the serially connected decision node 20 and the phasing node 21 of the receiving distributor. The second output of the formation unit 11 is connected via the switching node 8, the analyzing node 7 connected to the formation node 11. and the first element OR 3 is connected to the second input node of the control node 5 and node 20. Node formir The transmitter 11 is also connected directly to the decoder 1, the analyzing node 7 and the second input of the third element OR 19 The input of the decoder 1 and the output of the phasing unit 21 are the input and output of the device, respectively, the input 22 of the control unit 5 is the clock pulse input. In this way, the Pulse Code String from the input of the device enters the decoder 1, at the output of which signals are generated both on the sync groups and on the code groups of the information signal similar to the sync groups. The signals evicted by the decoder 1 are transmitted through the second element OR 4 to the input of the control unit 5 corresponding to the start of the divider 6. With a regular arrival of clock pulses from the input 22 through the control node 5 to the input of the divider 6, a sequence of pulses is formed at its output clock frequency and the next with a frequency of cycles. In the steady-state mode, the response on the first-type sync rotor from the output of the decoder 1 enters the input of the analyzing node 2 at the moment when testing input 8 arrives at its other input through the open element 9 of switching node 8 from divider 6. In this case, the repetition signal from the output of the analyzing node 2 through the third element OR 1 9 passes to the recording input of the state of synchronism in the decisive node 20 and to the input of the phasing node 21. In addition, the repetition signal from the output of the analyzing node 2 delayed by the delay element 12 of the formation unit 11, passes the element OR 14 and switches the trigger 16 to the position allowing in the next cycle the testing pulse from the divider 6 through the AND 10 element of the commutator unit 8 to the input, the analyzing node 7 and prohibiting through the AND 9 element to the input of the analyzing node 2. In the next cycle, as a result of the response of the decoder 1 output to the second VH sync circuit, the trigger 16 is switched to its initial position by a repetition signal from the output of the analyzing node 7 through the delay element 13 and the OR element 15, t. e. The device is being prepared for reception in the next sync cycle of the first type. In case of loss of synchronism by the device (absence of the expected response at the output of the decoder 1), an error signal is generated at the output of the analyzing node 2 or 7 prepared for testing, which through the first element OR 3 enters the reset input of the decision node 20 and the input of the control node 5, prohibiting receipt pulses of clock frequency to the input of divider 6, i.e. the divider stops at the position corresponding to the time of testing, and the items 17 and 18 remain open.

In the search engine, the first one: Ke of the responses to the sync group like pulse simulation and the information signal, which appeared at the output of the decoder 1, the dog stumbles on the corresponding analyzing node 2 or 7 and on the launch of the de- block 6.

This response passes the corresponding elements AND 17 or 18 and the RSHI element 14, or 15 of the formation unit 11 and sets the trigger 16 to the position that opens the AND 9 10 element of the switching node 8, which passes the signal from the divider 6 to that analyzing node 2 and 7j to the input of which came the response from the decoder 1.

The image of the lean repetition signal is appropriate; decrypted sync group, through the third OR or 1 9 is fed to the input of the record of the decision node 20,

Besides. .3. The sustained signal of repetition through the corresponding element OR 14 or 15 in the formation unit 11 transfers the trigger 16 to the state in which the device is ready to receive in the next sync group. py.

Fixing the state of synchronization with the decisive op:;,, 2 O from the phase 2 node. L, hochory: open to install the Bershms version; impulse is received for adjusting the reception area;

The formulas 5 of which are connected through the analyzing node of the synchro group of the first type to the input of the first element OR, to the input of the analyzing node of the synchro group of the second type, and through the second element OR, the control node -. To the input of the clock divider, as well as serially connected decisive node and the phasing node of the receiving distributor, characterized in that, in order to reduce the detection time of the synchronization group, a third OR element, a switching node, a control signal generating node, and a clock divider output are connected to the inputs of the switching node, and through the node of the control signals form, the node of the commutator, the analysis: the first node of the synchro group of the first type, the third OR element - to the corresponding inputs of the form node The control module, the decision node and the phasing node of the receiving distributor, the second output of the switching node is connected via an analyzing node of the second type sync group, connected to the control signal generating node, and the first OR element to the second inputs of the control node and the decision node.

Sources of information taken into account in the examination:

1. Gurevich V.E. and others. Pulse-code modulation in multichannel telephone communications. M., Svy, 1973, p.24O.

2. The patent of Germany No. 1142921, class 21a 49, 1963 (prototype).