SU528588A1 - Interpolator for Step Plotter - Google Patents

Description

block 12 comparison of codes and bus 18 interrogation block 6 valves, combined with one of the inputs of the logic element OR 13. The interpolator also contains a counter 19 basic segments, block 20 scale change and the decoder 21 service commands associated with the individual bits of the service Register 2. Registers 1 and 2 are designed to store and store information received from external devices through an interface and exchange unit (not shown in the drawing).

The information register code 1 sets one of the coordinates, coordinates of the nodal point and simultaneously with it the tangent of the angle of inclination of the drawn line. The pulse generator 9 generates a continuous series of pulses with a frequency equal to the maximum input frequency of the stepper drive. Summing counter 3 is designed to count the number of pulses coming from generator 9 and to form an overflow pulse at the moment when the mining of a line of base length is completed. The subtractive counter 4 is intended for the initial recording of the parallel code of one of the increments Al; or L (/, coming from the information register 1 through the valve block 6 to the installation inputs of the counter, and for subsequent subtraction of the pulses coming from the shift register 7 through the OR 13 gate and the delay line 14. Using the decoder 5, the "zero state" is selected subtractive counter 4. Shift register 7, together with logic element 13, delay line 14 and binary code converter 8, form a digital controlled frequency divider from the pulse generator 9. Counter 19 basic segments of presets assigned for counting the number of overflow pulses from summing counter 3 and corresponding to the number of "depleted base sections. Scale change block 20 is used to convert the conditional scale code of the drawn line from the small number of bits of the service register 2 to the binary parallel code of the true scale Switch 15 provides switching of pulse inputs of stepper motors of the plotter (not shown in the drawing). Switch 15 is controlled by a separate bit 22 of service register 2. Service command decoder 21 is designed to form "Reverse X," Reverse Y, coming in conjunction with pulse sequences at the input of the drive, and the "Lift, arriving at the executive drawing element.

In the initial state, all the interpolator nodes containing the memory elements are dropped by a signal coming over a separate bus "Reset (not shown), the AND 10 and 11 logic elements are in the closed state, on the request bar

a high potential level corresponding to the interpolator's readiness to receive information from an external device; the drawing element of the plotter is set to the initial point of the drawing. An external device (for example, a digital computer), analyzing the status of the bus Request, writes in registers 1 and 2 information on the coordinate increment of the first chain of the drawing and on the tangent of the angle of the drawn line segment and service information.

In the interpolator, an infinite set of possible displacement vectors is limited when drawing lines with a finite number of vectors so that the absolute error of the deviation of the drawn line from the calculated one caused by this restriction does not exceed the permissible error in the interpolation interval. The tangent code of the angle of the drawn line is specified by the code of the higher bits of the information register 1.

After recording the information in registers 1 and 2, the external device generates a "Start" signal, which enters the input of control unit 16, which, upon the expiration of this signal, opens the logic elements And 10 and I. A series of pulses begins to flow to the inputs of summing counter 3 and shift register 7. The parallel increment code of one of the coordinates is recorded through valve block 6 and subtractive counter 4 using a signal from the control unit 16 on the interrogation bus 18. At the same time, the parallel binary code of the higher bits of information register 1 is reconstructed using converter 8 into a unitary code, which is recorded by this signal via an OR 13 gate and delay line 14 into shift register 7. This sets the frequency of the pulses at the output of the digital controlled divider formed by the shift register 7, the OR element 13 and the delay line 14, in a closed circuit of which the logical unit from the output of the shift register 7 circulates through the OR element 13, delay line 14, polling the input of the binary code converter 8 to the unitary input to the installation input of a certain bit of the shift register 7. The output frequency from the output of the element 13 and the frequency of the pulse train coming from the output of the logic element 10 to the inputs of the switch 15 determine the slope of the drawn line segment.

The connection of two series of pulses to the required step motor is carried out by controlling the switch 15 using a separate bit 22 of the service register 2.

When the pulses of the summing counter 3 at its output 17, an overflow pulse appears, which enters the input of the counter 19 of the basic segments.

Claims (1)

According to the overflow signal of the summing counter 3, the control unit 16 sets the AND 10 logic element to the closed state, since the base coordinate along the X axis is already exhausted. Subsequently, the drawing element only moves along one Y coordinate, since the pulses continue to flow from the output of the shift register 7 through element 13 to the input of the switch 15. At the moment when the zero code appears in the subtractive counter 4, the output of the decoder 5 will generate a signal , coming to the input of the control block 16, which sets the AND gate to the closed state. Thereby, the interpolator is set by the control unit 16 to the initial state. When drawing lines parallel to one of the coordinate axes, only the line scale information is transmitted to the interpolator and along which of the coordinate axes movement should take place (bit 22 of the service register 2), and a zero code is sent to the information register 1. In this case, at the zero output of the converter 8 of the binary code to the unitary one, a high potential is obtained, which is fed to the control unit 16. In this case, the logic element 11 is closed, and there is no pulse sequence at the output of the shift register 7, and the maximum frequency pulses from the output of the logic element 10 are received at the input of the switch 15, which are fed to the input of the corresponding stepper motor using bit 22. the work of the interpolator is similar. Claims of the invention Interpolator for a shchagovy plotter containing an information register connected to serially connected valve block, subtractive counter and decoder, service register connected to the switch and through the scale circuit block to the comparison block clock generator connected via logic elements And to a summing counter and a shift register connected to a binary-to-unit converter, a correction unit connected to a summing counter, a decoder , AND gates and a block of gates, a delay line, and a logical element OR, differing in that, in order to simplify the device, it contains a counter of base segments connected to a summing counter and a comparison block connected to the control unit, the shift register output through a logic element OR is connected to a switch connected to one of the AND gates and through a delay line with a subtractive counter and with a binary to unitary converter, connected to the information register, and one of the inputs The logic element OR is connected to the control unit.