SU488344A1 - Reversible distributor - Google Patents

Description

one

This invention relates to the field of computing.

A lime reversing distributor, each bit of which contains four AND-NOT elements, a bus "to the left and a bus" to the right. Moreover, the output of the first element AND is NOT connected to the input of the second element AND is NOT its own discharge and with the input of the fourth element AND is NOT the previous discharge, the output of the second element AND is NOT connected To the inputs of the first and third elements AND is NOT its own discharge the output of the third element AND is NOT connected to the input of the second element AND is NOT its own discharge and to the input of the fourth element AND is NOT subsequent, its discharge, the bus “to the left is connected to the inputs of the first elements AND — NOT to all bits, the bus to the right with inputs of the third element | 3 AND - NOT all bits.

The purpose of the invention is to reduce the number of inverters and expand the logical capabilities of the distributor. For this, in the proposed distributor the output of the second element AND is NOT connected to the inputs of the second AND elements — NOT the previous and subsequent bits; the output of the fourth AND element is NOT connected to the inputs of the first and third AND elements — NOT its discharge; , the third and fourth elements AND - NOT the previous bit and

with the inputs of the first, second, and fourth elements AND — NOT the subsequent discharge, but the newly introduced bus “shift is connected to the inputs of the fourth elements AND — NOT all bits.

The drawing shows a diagram of the proposed reversing distributor with the number of bits equal to four (the number of bits can be any).

The distributor contains the elements AND - NOT 1 and 2, 3 and 4, 5 1 6, 7 1 8, which form the triggers, and the elements AND - NOT 9-12 and 13-16, respectively, of the first, second, third and fourth digits.

E, the initial moment of time, the trigger of the first bit is set to the state of "one, the other triggers are set to the state of" zero.

At the beginning of the shift to the right, the bus “to the left is given a signal equal to logical zero, and to the bus“ to the right - a signal equal to logical one. Since at the initial moment of time the clock signal is absent (equal to logical zero), then at the outputs of the elements AND- NOT 1, 9,3,4, 5, 6, 7, 8, 13, 14. 15, 16 there is a signal equal to the logical one , and at the outputs of the elements AND - NOT 2, 10, 11, 12 - a signal equal to logical zero.

With the arrival of a clock signal, an AND element is triggered, NOT 14, at its output by