SU1716522A1 - Device to control phase shift of two signals - Google Patents

Abstract

The invention relates to computing and can be used in the construction of instrumentation and to control the phase shift between two harmonic signals. A distinctive feature of the device is that it allows reducing the monitoring time by simultaneously measuring the period of the input signal in the counter 15 and the time of the phase shift in the counter. The aim of the invention is to reduce the monitoring time. The goal is achieved by introducing a comparator, switches, counters, an OR element. 4 il.

Description

The invention relates to computing and can be used in the construction of instrumentation for measuring the phase shift between two harmonic signals.

The aim of the invention is to reduce the monitoring time.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a comparison block diagram; in fig. 3 is a timing diagram of the formation of signals at the control points of the device; in fig. 4 is a comparator circuit.

The device contains comparators 1 and 2, switches 3 and 4, delay element 5, element AND 6. element NOT 7, element AND 8, trigger 9, element OR 10, trigger 11, element AND 12, counter 13, trigger 14. counter 15 , Element 16, counter 17, Element 18, counter 19, Element 20, clock pulse generator 21, Element 22, register 23, control block 24, control block 25, control groups 26-35, reference voltage input 36 , input 37 of the first monitored signal, input 38 of the reference voltage, input 39 of the second monitored signal, outputs 40-43. input 44 of the control unit 24.

Comparison unit 25 comprises a modulo two element 45, an element NOT 46, elements AND 47.48, a trigger 49, element And 50.

Comparators 1 and 2 contain operational amplifiers 51 and 52, resistors 53-56, operational amplifier 57, resistor 58, diodes 59 ibO.

The device works as follows.

In accordance with the program recorded in the microprocessor 24. By writing the unit to the corresponding register bit 23, a reset signal is issued, which sets the triggers 9, 14. 11 to the initial state.

After that, the device measures the signal timing.

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control formed when the input signal to the inputs of the meter.

The measurement is carried out as follows.

The block 24 records: in the counter 13 pulses of the return code corresponding to the number of periods of the control signals, for which the time of the periods in the counter of 15 pulses, the time of the pulse duration in the counter 17, the duration of the pause in the counter 19 is measured.

The measurement of time over N periods is carried out in order to increase the measured time interval.

Then block 24 by writing to the counters 15, 17, 19 zero code produces their zeroing. Thereafter, the microprocessor writes the unit to the corresponding register bit 23, thereby ensuring the issuance of the Start command. At this command, trigger 9 is transferred to a single state. Its output signal provides a controlled signal through the element And 12 in the counter 13 pulses and trigger 11.

When a monitored signal arrives, trigger 11 is transferred to a single state. Its output signal provides the passage of reference frequency pulses from the generator 21: to the counter 15 pulses through the element 16 to measure the time period of the monitored signal; to the pulse counter 17 via the And 18 pulse to measure the time of the monitored signal; pulse counter 19 through AND 20 to measure the pause of the monitored signal.

Upon the passage of the periods of the monitored signal, the counter 13 generates an overflow pulse. It arrives at the installation input into trigger unit 14, sets it to one state. The output signal from trigger 14 indicates the end of the measurement.

This output signal is fed to the setup input of the trigger 9 and through the element OR 10 to the setup input of the trigger 11, to drive them to the initial state. The pulses from the generator 21 to the counters 15, 17, 19 and the monitored signal to the counter 13 are stopped.

At the same time, the control unit 24 reads the signal. The end of the measurement from the output of the trigger 14 through the AND 22 element. If there is a signal at the end of the measurement, the block 24 reads the information recorded in the counters 15, 17. 19 pulses. After that, the block 24 monitors the presence of failures in the operation of the meters 15,

17.19 pulses by checking the ratio

MStg Msb + Mst „, (1)

where Hstg is the number of pulses corresponding to the time N periods of the monitored signal, recorded in the counter 15 pulses;

NCT3 is the number of pulses corresponding to the time N of pulses of the monitored signal recorded in the counter of 17 pulses;

NCT4 is the number of pulses corresponding to the pause time of the monitored signal recorded in the counter 19 pulses. 5 If ratio (1) is not fulfilled, block 24 makes repeated measurements and controls this ratio. When repeated failure to comply with the ratio (1), the microprocessor 26 stops the measurement process 0 and provides information to the indication unit 29 about the presence of a malfunction.

When performing relation (1), blr 24 monitors the operation of the device by controlling the delay time 5 (1 delay) of the signal by delay element 5.

The control is carried out by checking by the microprocessor 26 ratios 1min extra Ј g 1 delay 5 g 1 max extra, (2)

0 where 1delay is the measured delay time, which will be determined by the number of pulses recorded in the counter 17 pulses;

t.min dop - minimum allowable time-5 m delay;

t-max add - the maximum allowable delay time.

The maximum and minimum values of the delay time are determined by the output from the permissible value of the delay time of the monitored signals introduced by the input elements of the device, including the delay element 5.

If ratio (2) 5 is not fulfilled, further measurements are stopped.

The control unit 25 (FIG. 2) monitors the value of the output functions at the output of the AND elements 16 and 20 at that moment in time when the trigger 11 is in unit state, and the output of the element 18 is removed a signal equivalent to a logical zero. If at this point in time the signals at the output of the elements And 16, 20 are opposite, the trigger 49 is set to the 5 one state.

The control unit 24 can be executed on the microprocessor K580IK80. Formula of the invention 1. A device for controlling the phase shift of two signals, containing two comparators, the first switch, the delay element, seven AND elements, ten AND groups of elements, the NOT element, three triggers, two counters, a clock generator, a register and a control unit, the first input of the first comparator is connected to the first information input of the first switch and is the input of the first monitored signal, the equality output of the comparator is connected to the first input of the first element AND, the equality output of the second comparator is connected to in ode one delay element, the output of which is connected to the second input of the first element And, the output of which is connected to the first input of the second element And, to the input of the element NOT, the output of which is connected to the first input of the third element And, the second input of which is connected to the first output of the register, the second output which is connected to the first input reset to zero of the first trigger, to the reset input to zero of the second trigger, the output of which is connected to the second reset input to zero of the first trigger, to the first input of the fourth element And, the output of which is connected to the primary input of the group of inputs of the control unit, the first output of which is connected to the first inputs of elements of the first, second, third, fourth and fifth groups, the second output of the control unit is connected to the first inputs of elements of the sixth, seventh, eighth, ninth and tenth groups and with the second input of the fourth element And, the outputs from the first to the tenth first group of outputs of the control unit are connected to the second inputs of the elements And groups of the corresponding first to the tenth, eleventh output of the first group of outputs of the control unit connected to the third input the house of the fourth element And, the second group of outputs of the control unit is connected to the inputs of elements of the first, second, third, fourth and fifth groups, the outputs of elements of the sixth, seventh, eighth, ninth and tenth groups are connected to the groups of inputs of the first, second the third, fourth and fifth groups of inputs of the control unit, the outputs of the elements of the first group are connected to the information inputs of the first counter, the bit outputs of which are connected to the third inputs of the elements of the sixth group, the outputs of the elements of the second group with the information inputs of the second counter, the bit outputs of which are connected to the third inputs of elements And the seventh group, the outputs of elements And the fifth group are connected to information inputs of the register, the group of outputs of which is connected to the group of inputs of elements the first input of the fifth element I, the output of the first trigger is connected to the second input of the second element I, the output of which is connected to the counting input of the first counter; the synchronous input of the first trigger is connected to the bus one A device potential, characterized in that, in order to reduce the monitoring time, an OR element, a second switch, a third and fourth counters, and a control unit are inserted into the device, the starting input of the comparator unit is connected to the output of the third trigger, with the second output of the register; the permission input of the control unit of the control unit is connected to the output of the sixth element I and with the counting input of the third counter; the first information input of the task of the control unit is connected to the output

0 of the seventh element And with the counting input of the second counter, the input of the read resolution of the control unit connected to the first inputs of the elements And the sixth group, the second input of the ninth group of the control unit

5 is connected to the address input of the control unit, the output of the control unit is connected to the second input of the input group of the control unit, the second information input of the first switch is the input of the second monitored signal of the device, the first information input of the second switch is connected to the second input of the first comparator and is the first entrance. the reference voltage of the device, the second

5 the information input of the second switch is connected to the second input of the reference voltage of the device, the third output of the register is connected to the control inputs of the first and second switches, the outputs of the first and second switches are connected respectively to the first and second inputs of the second comparator, the output of the element is NOT connected to the second input p of the element And, the output of which is connected to the counting input of the fourth counter and with the second information input of the control unit, the output of the third element And is connected to the input of the installation in the unit th flip-flop, whose output is connected to the clock terminal of the third

0 flip-flop, the output of which is connected to the second input of the fifth AND element, to the first input of the sixth And element and to the first input of the seventh And element, the output of the OR element is connected to the reset input in the trigger5 of its trigger, the second output of the register is connected to the first input of the element OR, the second input of which is connected to the output of the second trigger, the output of the first element I is connected to the input of the unit installation of the third trigger and to the second input of the sixth element I, the third input of which is connected to the second input of the seventh element I and to the output of the clock generator, the overflow output of the first counter is connected to the installation input of the second trigger unit, the outputs of the elements of the third group are connected to the information inputs of the third counter, the discharge outputs of which are connected to the third inputs of the elements of the eighth group, the outputs of the elements of the fourth group are connected to information the inputs of the fourth counter, the bit outputs of which are connected to the third inputs of the elements And nine groups.

2. The device according to claim 1, wherein the control unit contains an addition element modulo two, the element is NOT. two AND elements, trigger, the first input of the modulo two element is the first information input of the block, the second input of the modulo two element is the second information input of the block, the output of the modulo two element is connected to the first input of the first And element, the output which is connected to the installation input in the trigger unit, the reset input to zero of which is the input of the initial installation of the block, the input of the element is NOT the input of the resolution of the control of the block, the output of the element is NOT connected to the first input of the second element And, the second input of which is the start input of the block, the output of the second element AND is connected to the second input of the first element I. The output of which is connected to the first input of the element AND, the second and third inputs of which are respectively read enable inputs and address input of the block, output element I is the output of a block.

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Claims (2)

Claim 1. A device for monitoring the phase shift of two signals, containing two comparators 5 connected to the first input of the fifth element And the output of the first trigger connected to the second input of the second element I. the output of which is connected to the counting input of the first counter, the clock input of the first trigger is connected to the unit potential bus device, characterized in that, in order to reduce the monitoring time, an OR element, a second switch, a third and fourth counters and a control unit are introduced into the device, the start input of the comparison unit being connected to the output of the third trigger, the input of the initial installation of the control unit is connected to the second output of the register, the input of the permission of the control of the control unit is connected to the output of the sixth element And and to the counting input of the third counter, the first information input of the job of the control unit is connected to the output of the seventh element And and to the counting input of the second counter , the read permission input of the control unit is connected to the first inputs of the AND elements of the sixth group, the second input of the ninth group of the control unit is connected to the address input of the control unit, the output of the control unit It is connected to the second, third input of the group of inputs of the control unit, the second information input, the first switch, the delay element, seven AND elements, ten groups of AND elements, the NOT element, three triggers, two counters, a clock, a register and a control unit, the first input of the first comparator is connected to the first information input of the first switch and is the input of the first controlled signal, the output of the equality of the comparator is connected to the first input of the first element AND, the output of the equality of the second comparator is connected to the input of the element the delay whose output is connected to the second input of the first AND element, the output of which is connected to the first input of the second AND element, with the input of the element NOT, the output of which is connected to the first input of the third AND element, the second input of which is connected to the first output of the register, the second output of which connected to the first reset input to zero of the first trigger, to the reset input to zero of the second trigger, the output of which is connected to the second reset input to zero of the first trigger, to the first input of the fourth element And, the output of which is connected to the first input of gr oppy inputs of the control unit, the first output of which is connected to the first inputs of the And elements of the first, second, third, fourth and fifth groups, the second output of the first switch is the input of the control current connected to the first inputs of the 50th controlled signal of the device, And the sixth, seventh , the eighth, ninth and tenth groups and with the second input of the fourth element And, the outputs from the first to tenth of the first group of outputs of the control unit are connected to the second inputs of the elements And groups corresponding to the first to tenth, eleven th output control unit of the first group of outputs coupled to a third input of the fourth AND gate, the second group control unit outputs connected to inputs of AND gates of the first, second, third, fourth and fifth groups of elements and outputs of the sixth, seventh, eighth. the ninth and tenth groups are connected to the input groups of the first, second, third, fourth and fifth groups of inputs of the control unit, the outputs of the And elements of the first group are connected to the information inputs of the first counter, the bit outputs of which are connected to the third inputs of the And elements of the sixth group, the outputs of the And the second group is connected to the information inputs of the second counter, the bit outputs of which are connected to the third inputs of the elements And the seventh group, the outputs of the elements And the fifth group are connected to the information the inputs of the register, the group of outputs of which is connected to the group of inputs of the elements of the tenth group, the clock output, the first information input of the second switch is connected to the second input of the first comparator and is the first input. the reference voltage of the device, the second 55 information input of the second switch is connected to the second input of the reference voltage of the device, the third register output is connected to the control inputs of the first and second switches, the outputs of the first and second switches are connected respectively to the first and second inputs of the second comparator, the element output is NOT connected to the second input of the fifth element And, the output of which is connected to the counting input45 of the fourth meter and with the second information input of the control unit, the output of the third element And so inen with the installation input to the unit of the first trigger, the output of which is connected to the sync input of the third 50 trigger, the output of which is connected to the second input of the fifth element And, with the first input of the sixth element And and with the first input of the seventh element And, the output of the element AND is connected to the reset input to zero is third55 of its trigger, the second output of the register is connected to the first input of the OR element, the second input of which is connected to the output of the second trigger, the output of the first element And is connected to the installation input to the unit of the third trigger and to the second input of the sixth e element I, the third input of which is connected to the second input of the seventh element And and with the output of the clock generator, the overflow output of the first counter is connected to the unit input of the second trigger unit, the outputs of the elements of the third group are connected to the information inputs of the third counter, the bit outputs of which are connected to the third inputs of the elements And the eighth group, the outputs of the elements And the fourth group are connected to the information inputs of the fourth counter, the bit outputs of which are connected to the third inputs of the elements And Yatoy group. 2. The device according to claim 1, characterized in that the control unit contains an addition element modulo two, an element NOT, two AND elements, a trigger, the first being the first information input of the block, the second input of the addition element modulo two is the second the information input of the block, the output of the addition element modulo two is connected to the first input of the first element And, the output of which is connected to the input of the installation in the trigger unit, the reset input to zero of which is the input of the initial installation of the block, the input of the element is NOT the permission input to For the control of the block, the output of the element is NOT connected to the first input of the second element AND, the second input of which is the start input of the block, the output of the second element And 15 is connected to the second input of the first element I. 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