SU1621146A2 - Device for shaping pulse trains - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation, control and monitoring devices. The aim of the invention is to expand the field of application by allowing the formation of pulses of various duty cycles. A device for forming a series of pulses contains a trigger 1, a pulse counter 3, a register 5, a comparison block 6, a number setting block 4, a setting block 10, an OR 9 element and a delay element 8. To achieve the set goal, a delay element 11 is inserted into the device, triggers 12 elements OR 13, 14. Zil.

Description

1

ABOUT

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The invention relates to a pulse technique and can be used in automation, control and monitoring devices.

The aim of the invention is to expand the scope by forming pulses with different duty cycle.

Figure 1 shows a block diagram of a device for generating a series of pulses; 2, 2 shows timing diagrams for his work.

A device for forming a series of pulses contains a trigger 1, a start bus 2, a pulse counter 3, a number setting unit 4, a register 5, a comparison unit 6, an output bus 7, a delay element 8, an OR element 9. a setup unit 10, a delay element 11, a trigger 12, elements OR 13, 14, with the C input of the trigger 1 connected to the start bus 2, and the output to the write input of the pulse counter 3, the information inputs of which are connected to the outputs of the number setting unit 4, the outputs of the pulse counter 3 are connected to the information inputs of the register 5 and with the first inputs of the block b comparison, w These inputs are connected to the outputs of the register 5, the output of the comparison unit 6 is connected to the output bus 7 and to the input of the delay element 8, the output of which is connected to the S input of the trigger 12, to the input of the delay element 11, to the input of the register 5 and through the OR element 13 - to the counting input of the counter 3 pulses, the direct output of the trigger 12 is connected to the second input of the element OR 13, the output 11 of the delay is connected through the element OR 14 to the R input of the trigger 12, the output of the installation unit 10 is connected to the first input of the element OR 9, the output of which connected to the R inputs of trigger 1, the counter and 3 pulses, register 5, to the second input of the element OR 14, the second input of the element OR 9 is connected to the borrowings of the counter of 3 pulses.

The device works as follows.

When the power is turned on, the installation unit 10 generates a setup pulse (reset pulse), which zeroes the triggers 1, 12, the pulse counter 3 and the register 5. Thus, in the initial state, the triggers 1, 12, the counter 3 and the register 5 are reset to zero. Block 4 is set to the code number, and on the output bus 7 - zero potential.

When a Start command is received via bus 2 (Fig. 2a), the trigger edge 1 is set to one on the leading edge of the pulse. On the leading edge of the signal from the output of the trigger 1 (Fig. 26), the number code from the number setting block 4 is rewritten into the counter of 3 pulses. At the output of the comparison unit 6, the leading edge of the first pulse of the series (Fig. 2b) is formed due to the inequality of the codes of the counter 3 and the register 5

at the inputs of block 6 comparison. After time Gzad.1 (fig.2g), determined by the delay element 8, the leading edge of the first pulse arrives at the S input of the trigger 12 (fig.2d), switching it to one state and

the input of the recording of the information of register 5 and rewrites the code from the outputs of the counter 3 into the register 5. At the output of the comparison unit 6, the falling edge of the first pulse of the series is formed. Through time G3ad.1 rear front of the first

a pulse appears at the output of delay element 8. At the counting input of the counter 3, a high (single) potential arriving through the OR element 13 (Fig. 2g) from the direct output of the trigger 12 is retained. The first pulse of the series delayed by the delay element 8 is also fed to the input of the delay element 11 (Fig. 2e) delay time of which gzad2 Tzad.1. The occurrence through time G3ad 2 (fig.2d) of an output pulse

The delay element 11, the trigger 12 switches to the initial zero state, at its output and, accordingly, at the counting input of the counter 3, a low (zero) potential appears, on the front of which one is subtracted from the contents of the counter 3. The code at the output of the counter 3 is changed, and at the output of the comparison unit 6, the leading edge of the second pulse of the series is formed. The device then works in a similar way.

When the counter 3 reaches the zero state, the leading edge of the last is formed at the output of the comparison unit 6

pulse series. After time 1, at the output of the delay element 8, the leading edge of the delayed last pulse of the series appears, through which the trigger 12 switches to one state, the zero value of the counter code 3 is rewritten into register 5 and the output of the counter 3 emerges since counter 3 is reset. The impulse from the output of the loan counter 3 enters through the element OR 9

0 (FIG. 2z) to the R-inputs of the counter 3 and register 5, confirming their zero state, to the R-input of the trigger 1, switching it to the zero state, and to the R-input of the trigger 12, on the direct output of which the time of the signal on the S-input is kept high (single) potential. At the output of the comparison unit 6, the leading edge of the last pulse of the series is formed, the device returns to its initial state.

the last delayed by the delay pulse element 8 of the series is set to the zero state of trigger 12, and then the pulse at the output of the delay element 11 confirms the zero state of trigger 12.

Thus, under the condition T3ad.2 Tzad.h, the device can form at the output of a series of pulses with different porosity (Q 2), the value of which is determined by the ratio of T3ad.1 and

Tzad.2.

Under the condition gzad.2 tzad.1, the device forms at the output of a series of pulses with a duty cycle equal to two. In this case, the device operates as follows.

When the Start command (Fig. 3a) arrives on the bus 2, the trigger edge 1 is set to one on the leading edge of the pulse. On the leading edge of the signal from the output of the trigger 1 (Fig.Zb), the number code from the number 4 block of numbers assignment is rewritten, The output of the comparator unit 6 forms the leading edge of the first pulse of the series (Fig. 3b). After time Tzad.1, the leading edge of the first pulse of the series from the output of the delay element 8 (Fig. 3g) arrives at the S output of the trigger 12 (Fig. Ze) and switches it to one state, to the input of the delay element 11 and to the information recording input register 5. At the output of the comparison unit 6, the trailing edge of the first pulse of the series is formed. After time G3ad.2, the leading edge of the first pulse from the output of the delay element 11 (Fig. 3D) goes through the element OR 14 to the R input of the trigger 12, the forward output of which maintains a high (unit) potential for the duration of the signal at S- the entrance. At the end of the first pulse at the output of the delay element 8, the trigger 12 switches to the zero state (due to the effect of a signal at its R input). At the output of the trigger 12, at the output of the element OR 13 (FIG. ZH) and, accordingly, at the counting input of the counter 3, a zero potential appears, on the front of which one is subtracted from the contents of the counter 3. The code at the output of counter 3 is changed, as a result of which, at the output of comparison unit 6, the leading edge of the second pulse of the series is formed. In the future, the device works in a similar way.

When the counter 3 reaches the zero state, the leading edge of the last pulse of the series (FIG. 3) is formed at the output of the comparison unit 6. After time 7 Zed.1. At the output of the delay element 8, the leading edge of the delayed last pulse of the series appears, through which the trigger 12 switches to one state, the zero value of the counter code 3 is written into the register 5 and at the output of the loan

5, counter 3, a pulse appears, as counter 3 is zeroed. The impulse from the output of the counter 3 goes through the element OR 9 (Fig. 3) to the R-inputs of the counter 3 and the register 5. confirming their zero state, to R10 the trigger input 1, switching it to the zero state, and to the R-input the trigger 12, on the forward output of which a single signal is stored for the duration of the pulse at the S input. At the output of the comparison unit 6, the leading edge of the last pulse of the series is formed. Upon completion of the pulse at the output of the delay element 8, the trigger 12 switches to the zero state, the device returns to its initial state.

Thus, this device allows to expand its area of application by forming a series of pulses of various duty cycles at the output. The duration of the pulses is determined by time.

5 the delays of the second delay element are Tzed.1, and the pause between pulses is determined by the delay time of the second element

Delays - Gzad.2. ON CONDITION TIER 2

ass 1 the pulse ratio is equal to two 0 (Q 2). Under the condition Gzad 1, the device generates a series of pulses of different porosity (Q 2), the value of which is determined by the ratio between gzad2 and Tjad.1. The number of pulses in a series is determined by the code of the number in the block 4 specifying the numbers.

Claims (1)

The invention of the device for forming a series 0 pulses auth. Ev, No. 1420649, which is so that, in order to expand the scope of application by ensuring the formation of pulses of different porosity, a second trigger, a second delay element, a second and a third OR element, are introduced into it, moreover, the S-input of the second trigger is connected to the output of the first delay element and to the input of the second delay element, the output of the second trigger is connected to 0 by the first input of the second element OR, the output of the second delay element is connected to the first input of the third OR element, the second input of which is connected to the output of the first OR element, the output of the third element 5 OR is connected to the R-input of the second trigger, while the output of the first delay element is connected to the counting input of the pulse counter via the second element OR. About i (Start) G- F 3 Ug (Cdpoc) and Cg g 6 Ui d Uc f-Ml Lee Zh Ui $ 3 Ug P FIG. 2 --AND