SU1672434A1 - Analog data input device - Google Patents

Abstract

The invention relates to computing and can be used in automated control systems for analog electric circuits and for inputting analog information into a computer. The purpose of the invention is to expand the field of application of the device by automatically adjusting the quantization step with a change in the frequency of the signal under study. The device contains ADC 1, register 2, memory block 3, pulse generator 5, counters 4 and 18, comparator 6, AND-NOT elements, six triggers, OR element, OR-NOT element, AND elements, NOT 7. 4 element silt

Description

cl

with

and vi to

Ј

with

The invention relates to computing and can be used in automated systems for controlling analog electric circuits and for processing on an analog computer signals.

The aim of the invention is to expand the field of application of the device due to the automatic adjustment of quantization of quota when the frequency of the signal under study is changed.

During the first period of the input analog signal, the code accumulates at the outputs of the second counter

LA KT0

where TA is the period of the input analog signal;

That is the period of the clock signal;

K - a binary code installed at the inputs of the CO, C1C (K-1) device.

During the second period of the input signal, the operation of the first and second counters is prohibited, and the number of sample codes of the input analog signal recorded in RAM is as follows:

2 TA

Tg

TA

As can be seen from equality (2), the number of codes of samples of the input signal does not depend on the period of this signal, and the quantization step with which the codes of the samples are entered into RAM is directly proportional to the signal period

TKV 2 Tn L 2 Tc

2 TA 4p.

 (3)

where TQ is the quantization period.

Thus, the device automatically adjusts the quantization period to the frequency of the input analog signal so that RAM always writes K samples into one period, where the K number is specified by the input code. This shows that the device can operate in a wide frequency range, which determines the expansion of the field of application of the device.

Figure 1 and 2 presents the block diagram of the device; 3 and 4 are diagrams illustrating the operation of the device.

The device for input of analog information (Figs. 1 and 2) consists of an analog-digital converter (ADC) 1, register 2, memory block 3, first counter 4, pulse generator 5, comparator 6, NOT element 7. first wto 5

ten

15

20

25

thirty

35

40

45 50

55 of the pry and third elements are AND-NE 8-10, the first and second triggers 11 and 12, the first element AND 13. the third trigger 14, the second element 15, the first frequency divider 16. the fourth trigger 17. the second counter 18. the third element AND 19, the fourth element AND 20, the second divider 21 frequency, the fifth trigger 22, the element OR-NOT 23, the element OR 24, the fifth element AND 25, the sixth trigger 26, the sixth element And 27, fourth 28 and p of the 29 elements AND-NOT.

The input signals to the device are the analog input signal UBX and the threshold voltage Unop; logical signals, the reset signal of the SSR, the start signal of the SIT signal of the start type VZ, the control signal of the C / V mode setting (removal / expansion), the read signal of the CT device, the signal of the installation of the period code. ., code signals of the number of sample codes

input analog signal WITH, С1С (К-1),

period code signals SO, S1S (L-1).

The output signals of the device are the signal codes of the samples of the input analog signal DO, D1D (N-1), the output

the period code signals of the input analog signal PO Р1P (L-1), the readiness signal (GI,).

The device works as follows.

The data inputs DO, D1D (K-1) of the first frequency divider 16 are fed with a code for the number of codes of the samples of the tax signal. A CBP signal is given. When this signal is applied, a logical O appears at the output of the first element And 13. As a result, a logical 1 is established at the output Q of the third flip-flop 14. At the input S of the second flip-flop. 12 is the logic level O. As a result, the output Q of this trigger is logical 1 (signal C of the timing diagram, fig. 3), and the output Q is the level of the dogic O, which is fed to the input R of the first trigger 11, is set at its output Q logic level O (signal B of the time diagram, figure 2). Therefore, at the output of the second element I 15, and therefore, at the input of the preset V of the first frequency divider 16, as well as at the input R of the fourth trigger 17, the state is logical O, as a result of which the operation of these elements is prohibited. After transferring the CBR signal to the logical 1 state (time point T1), the operation of the second and third triggers 12 and 14 is permitted.

To switch the device to the recording mode of the input signal samples (Clear mode), the C / B signal is set to logical 1 (time point T2). As a result of this positive front

a C / B signal at input C of the third flip-flop 14 at a logic level 1 at its input D at its output Q appears a logical O signal, and at the output Q a logical 1, so that the output Q of the second flip-flop 12 sets the logic level O and the output Q is a logical one. thereby resolving the operation of the first trigger 11. Since the signal of the logical O is present at the second input of the AND 19 element (signal C of the timing diagram, fig.3), the first input of the sixth element AND 27. the second input of the fifth element And 25, and consequently, at the inputs R of the sixth trigger 26, on the input of the fourth element I 20 and its output, as well as the input V (preset) of the second frequency divider 21, then the operation of the frequency divider 21, the fifth and sixth triggers 22 and 26 is prohibited. The level of logic O at the second input of the fourth element I- NOT 28 sets the state to logical 1 at its output and thereby prohibits the operation of counter 4,

With the appearance of a logical signal at the output Q of the third trigger 14 (time diagram signal D. FIG. 3), the logic level O is set at the outputs QO, Q1Q (L-1) of the second counter 18.

Depending on the input signal level V.Z. The device can operate in two modes. If the signal V.Z. has a logical level O at the second input of the first element AND-NOT 8 - a logical signal O, and at its output - a logical signal 1. At input 2 of the second element AND-NOT 9 - a logic level 1. and the device operates from an external logical signal LAP, which arrives at the first input of the second element AND-NOT 9, inverted, comes to the second input of the third element AND-NOT 10 and. once again inverted. passes to the input of the first trigger 11 (signal A timing diagram). The LAP signal is generated by an external trigger circuit. If the signal V.Z. has a logic level 1, then the input2 of the second element AND-NOT 10 is the logical level O, and the input of the third element IS-NOT 10 is the logic level 1 and thus the passage of the LAP signal is prohibited and the passage of the signal C at the first trigger 11 is allowed comparator output 6.

At the transition of the signal UBx through the Unop level (timing diagram of FIG. 3, time point of the specification), the output of comparator 6 shows a positive edge of the logical signal and. having double inverted, passes to the input C of the first trigger 11 (signal A of the timing diagram, FIG. 3), is set to the state 1

its output is Q. As a result, logic level 1 appears at the input of the first frequency divider 16 and the R input of the fourth trigger 17, allowing them to work. At the same time, the logic level O is set at the output Q of the first flip-flop 11 and, therefore, at the first input and at the output of the first And 13 element, with the result that the Q output of the third flip-flop 14 (signal D

0 timing diagram. FIG. 3) establishes the logic level O by allowing the operation of the second counter 18. The input signal of the INSTALLATION COMP. has a high logic level, and the entry of the input code SO. S1, S2, ... S (L-1)

5 in the second counter 18 does not occur. At the input R of the second trigger 12, a logical 1 signal appears, enabling the operation of this trigger.

When K pulses from the generator output 5 of pulses arrive at the counting input of the first frequency divider 16, a logic level O appears at its output, which, arriving at the second input of the second element 15, passes to the input V of the first frequency divider 16, as a result CO code is written to the internal register of the latter,

C1C (K-1) (code number of sample codes), after

which, the signal at the output Z returns to the state of logical inverts the signal at the output Q of the fourth flip-flop 17. As the input D of this flip-flop is given a signal from the output O. Each edge of the signal is from the output O of the fourth flip-flop 17 (the signal E of the timing diagram ) increments the output code QO, 01, ... Q (L-1) of the second counter 18.

To the moment of the second transition of the input analog signal through the Unop level, corresponding to the end of the period of the input signal or the arrival of the second trigger pulse (time point T4 of the time diagram, FIG. 3). at the input C of the first trigger 11, a signal front is formed, which sets the output Q of this trigger

5 (signal B of the timing diagram, Fig. 3) the level of logical O, since up to this point, the input D of the first trigger 11 was a logical level of 1 0. The appearance of a logical O at the input of the first frequency divider 16 and the input R of the fourth trigger 17 prohibits the operation of these elements. At the same time, the rise of the signal at the output Q of the first trigger 11 sets the output Q of the second trigger 12 to a high logic level (signal C of the timing diagram, FIG. 3), thereby setting the logic level at the outputs of the elements And 19 20. 25 and 27 dry the logical level and, therefore, allowing the second divider 21 to work, the p and the sixth trigger 22, and

0

five

0

five

0

0

five

26 and counter 4 (at the fourth input of the element AND 19 - the level of logic 1 since the sixth trigger 26 is set to the logical state O). Also at this moment, the logic level O established at the output Q of the second trigger 12 prohibits changing the levels of the signals at the outputs of the first trigger 11.

By the time T4 (time diag-

frame, fig.Z) at the outputs of QO, Q1Q (L-1)

second counter 18 and respectively on

DO, D1D (L-1) splitter 21 frequency inputs,

which are also the outputs of the PO. P1P (L-1)

device, fixed code, the numerical value of which is proportional to the period of the input analog signal:

I -

2 Td To That

where TA is the period of the input analog signal:

T0 is the period of the clock signal;

K-code at the inputs of the CO, C1C (K-1) device.

Frequency divider 21 and fifth trigger 22 operate similarly to elements 16 and 17. When L pulses are sent to the counting input of frequency divider 21 from the output of the B. pulses generator, the output of this frequency divider appears logic level O and arrives at the input of the AND element 19, passes to the input V of the frequency divider 21, as a result of which the code set at the outputs will again be written into the register of this divider

QO.Q1Q (L-1) of the second counter 18. After

This signal at the output Z of the frequency divider 21 again assumes the level of logic 1, and the front of this signal inverts the signal at the outputs Q and Q of the fifth flip-flop 22, since its output Q is connected to the input D. At the front of the signal at the output Q of the fifth flip-flop 22 (signal F of the timing diagram, fig. 3) the code from the output of the A / D converter 1 is written to register 2, the signal at the output of the OR-NO 23 element has a low logic level (signal M of the timing diagram, fig. 3), since the first input is a logic level 1 (C / V signal), so a logic level 1 appears at the output element OR (signal H time diagram, fig.Z) when F has a high logic level. The recording takes place in block 3 when the signal at the output of the NAND 29 element receives a logic level O (signal P of the timing diagram, FIG. 3). This occurs when a logic level 1 appears at the output Q of the second trigger 22.

five

YU

15

20

25

30 35

Counter 4 operates as follows. The difference 1 - O at the input +1 of the direct count increments the code on its internal registers, and the next difference O leads to this code in the output register (the outputs of the counter QO. Q1Q (K-1). Thus, the following sequence is observed Belt diagram, Fig. 30 signals F, H, P): write to register 2, write to block 3, change of address.

At time T5 (Fig. 3), the input voltage UBx passes through a threshold level (or a regular pulse of the LAP signal passes). and at the output of the third element IS-NOT 10 a signal front is formed, which sets the output Q of the sixth trigger 26 to a low logic level. As a consequence, the logic level O appears at the input of the element AND 19, at the output of the sixth element And 27 (signal L of the time diagram, Fig. 3) and, respectively, at the second input of the fourth by the elements 20 and at its output. As a result, the input V of the second frequency divider 21 and the input R of the first trigger 22 establish a logic level O, prohibit their further operation and set the logic input O at the first input of the OR element 24.

At this point, the number of sample codes recorded in block 3 is:

TO

TA ToL

(five)

where L is the code on the outputs QO, Q1Q (L-1) of the second counter 18.

At the output Q of the sixth trigger 26, a logic level 1 is set. This is the output signal indicating the end of the writing process of the sample codes (the GI signal of the time diagram, FIG. 3) to the operational memory block. At the same time, the logic level O appears at the first input of the fifth element AND-NE 29 (signal N of the time diagram, FIG. 3), sets the level of the logical G at the input W / R of block 3, which corresponds to the reading mode.

In order to read from the 3 sample codes of the analog signal, it is necessary to apply a CBP signal. which, arriving at the first input of the fourth element IS-HE 28, sets the state of logical 1 at its output, as a result of which the outputs QO, Q1Q (K-1) of counter 4 accept the state of logical O.

After transferring the CBP signal to the logical 1 state (time instant T6 of the time diagram, Fig. 3), the C / B signal needs to be switched to the logical O state, which corresponds to switching the device to the Sampling mode. At the same time, at the output of the fourth element, AND 20 (signal N of the time diagram, FIG. 3) is the logic level O, and at the input W / R of block 3, the level of logic 1 (the signal P of the time diagram, FIG. 3), which corresponds to the reading mode from the block. At the first input of an OR-NOT 23 element, the logic level is O, which permits a change in the signal at the output of this element (the signal M of the time diagram, Fig. 3) as the signal CTU changes. When translating the signal to THU. a logic level 1 (output signal H of the time diagram, FIG. 3) appears in the state of logical 1 at the output of the element OR 24 and an increase of 1 code occurs on the internal register of the counter 4, and also the sampling code is set at the outputs QO. Q1 ,. ., Q (K-1) corresponding to the current address on the address inputs of block 3. When translating the signal THU. in the state of logical O, an increase of 1 occurs.

code on the outputs QO, Q1Q (K-1) counter 4.

This procedure occurs until all sample codes are read from block 3 (time diagram T8, FIG. 3).

If it is necessary to record and read from block 3 codes of samples of the input signal for the time specified by the input digital code

SO, S1S (L-1). must submit this code

the inputs DO, D1D (L-1) of the second counter

18, set the state of the CBP input signal into FIG. 4 (FIG. 4). then set the logical 1 input signal to C / B. The 5 pulse generator must be disabled. Next you need to remove the CBP signal. When the C / B signal goes into the logical 1 state, the first, second, and third triggers 11, 12, and 14 do not change their states, since at the R input of the third trigger 14 there is a low logic level. After the RBS signal is removed, the input signal SET. in the state of logical O, as a result of which, at the outputs QO, Q1О (Ы) of the second counter 18, the code S1S (L-1) will be set. In the future, the signal SET. K.P. can be After this, the state of the device is completely identical to the state after time T4 (FIG. 3). Then, simultaneously with the arrival of the front of the signal at the input C of the first trigger 11 (signal A of the timing diagram, FIG. 4), it is necessary to start the pulse generator 5, and further operation of the device is completely similar to working from time T4 to time T8 of the timing diagram (FIG. four).

Thus, the use of the invention allows to expand the field of application of the device by automatically adjusting the quantization step with a change in the frequency of the signal under study.

Claims (1)

A device for inputting analog information containing analog-digital converter, first and second counters, first trigger, pulse generator, first and second frequency dividers, first AND element, OR element. the RAM block, the analog-digital converter input is the information input of the device, the outputs of the RAM block are the information outputs of the first group of the device, the address inputs of the RAM block are connected to the outputs of the first counter, characterized in that. in order to expand the field of application of the device due to automatic adjustment of the quantization step when the frequency of the signal under study is changed, a register, the NOT element, the OR-NOT element, the second sixth I. elements are entered into the device. the second - sixth triggers, the outputs of the analog-digital converter are connected to the information inputs of the register, the outputs of which are connected to the information inputs of the RAM, the output of the pulse generator is connected to the counting inputs frequency dividers, the first input of the comparator is the information input of the device, the second input of the comparator is connected to the reference voltage source, the output of the comparator is connected to the first the input of the first NAND element, the second input of which and the input of the element are NOT the input for selecting the launch mode of the device. the second input of the second element AND is NOT connected to the output of the element is NOT, and the first input is the start-up input of the device, the outputs of the first and second elements AND-NOT are connected to the inputs of the third element AND-NOT, the output of which is connected to the clock inputs of the first and sixth triggers, direct the output of the first trigger is connected to the first input of the second element I and the reset input of the fourth trigger, and the inverse output to the information input of the first trigger, the first input of the first element I and the clock of the second trigger, the inverse output of which is connected to the reset output of the first trigger, and the direct output - with the first inputs of the third, fifth, and sixth AND elements and the first input of the fourth AND – NOT element, the second inputs of the first element And And the fourth NAND element and the setup input in 1 of the second trigger are the device reset input, the output of the first element I is connected to the reset input of the third trigger, the inverse output of which is connected to the reset input of the second trigger and direct to the reset input of the first counter, the outputs of which connected to the preset inputs of the second frequency divider and are information outputs of the second group of the device, the clock input of the third trigger, the second inputs of the third and fifth And elements and the first inputs of the fourth And element and the element LIE-NOT are the control input of the device, the inputs of the preset of the first frequency divider and the first counter are the inputs of the preset of the first and second groups of the device, the output of the second element I is the control input of the first frequency divider, the output of which is connected to the second input of the second element And the clock input of the fourth trigger, the inverse output of which is connected to the information input of the fourth trigger, and the direct output to the counting input of the first counter, whose recording input is the recording input of the device TWA, the output of the third element And connect with the control input of the second frequency divider, the output of which is connected to the third input of the third element AND and the clock input of the fifth trigger, inverse 5 the output of which is connected to the information input of the fifth trigger and the first input of the fifth NAND element, and the direct output to the register entry input and the first input of the OR element whose output is connected to the counting input of the second counter, the reset input of which is connected to the output of the fourth element AND-NOT, the output of the fourth element AND is connected to the reset input of the fifth trigger and the second input of the fifth 15 element AND-NOT, the second input of the element OR-NOT is the input of the reading device, the output of the element OR-NOT is connected to the second input of the element OR, the output of the fifth element AND is connected to the reset input 20 of the sixth trigger, the direct output of which is output the device is ready, and the inverse output is with the fourth input of the third element AND and the second input of the sixth element AND, the output of which connects 25 pins with the second input of the fourth element AND, the output of the fifth element AND-NOT is connected to the input write / read of the RAM block Fi & W FIG L