SU1667268A1 - Device for preliminary synchronization - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to improve the accuracy of synchronization of the time ratios of information and clock pulses. The pre-synchronization device contains D-triggers 1, 10 and 11, elements AND 6 and 7. The goal is achieved by introducing impulses 2 and 3 pulses, elements OR 4, 5 and 12 and RS-triggers 8 and 9, with the help of which the preliminary processing is carried out potential impulse information. 1 il.

Description

The invention relates to a pulse technique and can be used in systems for the preliminary processing of potentially pulse code information.

The purpose of the invention is to improve the accuracy of synchronization of the temporal relationships of information and clock pulses.

The drawing shows a structural electrical diagram of a device for pre-synchronization.

The pre-synchronization device contains a first D-trigger 1. the first driver 2 pulses, the second driver 3 pulses, the first element OR 4, the second element OR 5, the first element And 6, the second element And 7, the first RS-trigger 8, the second RS-trigger 9, the second D-trigger 10, the third D-trigger 11. the third element OR 12.

The pre-synchronization device operates as follows.

In the initial state, the first D trigger 1 can be in two states in the single or zero. Suppose that D-trigger 1 is in the zero state, then the information input D of this trigger receives a unit potential (high signal level) from its inverse output, which also goes to the input of the second pulse shaper 3 and to the second input of the first element OR 4. From the direct output of the first D-flip-flop 1, a low signal level (zero potential) is supplied to the input of the first driver 7 pulses and to the first input of the second element OR 5. From the output of the first element OR 4 to the second input of the first element And 6 potential, and on the inverse zeroing input of the first RS trigger 8 - potential that prohibits reset. Through the second element OR 5, the inhibitory potential enters the first input of the second element And 7, and the potential that resets the ego1 trigger arrives at the input and resets the input of the second RS-trigger 9. When a pulse of information arrives at the information input of the device using the first element And 6, the first RS-trigger 8 is set to a single state. When the first pulse of the synchronizing sequence arrives at the clock input of the device, the first D-trigger 1 is set to a single state, and a short pulse is formed at the output of the first Pulse driver 2, which, on the front, sets the second D-trigger 10 to a single state, since its information input was present a high signal level.

From the direct output of the first D-flip-flop 1, the resolving potential through the second element OR 5 goes to the first input of the second element And 7, and to the inverse zeroing input of the second RS-flip-flop 9, the potential prohibits the reset of this trigger. When the second pulse of information arrives at the information input in a single state, the second RS trigger 9 is installed. The potential comes from the inverse output of the first D-trigger 1 through the first element OR 4 to the inverse zeroing input of the first RS-trigger 8. resetting the first RS-trigger 8 to zero. When a pulse of a synchronizing sequence arrives at the device’s clock input, the first D-trigger 1 is set to zero, at the output of the second driver 3 they are pulled, a short pulse is generated, which resets the second D-trip 10 and sets the third D trigger 11 and etc. The processes in the device are repeated.

Claims (1)

Claim Pre-sync device. containing three D-flip-flops, two elements of I. characterized in that about. In order to increase the accuracy of synchronization of the temporal relationships of information and clock pulses, two RS-flip-flops and two pulse shapers were introduced. three OR elements, the direct output of the first D-trigger connected to the first input of the second OR element and the input of the first pulse former, the output of which is connected to the clock input of the second D-trigger, zeroing the input of the third D-trigger and the first input of the first OR element, the output of which connected to the inverse zeroing input of the first RS-trigger and the first input of the first element I. the output of which is connected to the S-input of the first RS-trigger, the output of which is connected to the information input of the second D-trigger, the zeroing input of which is connected nen with the clock input of the third D-triggers, the output of the second pulse shaper and the second input of the second OR element, the output of which is connected to the inverse zeroing input of the second RS-trigger and the first input of the second element I. whose output is connected to the S-input of the second RS-trip the output of which is connected to the information input of the third D-trigger, the output of which is connected to the first input of the third OR element, the second input of which is connected to the output of the second D-trigger, the inverse output of the first D-trigger 5 connected to the input of W of the second pulse driver, the second input of the first OR element and its own information input, and the second input of the first AND element is connected to the second input of the second AND element and is the information input of the device, the information output of which is the output of the third OR element. and the clock input of the first D-trigger is the clock input of the device.