SU1536437A2 - Device for check of synchronism of reproduced signals - Google Patents

Abstract

The invention relates to the accumulation of information. The purpose of the invention is to reduce the error in checking synchronism. In the case of a temporary loss of a reproducible pseudo-random sequence of characters from the input bus 2 of the pseudo-random signal, the logic zero level arrives at the shift register 4. In this case, the shift register 4 ensures the formation at the output of an ORIEN 12 element of a logical unit level, which is fed through the OR 11 element to the detector 3 without errors, preventing its triggering. 1 il.

Description

The invention relates to the accumulation of information, in particular to devices for controlling the synchronism of reproduced signals.

The purpose of the invention is to reduce the error of control of the synchronism of reproduced signals.

The drawing shows one of the possible variants of the proposed device for controlling the synchronism of reproduced signals.

The device contains a first adder 1 modulo two, the first input of which is connected to the input bus 2! pseudo-random signal, detector 3 1 no errors, register 4 shift! and the second adder 5 modulo two. : The clock input of the shift register 4 and • the clock input of the detector 3 are absent • errors are connected to the bus 6 clock pulses, the inputs of the second adder 5! connected to the outputs of the register 4 shift 'ha, the output of the second adder 5 is connected to the second input of the first adder 1.

The device also contains a pseudo-random sequence detector 7, a trigger 8 and a switch 9, the first signal input of which is connected to the input bus 2 of the pseudo-random signal, and the second signal input: with the output of the second adder 5. Output; switch 9 is connected to the information input of shift register 4, and the equalizing input is connected to the output of trigger 8 connected to output bus 1Q.

The single input of trigger 8 is connected to the output of the detector 3 of the absence of errors, and the other input is connected to the output of the detector 7 of the pseudo-random sequence. ί The inputs of the latter are connected to the output of the first adder 1 and to the bus 6 clock pulses.

The device also contains an OR element 11, through which the output of the first adder 1 is connected to the error detector 3, and an OR-NOT 12 element connected to the outputs of the shift register 4, the latter being made with additional outputs connected to other the inputs of the element OR NOT 12 connected by the output to the input of the element OR 11.

A device for controlling the synchronism of reproduced signals works as follows.

To the input bus 2 of the pseudo-random signal and to the bus 6 clock pulses from the outputs of the monitored channel of the digital magnetic recording-reproduction, respectively, the reproduced digital signal and the accompanying clock synchronization signal of reproduction are supplied. In this case, the reproduced digital signal is a test signal having the form of a pseudo-random sequence of characters.

At the initial moment of operation, in the absence of synchronism between the reproduced pseudorandom sequence of characters and the control pseudorandom sequence of characters generated by the shift register 4 and the second adder 5, the first adder 1 generates an error signal. This signal is a pseudorandom sequence in structure, the period and code formation of which correspond to the reproducible pseudo-random. character sequences. The error signal of the first adder 1 acts on the pseudo-random sequence detector 7, which switches the trigger 8, while the latter switches the switch 9, which begins to pass the reproduced pseudo-random sequence of characters to the information input of the shift register 4. After the register 4 is completely filled with an error-free reproducible pseudorandom sequence of characters, the first adder 1 ceases to generate an error signal, which is detected by the detector 3 for the absence of errors. In this case, the latter generates a signal that returns to the initial state trigger 8, which switches the switch 9. As a result, the shift register 4 and the second adder 5 begin to form a control pseudorandom character sequence synchronous with the reproduced pseudorandom character sequence. Moreover, the first adder 1 does not generate an error signal or generates only single symbolic errors, which the pseudo-random sequence detector 7 does not respond to.

After a failure of the clock synchronization signal of reproduction, which is expressed in a decrease or increase in the number of clock intervals for a certain period of time, the synchronism between the reproduced and control pseudorandom sequences of symbols is violated. So, for example, when an extra clock pulse occurs, an additional information shift occurs in the shift register 4, as a result of which the subsequent control pseudorandom sequence of characters is formed with a shift of one clock cycle relative to the reproduced pseudorandom sequence of characters. In this case, the first adder 1 generates an error signal to which the pseudo-random sequence detector 7 responds, triggering the trigger 8. The output signal of the trigger 8 is fed to the output bus 10 and switches the switch 9, through which re-synchronization of the shift register 4 begins.

In the event of a temporary disappearance of the reproduced pseudo-random sequence of characters from the input bus 2 of the pseudo-random signal, the level 0 is received at the information input of the shift register 4. In this case, the shift register 4 ensures the formation at the output of the OR-NOT 12 element of level 1, which enters through the OR element 11 to the detector 3 of the absence of errors, preventing its operation. The latter ensures the operation of the detector 3 of the absence of errors only when a pseudo-random signal is received on the input bus 2 without an erroneous reproducible pseudo-random sequence of characters.

The present invention allows to significantly reduce the error of control of the synchronism of reproduced signals.

Claims (1)

Claim Device for controlling synchronization. 20 of reproduced signals by 'ed, sv. 1? 1256092, characterized in that, in order to reduce the error of synchronism control, an OR element is inserted into it, through which the output of the first adder is connected to the error detector, and an OR-NOT element connected to the inputs of the shift register outputs, the shift register being made with additional outputs connected to other inputs of the OR-NOT element connected to the output with the input of the OR element.