SU1520571A1 - Information transceiver - Google Patents

Abstract

The invention relates to radio engineering and can be used in multi-channel information transmission systems with pulse-code modulation. The purpose of the invention is to increase the information content of the device. The device contains on the transmitting side points 1 and 2 of the transfer, the shift register 3, the element AND 4, the element OR 5, the linear transmitting unit 6, the element OR 7, the inverter 8, the element AND-9, the trigger 10, the element-AND 11, shift register 12, element AND 13, synchronization unit 14, receiving stations 27 and 28 on the receiving side, linear receiving unit 29, AND elements 30 and 31, clock receiving unit 32, inverter 33, AND NOT 34 and 35 elements, trigger 36. When transmitting information from paragraph 1 of the transmission, a unit is set in the first discharge of the 3 shift register, and when information is transmitted from paragraph 2, soap has set zero in the first discharge shift register 12. 2 Il.

Description

Фа1.1

The invention relates to radio engineering and can be used in information transmission systems with impulse modulation.

The purpose of the invention is to increase the information content of the device.

Fig, 1 shows a functional diagram of the transmitting side; Fig 2 is a functional diagram of the receiving side.

The device contains on the transmitting side points 1 and 2 of the transmission, register 3 shift, the element AND 4, the element OR 5, the linear transmitting unit 6, the element OR 7, the incoming mountain 8, the element КЧ1Е 9, the trigger 10, the element AND NOT 1 , the shift register 12, the element And 13 and the block 14 synchronization.

Each transmission point contains a generator 5 pulses, an adaptive switch 16 consisting of a comparison unit 7, a memory block 18, a key 19, a memory block 20, a priority measurement block 21, and a sampler 22, in addition, each transmission point contains a channel number decoder 23, a signal encoder 24, a transmitter 25 and a channel number encoder 126. On the receiving side, the device contains receiving points 27 and 28, a linear receiving unit 29, AND elements 3D, 31, receiving unit 32 synchrosh 3 inverter 33, elements AND-HE 34 and 35 and trigger 36. Each receiving item contains receiver 37, decoder 38 signals, keys 39, memory blocks 40, filters 41, descramblers 42 channel numbers and a total of 43 pulses.

The device works as follows.

When transmitting each codeword from transmitter output 25 of paragraph 1, the device sets a single value in the first readable bit - de register 3 shift, and when transmitting each codeword from the transmitter output 25 of transmitting point 2, the device sets a zero value in the first considered bit - ry shift register 12. When writing a non-zero value of the code word in the shift register 3, the latter is transmitted over the communication line, and the transfer of the code word recorded in the shift register 12 is blocked. If from the transmitter output 25 point 1 to the shift register 3 is written the code word, all the elements of which 1meet

Zero value, the device transmits to the communication line a code word written to shift register 12. When transmitting a non-zero code word written to the shift register 3 at least from one of the codes of the shift register bits 3, except for the first counted bit, a high signal level turns the element OR 7 at the first input of the AND-NE element 1 and coincides with time with a control signal. The output signal of the NAND 11 element sets the trigger 10 to one state. The high level of the signal from the direct output of the trigger O is fed to the input of the AND 4 element and allows the transmission of a code word readable from the shift register 3, through the AND 4 element, the RSHI 5 element and the linear transmitting unit 6 to the communication line. In this case, the low level of the signal from the inverse output of the trigger 10 enters the element And 13 and prohibits the transmission of the code word counted from the shift register 12 through the element 13, If the zero word is written to the register 3 from the output of the transmitter 25 point 1, then low The signal level from all outputs of the 3-shift register, except for the output of the first counted bit, through the OR element 7 and the inverter 8 enters the first input of the AND-HE element 9 and coincides in time with the control signal. The output signal of the NAND 9 element sets the trigger 1.0 to the zero state. The high level of the signal from the inverse output of the trigger 10 enters the input of the AND 13 element and allows the transmission of a code word read from the shift register 12 through the AND 13 element, the OR 5 element and the linear transmitting unit 6 to the communication line. At the same time, the low level signal from the direct output of the trigger 10 enters the input of the AND 4 element and prohibits the transmission of the zero code word read from the shift register 3 through the AND 4 element. The synchronization signal from the second output of the synchronization unit 14 through the OR 5 element and the linear transmitter block 6 enters the link. At the same time, in the previous channel interval, the transmission of code words from points 1 and 2 is not performed.

A linear signal. Enters the input device of the receiving side. The operation of the device side receiving osugar.stv515

It depends on the reception of a high or low signal in the first received codeword bit. When receiving a high level in the first element of the code word, the high level of the linear signal from the first output of the linear receiving unit 29 arrives at the first input of the AND-HE element 34 and coincides in time with a high level of the synchronization signal acting at the second input of the AND-HE element 34, the Output the signal element AND-NOT 34 sets the trigger 36 to one state, and the high signal level from the direct output of the trigger 36 is fed to the second input of the I 30 element. In this case, the received code word from the first output of the linear receiving unit 29 through the element AND 30 enters the input of the first receiving point 27. If the level of the signal at the output of the linear receiving-Guo block 29 is registered in the first received code word discharge, then the inverter 33 supplies a high level of the signal to the second input of the IS-HE element 35 which coincides in time with the synchronization signal acting at the input of the AND-NO element 35. At the same time, the output signal of the AND-HE element 35 sets the trigger 36 to the zero state, the high level of the signal from the inverse output of the trigger 36 goes to the input of the AND element 3 1 and accept My code word from the output of the linear receiving unit 29 through the element I 31 enters the input of point 28. The synchronization signals from the first output of the clock receiving unit 32 are fed to the inputs of the generator 43 of pulses.

Claims (1)

Invention Formula An apparatus for transmitting and receiving information, comprising, on the transmitter side, a first transmission point, including a pulse generator, the output of which is connected to the clock inputs of the adaptive switch, whose information output is connected via a signal encoder to the first input of the transmitter, the priority outputs of the adaptive switch connected to the encoder inputs of the channel number, the output of which is connected to the second transmitter input n to the input of the channel number decoder, the outputs of which are connected 0 5 О Q five five Q With the control inputs of the adapter switch, the information inputs of which are the information inputs of the device, on the receiving side is the first receiving point that includes the receiver, the first output of which is connected to the information inputs of the keys through the signal decoder, the outputs of which are connected to the first inputs corresponding memory blocks, the outputs of which are connected to the inputs of the corresponding filters, whose outputs are the outputs of the device, the second output of the receiver is connected to the input of the channel number decoder, the moves of which are connected to the control inputs of the keys, the output of the pulse generator is connected to the second inputs of the memory blocks, characterized in that, in order to increase the information content, the second transmission point, the first and the second shift registers, the synchronization unit, the first and the second elements III, the first and second elements AND, the first and second elements AND-NOT, the inverter, the trigger, the linear transmitting unit, the transmitter outputs of the first and second transmission points are connected to the first inputs of the first and second respectively The first output of the first shift register is connected to the first input of the first element, whose output is connected to the first shift register. m input of the first element OR, the output of which through the linear transmitting unit is connected to the communication line, the first output of the synchronization unit is connected to the second inputs of the first and second register-shift, the output of the last is connected to the first input of the second element AND, the output of which is connected to the second input of the first element 1, the third input of which is connected to the second output of the synchronization unit, the third output of which is connected to the inputs of the generator of shu-pulses of the first and second transmission points, the second outputs of the first shift register are connected The inputs to the inputs of the second OR element, the output of which is connected to the first input of the first AND-NOT element and through the inverter, to the first input of the second AND-NOT element, the output of which is connected to the first input of the trigger, the output of which is connected to the TMRM - the house of the element And, the output of iiepHc.ir. II IOMTH-AND-NOT connected to the second-iy of the trigger trigger, the second output of which is connected to the second input of the first AND element, the fourth output of the synchronization unit is connected to the second inputs of the first and second elements of the IS-NOT, the fifth and sixth outputs of the block synchronization is connected to the third inputs of the first and second shift registers, respectively, the second receiving point, the first and second elements AND, the trigger, the first and second AND-NOT elements, the inverter, the clock receiving unit, the linear receiving unit, the first output of which connected with the first inputs of the first and second elements AND, with the first input of the first element AND-NOT and through the inverter with the first input of the second element AND-NOT, the outputs of the first and second elements AND-NOT are connected to the trigger inputs, the first and second outputs of which are connected to the second inputs, respectively, of the first and second elements I, the outputs of which are connected to the inputs of the receivers, respectively, of the first and second receiving points, The second output of the linear receiving unit is connected to the input of the sync pulse receiving unit, the first output of which is connected to the second inputs of the first and iBToporo I-NE elements, the second output of the clock receiving unit Connected to the inputs of the generators of the first and second receiving points, the input of the linear receiving unit is connected to the communication line. Editor O. Golovach Compiled by M. Artamonov Tehred A. Kravchuk Proofreader M.Samborsk Order 6762/52 Circulation 518 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 111055, Moscow, Zh-35, Raushsk nab. 4/5 Subscription