SU1506584A1 - Device for asynchronous switching of digital signals - Google Patents

Abstract

The invention relates to radio engineering and communications. The purpose of the invention is to improve the accuracy of switching by eliminating symbol slippage. The device contains N counters 1 time channels, N registers 2 incoming channels, N blocks 3 of the memory of addresses, N registers 4 of information, block 5 of control. The goal is achieved by introducing into the device N blocks 6 primary memory, N blocks 10 secondary memory, N blocks 7 rewriting controls, N blocks 8 comparisons, N inverters 9 and the counter 11 addresses. To prevent slippage, which is unavoidable on an asynchronous network, for the time of the telephone conversation, information is stored in blocks 6 for a time interval of half the cycle of the PCM paths, and then this information is read and rewritten into blocks 10, of which then it is read in accordance with the cycle of PCM 30/32 paths and is sent to outgoing lines or to other links of switching systems. 1 il.

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The invention relates to radio engineering and communications and can be used in digital switching systems.

The aim of the invention is to improve the accuracy of switching by eliminating symbol skipping.

The drawing shows the structural electrical circuit of the device for asynchronous switching of digital signals.

The device contains N counters 1 time channels, N registers 2 incoming channels, N blocks 3 memory addresses, N registers 4 information CIs, control block 5, N primary memory blocks 6, N rewriting control blocks 7, N blocks 8 comparison, N inverters 9, N blocks 10 of the secondary memory and the counter 11 addresses.

The device works as follows.

Switched digital PCM signals transmitted via incoming links are sent to registers 2, where they are converted from a serial code to a parallel one. In addition, each register 2 consists of two shift registers, one of which converts the signals of even time channels (O, 2, 4, ... 30) of the paths HKM 30/32, and the other - the odd channels (1, 3, 5,. .. 31). Next, the switching PCM signals are recorded on the registers 4 information.

Counters 1 determine the channel numbers in which the switching signals are transmitted. When recording signals to registers 4, the numbers of their time channels from counters 1 arrive in blocks 3, which have one memory cell for each time of the channel, the numbers of which correspond to the numbers of memory cells. When establishing connections, the L addresses of the outgoing channels with which the corresponding incoming channels commute are written to these memory cells. Thus, when incoming channels are received from counters 1, blocks of address memory 3 transform addresses of incoming channels to addresses of outgoing channels and issue them accompanied by a signal from 1 to registers 4. At the same time, registers 4 have PCM switched signals recorded, addresses outgoing channels to which PCM signals are to be transmitted, and

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The signals (1, These signals send 11S1 1 in the memory cell of the block 3 when establishing connections. They ensure the passage of the switched signals through the block 5. When the channels are disconnected, the signals in the corresponding memory cells of the block 3 are written (O 0.

The considered mechanism for transmitting switched PCM signals from registers 2 to blocks 6 is asynchronous, in which switched signals coming from different PBXs with a gradual divergence of the frequencies of the generator of these PBXs with the frequency of the generator of the receiving station are serviced by different clock pulses. The asynchronous mechanism consists in the fact that as the channels of the incoming lines move in time relative to the serving cycles, these channels are serviced with new and new cycles, i.e. switched information slides along clock pulses.

In order to prevent slippage, which is unavoidable on an asynchronous network, for the time of the telephone conversation, information is stored in blocks 6 for a time interval of half the cycle of the PCM paths, and then this information is copied and rewritten into blocks 10, from which is then read out in accordance with the operation cycle of the PCM 30/32 paths and output to the outgoing communication lines or to other links of the switching systems.

The moments of rewriting information from blocks 6 to blocks 10 are stored in the memory cells of the blocks / in which they are recorded when connections are made using signal 1. In this case, connections are made in two stages. At the beginning, at the first stage, the control input to blocks 3 receives the addresses of the incoming and outgoing channels switched together, accompanied by the signals O (1 and v 1, Blocks 3, write the addresses of the outgoing channels and signals 0 1 to their respective cells) Then, in the second stage, similarly, after a time interval T 125 of the ISS, the addresses of the same outgoing

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Signal 1 is read from blocks 3 and goes along with the information (as shown) through register 4 and block 5 to block 7, in which it writes to the memory cell of this block at address A, transmitted together with signals y and dj 1, (addresses) of time channel A from counter 11. In this case, the most significant bit of recorded A is inverted by inverters 9. Blocks 6, 7, and 10 are the same in the number of memory cells assigned to the downstream time channels. Blocks 6 and 10 provide storage of switched signals; and block 7 — numbers A of time channels, at times of which it is necessary to rewrite these signals from blocks 6 to blocks 10,

Blocks 6, 7, and 10 over a period of time equal to f + t ° (the time of operation of block 5 and the group path) record information received at their inputs to the recording cycle and read information to the cycle

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For the time interval equal to the duration of the time channel of the PCM paths, all the memory cells of blocks 6 and 7 are read. The read information is recorded in blocks 6 and 7 and then goes to blocks 10. At the same time, information from blocks 6 is transmitted directly to blocks 10, and information from blocks 7 is transmitted to blocks 8, in which it is compared with the address Ag from counter 11. Comparison produces signal 1, which arrives at blocks 10 and provides information overwriting from block 6 to blocks 10. All clock signals and generate

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Information is recorded in blocks 6 in time f jri provided 1, in blocks 7 - in time

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The reading of information from blocks 6 and 7, carried out in tact f, and the rewriting of information in block 10, carried out in tact f, are made but to the same address for rewriting A, from counter 11. Each

The new address A is stored at the outputs of the counter 11 for a period.

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A device for asynchronous switching of digital signals containing N time channel counters, N registers of input channels, N information registers, a control unit and N address memory blocks, to the first inputs of which the outputs of the corresponding time channel counters are connected, N outputs registers of incoming channels are connected to the first inputs of the corresponding information registers, the second inputs of which are connected to the address outputs of the corresponding N memory blocks of addresses, and the first outputs of the N information registers are connected to N first in The steps of the control unit, the N first outputs of which are connected to the first control inputs of the corresponding N information registers, is characterized in that N blocks of the primary memory, N blocks of the secondary memory are entered to increase the switching accuracy by eliminating the scrolling of the characters . N rewriting control units, N comparison units, N inverters and an address counter, the second output of the control unit being connected to the first inputs of the N rewriting control units and N primary memory blocks, the first outputs of which are connected to the first inputs of the corresponding N secondary memory blocks, the second inputs of which through the corresponding N comparison blocks are connected to the outputs of the corresponding N rewriting control blocks, the second inputs of which are combined with the third inputs of the corresponding N blocks of the secondary memory and the second inputs s of the corresponding N comparison blocks and are connected to the first output of the address counter, the second output of which is connected to the combined address inputs. N primary memory blocks, N rewriting control blocks and N secondary memory blocks, and N inverters connected between the first output of the address counter and additional inputs of the corresponding N rewriting control blocks.

Claims (1)

Claim Device for asynchronous switching of digital signals, containing N time channel counters, N input channel registers, N information registers, control unit and N address memory blocks, the first inputs of which are connected to the outputs of the corresponding temporary channel counters, the outputs of N input channel registers are connected to the first inputs corresponding information registers, the second inputs of which are connected to the address outputs of the corresponding N address memory blocks, and the first outputs of N information registers are connected to the N first inputs a control unit, the N first outputs of which are connected to the first control inputs of the corresponding N information registers, characterized in that, in order to improve switching accuracy by eliminating slippage of characters, N primary memory blocks, N secondary memory blocks, are introduced. N rewrite control units, N comparison units, N inverters and an address counter, while the second output of the control unit is connected to the first inputs of N rewrite control units and N primary memory blocks g, the first outputs of which are connected to the first inputs of the corresponding N secondary memory units, the second whose inputs, through the corresponding N comparison blocks, are connected to the outputs of the corresponding N rewriting control blocks, the second inputs of which are combined with the third inputs of the corresponding N secondary memory blocks and the second inputs are connected to the first output of the address counter, the second output of which is connected to the combined address inputs. N primary memory blocks, N rewrite control blocks and N secondary memory blocks, and N inverters are connected between the first output of the address counter and the additional inputs of the corresponding N rewriting control units.