SU1429105A1 - Information input/output device - Google Patents

Abstract

The invention relates to the field of computer technology and can be used for organizing the exchange between an EPM and a peripheral device. The purpose of the invention is to simplify the device and expand the scope by introducing an additional external synchronization mode. The device comprises a conjugation unit 1, a control unit 2, a shift register 3, a driver of the 4 request signals, a key block 5, a driver of the 6 addresses, a driver of the 7 signal of the end of the message. The device allows organizing the exchange of information in the mode of direct access to the memory between the computer and the subscriber transmitting and receiving information in the form of consecutive binary codes. The conversion of parallel codes to consecutive and inverse transforms performs register 3 shift. The exchange is effected by a signal Service Request Device. After the computer responds to the request with an exchange enable signal, the direct memory access address and the write-read signal generated by the driver 6 are output to the computer channel. This procedure is performed by DD1I of each word of the information message. 2 hp f-ly, 5 ilJ (L

Description

ND

WITH

The invention relates to a computational technique and can be used to organize an exchange between a computer and a peripheral device.

The purpose of the invention is to improve the device and expand the field of application by introducing an additional mode of external synchronization. A: Fig, 1 np medena functional device diagram; in fig. 2 - functional scheme of the interface block; in fig. 3 — func tional; ional circuit of the control unit; in fig. 4 is a functional diagram of the request signal generator; in fig. 5 is a functional diagram of the address driver i. In FIG. 1 denotes a matching unit 1, a control unit 2, a shift register 3 and a driver. 4 signals janpoca, 5 key block, fipper and 6 addresses, shaper 7 signal of the end of the message, inputs and outputs 8-20 of the device and blocks.

FIG. 2 designates the pulse former 21, the AND 22 element, the first YPI 23 element, the second AND 24 element, the first trigger 25, the third element and 26, the second OR element 27, the second trigger 28, the first output 29, the second output 18, the third output 30 and fourth output block 31.

FIG. 3, the synchronization circuit 32 is indicated, the AND element 33, the OR elements 34 and 35, the counter 36, the disinfector 37, the first 38 and the second 39 outputs.

FIG. 4 designates the one-shot 40, the trigger 4 entries, the first and second elements OR 42 and 43, the reading trigger 44, the first element AND 45, the third and fourth elements OR 46 and 47, the delay elements 48 and 49, the request trigger 50, the second and third elements 51 and 52, the first output 14, the quarter output 53, the second output 54, the fifth output 55, the third output 56 of the inquiry signal generator.

FIG. 5, the counter 57, keys 58, the outputs 59 of the second group, the outputs 16 of the first group and the output 19 of the address generator are indicated.

The device works in a clean way.

In the initial state, when the device does not enter or. the output of information, on information inputs 15, address inputs 16 and output 19, the third state (state

Jq 15 20

25 30

dd

35

five

0

five

high output impedance).

Consider the operation of the device in the information input mode. Peripheral device outputs a single input signal to input 9 of this device. Upon the arrival of this signal, the pulse shaper 21 of the conjugate 1 produces a single pulse, which triggers the trigger 25 through the OR element 23, and triggers the recording trigger 41 in the block 4 through its output 30. As a result, a single input resolution signal is output to the control output 18 of the switch to organize the input of the first word of the informational message from the peripheral device. Having received this signal, the peripheral device starts to output information in the form of a sequential code to the information input 8 of this device. A single signal formed at the input 18 affects the third input of the control unit 2, through the elements AND 33, OR 34 and 35 and the output 39 of which pass the clock pulses. These clock pulses arrive at the C input of the 3-shift register and record the bits of the specified information. At the same time, the clock pulses begin to fill in the counter 36 of block 2, which is tuned to the length of one information signal. After receiving one word of information, the counter 36 is processed, as a result of which, a single pulse signal is extracted at the output 38, which enters the interface 1 and resets the trigger 25 to the zero state via the OR 27 element. Thereafter, a single signal is removed from the output 18, which prohibits the peripheral device from outputting information on the input 8 of this device. In control block 2, the clock pulse passes through the AND 33 element. A single pulse signal from the output 38 is sent to the fourth input of the driver 4 request signals, in which through the element 45 and OR 47 switches the trigger 50 of the request to one state. At the output of this trigger, a single service request signal is generated, which is switched to the output 14 of the device. After that, the device is in standby mode;

until a single pulse of exchange resolution is received from the computer to the device input 12. Upon arrival of this signal in block 4, the request trigger 50 is reset to the zero state, and element 51 is triggered. As a result, a single request signal is removed from control output 14, and at output 56 a single signal is generated (for the duration of the exchange enable signal) which arrives at the control input of the block of 5 keys and outputs it from

the output 20 of the device for removing the input signal from the peripheral device to the input 9 of this device. After this, the device returns to its original state. Thus, the proposed device, each time after receiving one word of the information message, generates a request signal and, upon receipt of an authorization signal, transmits information to the computer. The reception of the next word of the information message is made only after receiving a permit from the computer.

The third (high-impedance) state - j of the sending signal for removal of the previously received signal; as a result, information signals are formed at the output of this block.

The single exchange enable signal from the input 12 enters the address generator 6 and into the interface 1 unit. In block 6, it uses the counter 57 of keys 58 to generate an address code that commutes (for the duration of this signal) to the address outputs 16 to determine the computer memory cell into which the information formed at the outputs of the keys 5 should be written. The keys 57 upon the arrival of the exchange enable signal commutes to the output 19 of the control single signal Record allowing the recording of information into the computer memory at the address indicated.

In block 1, the single exchange enable signal through the elements AND 22 and OR 23 switches the trigger 25 to the single state, as a result of which a single signal is switched again to the output 18 of the device to continue organizing the next word retrieval of the information message from the peripheral device. In this case, blocking is removed from AND 33 of control unit 2, and therefore the clock pulses begin to fill counter 36 again and pass to the C input of shift register 3. In the future, the operation of the device for receiving and entering the next information word proceeds in a similar way. After the last word of the information message has been entered into the computer memory, the end of exchange signal will be generated at the output of the imaging unit 7 of the signal for the message. This signal zeros the shift register 3, the conjugation block 1, the driver of the 4 request signals, the driver of the 6 addresses and is switched to

0

five

0

five

that word. The information word is written into the corresponding cell of the computer memory at the address that is allocated by the exchange enable signal at the outputs 16. In this case, a single signal is generated at the output 19, which determines the mode of recording information in the computer memory.

Consider the operation of this device when displaying an information message from a computer. In this case, a single output signal arrives at the device input 13. In block 4, this signal enters the one-shot 40, which produces a single pulse. The latter, through the OR element 42, switches the read trigger 44 to the single state, as a result of which, at the output 55, the zero signal is replaced by a single N. This makes it possible to produce parallel recording of information in register 3 and select, with the help of block 6, the desired memory zone to be accessed. After the read trigger 44 is switched to one state, OR 46 and 47 elements are switched to one state and request trigger 50. As a result, a single service request signal is switched to the device output 14. In response to this request on. The device input 12 is output from the computer by a single pulse signal for exchanging the signal. In block 6, this signal changes the state of counter 57, which is transmitted via keys 58 to address outputs 16. At the same time, a zero signal is switched to output 19, which determines the read mode for the memory cells of the computer. Using the generated 5 address code, the first information word is read from the corresponding computer memory cell, which is fed to the information

0

five

0

514

inputs 15 in the form of a parallel code. This information is written to the shift register 3 according to the exchange enable signal, which, having passed delay element 49 and AND element 52 in block 4 and OR element 35 in block 2, affects the C input of this register. The exchange enable signal in block 4 resets the query trigger 50 to the zero state, and after delaying the delay elements 49 and 48 and the OR element 43 flushes the trigger trigger 44 to the zero state. At the output 53, the single signal changes to zero, in, resulting in the shift register 3 ready for sequentially issuing the bits of the information received from the computer, to the information output 17. The exchange enable signal in block 1 through the element 26 switches the triggers - Iger 28 in one state. At output | 29, a single signal is formed, which, in control unit 2, triggers synchronization circuit 32. The latter is intended to tie in the external clock pulses fed to the input 10 to the clock pulses. At the output of this circuit, synchronization pulses are extracted, which through the ILG element 34 fill counter 36, and through the element OR 35 and output 39 arrive at the C input of the shift register 3. Thus, with the frequency of external clock pulses in this register, the recorded information is shifted, which from the output of the last bit as a sequential code goes to information output 17. After issuing the first word of information, the counter 36 is processed in block 2, as a result of which a single impulse signal is generated. This signal in block 1. through the element OR 27 resets the trigger 28 to O, and through the element 24 (in the absence of a second input signal at its second input) from the bus 9) passes to output 31. Next, the specified signal enters block 4 and through it the OR 42 element closes the read trigger 44 into one state, which in turn leads to the trigger one request switch 50. In the future, the operation of the device for outputting the next information word proceeds in a similar way. After completion of the last word output of the informational message at the output form

Q 0 5 5 0 5

0

0

056

The message end signal body 7 forms a single pulse signal of the end of the exchange. This signal zeros the shift register 3 and the memory elements in blocks 4 and 6 and is switched to the output 20 of the device for removal. the output signal from the computer to input 13. After that, the device returns to its original state. Thus, the proposed device, after reading the information word from the computer memory, sends it to the communication channel in the form of a sequential code. After issuing the next word of information, it forms a request for service. The reading of the next word is made only after receiving a signal from the computer to open the exchange. In this case, the waiting time for reading the next word should be less than one period of the following clock pulses, arriving at the input 10 of the device. Reading the information layer from the corresponding computer memory cell is performed using the address code that is generated on buses 16. In this case, the device switches a zero signal to its control output 19, which sets the EV memory cells.

Thus, the proposed device allows the exchange of direct memory access for the subscriber transmitting and receiving information in the form of consecutive binary codes. The conversion of parallel codes to serial and serial to parallel when outputting and entering information produces the same shift register. During the output, the output information is synchronized externally.

Claims (3)

1. A device for input-output information containing a shift register, a key block, a control block and an address generator, the outputs of the first group of which are the device's address outputs, the outputs of the key block are information outputs of the device group, information. the input of the shift register is the information input of the device, the first input of the control unit is the clocking input of the device, characterized in that 714 simplifying and expanding the application area by introducing an additional external synchronization mode, the device contains a interface block, a signal end message generator, the output of which is connected to the first inputs of the request signal generator, the address generator, the interface block, the shift register reset input and is the end output device exchange, the second input of the interface module is the input input of the device input, the third input of the interface module is combined with the second inputs of the address generator and the forms The request signal body is the device exchange enable input, the fourth input of the interface block is combined with the third input of the request signal generator and is the input output resolution of the device, the first output of the interface block is connected to the second input of the control unit, the first output of which is connected to four - the fifth input of the interrogation signal generator and the fifth input of the interface block, the second output of which is connected to the third input of the control unit and is the output of the input resolution of the device, the third and fourth outputs the interface block is connected respectively to the fifth and sixth in the request signal generator, the first output of which is the device service request output, the second and third outputs of the request signal generator are connected respectively to the third input of the address generator and the control input of the key block, the fourth output the request signal generator is connected to the write register write enable of the shift register and the fourth input of the address generator, the output of which is the device write / write output, the fifth Exit request signal shaper is connected to a fourth input of the control unit, fifth input of which is input an external locking device, the second output of the control unit is connected to a strobe input of the shift register, the installation whose inputs are information. the inputs of the device group, the output of the shift register are connected to the information inputs of the key block, the output of the higher bit of the shift register is information, the output of the Q jn 5 5 0 5 0 0 058. The outputs, the second group of the address resolver, are connected to the inputs of the end-of-message signal compiler. 2, The device according to claim 1, about tl and - tea-to-others, in that the interface unit contains two triggers, a pulse shaper, two elements OR and three elements And, the first input of the first element And combined with the first input of the third element And is the third input of the block, the second input of the first element And is combined with the first input of the second element And, the input of the pulse shaper, the D input of the first trigger and is the second the input of the block, the output of the first trigger is the second output of the block, the output of the first element AND is connected to the first input of the first OR element, the output of which is connected to the C input of the first trigger, the output of the pulse shaper is connected to the second input of the first element This OR is the third output of the block, the first input of the second element OR is the first input of the block, the second input of the second element OR is combined with the second input of the second element AND, and is the fifth input of the block, the output of the second element AND is the fourth output of the block the output of the second element OR is connected to the R inputs of the first and second triggers, the second input of the third element I is the fourth input of the block, the output of the third element I is connected to the C input of the second trigger, the output of which is the first output of the block 3. The device according to claim 1, that is, so that the request signal generator contains a single vibrator, four OR elements, three AND elements, two delay elements, a recording trigger, a read trigger, and a request trigger. the output of which is the first output of the driver, the R input of the recording trigger is combined with the first input of the second element OR and is the first input of the driver, the R input of the request trigger is combined with the first input of the second element AND, the input of the second delay element and is the second input of the driver, the input of the one-oscillator, the first input of the first element AND, the S input of the recording trigger and the first input of the first 11PIs are the third, fourth, fifth and sixth inputs, respectively. The former, the output of the recording trigger, is fedinen with the second input of the first element AND, the first input of the third element OR, the second input of the second element AND, and is the second output of the ph | em, the output of the second element AND, is the third output of the p | ovatel, the output of the one-vibrator HiCH with the second input of the first element | a OR, the output of which is connected to the C input of the read trigger, the output of which is connected to the first input of the three element AND, the first input of the fourth element OR, the second input of the third element OR is even (rig. The twist output of the driver, the output of the first element AND is connected to the second input of the fourth element OR, the output of which is connected to the C input of the request trigger, to the D input of which the output of the third element OR is connected, the output of the second delay element connected to the second input of the third element AND and input the first delay element, the output of which is connected to the second input of the second OR element, the output of which is connected to the R input of the read trigger; the output of the third AND element is the FIVE1-1 output of the driver. 9g.Z