SU1411979A1 - Code to code translator - Google Patents

Abstract

The invention relates to computing and can be used in devices for processing digital data. The invention allows, without additional hardware costs and changing the structure of the device, to convert parallel codes of arbitrary type, which ensures the expansion of the area of use of the converter. The converter contains a counter of I pulses, two blocks 2 and 4 of memory, block 3 of comparison of codes and block 5 of control consisting of four trigs. geers, four elements, a decoder, a pulse counter and a pulse generator. 2 Il.

Description

OE

ss

Phage.1

The invention relates to computing technology, in particular, to information converters, and can be used in devices for processing digital data.

The purpose of the invention is to simplify the pre-processor and expand its use by the possibility of converting parallel codes of any kind.

FIG. 1 shows a block diagram of a parallel code converter; in fig. 2 - functional block diagram.

The parallel code converter contains a pulse counter 1, a first memory block 2, a comparison block 3, a second memory block 4 and a control block 5, input 6 and output 7.

The control unit 5 consists of the first, second, third and fourth triggers 8-P, the first, second, third and fourth elements AND 12-15, the decoder 16, the pulse counter 17 and the pulse generator 18. FIG. 2 positions 19-22 and 23 denote the first, second, third, fourth outputs and the input of the control unit 5

Blocks 2 and 4 of the reprogram memory-30 impulse N1 is formed by the front

Rule: e permanent memory device (memory). In block 2, all possible input codes are written, in block 4, the corresponding output codes are written to the same addresses.

. Counter 1 generates the addresses of block 2 and block 4.

i Block 5 generates a signal: control elements of the converter, so the decoder 16 under the influence of the generator 18 and the counter 17 sets the duration of the control signals of the block 2 and block 4 and generates the clock pulses for the counter 1 and the triggers 8 and 9, which form the signals (MF) and chip select (BK) for blocks 2 and 4. Elements And 12 and 14 form the signals MF and BK for. block 2, and the elements And 13 and 15 form signals MF and VK for block 4.; At the outputs of the elements And 12 and 14. Control signals (readings) of block 2, respectively, MF and VC, are formed.

At the outputs of the elements. And 13 and 15, control signals are generated (reading block 4, MF and VC respectively):

The Converter operates as follows.

When applying the current value of the input code to the code comparison unit 3, the control unit 5 at the output of the decoder 6 generates clock pulses (TI) for counter 1, and at the outputs of elements 12 and 14, the control (read) signals of block 2: pulse generator 18, counter 17 and the decoder 16 organizes pulses that specify the duration of the control signals of blocks 2 and 4, and the triggers 8 and 9 form these signals and, with the resolution from trigger 10, the signals of the midrange and VK from elements 12 and 14 are fed to the control input of block 2.

To generate the signals of the MF and VC units 2 and 4, four pulses N1, N2, N3 and N4 from the decoder 16 are needed, which would provide the specified temporal ratios of the signals MF and VC reflecting the specific features of the element base and operating modes of the converter.

The N1 and N4 pulses are used (for

five

0

five

0

five

front midrange, and the pulse N4 rear front). The N2 and N3 pulses participate in the formation of the VK signal (the leading edge of the VK is generated from the N2 pulse, and the falling edge from the N3 pulse).

The N4 pulse determines the end of the read cycle, and it also triggers the triggers 10 and 11 and the counter 17 of the control block 5.

In addition, the VC signal of block 2 is a gating pulse (GATE) for comparison unit 3, which allows comparing the codes to block 3. The VC signal of unit 2 confirms the start of block 2 in the absence of code equality at block 3 of the code comparison.

Counter 1 sequentially switches the memory cells of block 2, starting with the first one, and at comparison block 3, each code value read from block 2 is compared with this input code until these codes are equal (control block 5 each time -with a new address of block 2 generates signals SC and VK of block 2).

In the case of equality of codes in block 3, the comparison by the signal Equality

the control unit 5 at the output of the elements 13 and 15, according to the resolution from the trigger 11, generates the signals: MF and VC of block A (similar to the signals of MF and VC of block 2). The output information from block 4 is read at the address equal to the address of block 2 at the moment of equality, i.e. For a given input code, a new code is generated at the output of the converter — the result of the conversion.

Claims (1)

Invention Formula A code converter into a code containing a pulse counter, the outputs of which are connected to the address inputs of the first memory block, characterized in that, in order to simplify the converter and expand its use area due to the possibility of converting parallel codes of arbitrary type, a code comparison block is inserted into the converter, the second memory block and the control block containing the triggers, the elements AND, the decipher, the pulse counter and the pulse generator, the output of which is connected to the information input of the pulse counter, the output of which is connected to the input of the decoder, the outputs of which are respectively connected to the first and second inputs of the first and second flip-flops, the output : the first trigger is connected to the first inputs of the first and second elements And, the output of the second trigger is connected to the first inputs of the third and fourth elements And, the third output of the trigger is connected to the second inputs of the first and third elements And, the fourth trigger output is connected to the second inputs of the second and fourth elements And, the second input of the first trigger is combined with the first inputs of the third and fourth triggers and with the installation input of the pulse counter of the control unit, the outputs of the first to the third And elements are connected to the control The first inputs of the memory block, the outputs of the second and fourth elements I are connected to the control buttons of the second memory block, the second input of the third trigger is connected to the output of the third element I and combined with the input gate of the code comparison unit, the output of which is connected to the second input the fourth trigger, the output of the first block: the memory is connected to the first input of the code comparison block, the address input of the second memory block is connected to the output of the pulse counter, the input of which is combined with the first input of the first trigger of the control unit ION r a second input of the comparator is input to the code converter, taken the analysis of the second block memory is output transducer. Thebes. 2