SU1485387A1 - Time interval extremum meter - Google Patents

Description

The invention relates to the field of measurement technology and can be used to measure extremal2

values of time intervals in digital measuring devices and systems. The purpose of the invention is to improve the measurement accuracy and reliability for the expense of simplification. The device contains registers 1, 2, blocks 3, 4 of the display, blocks 5, 6 comparison, counter 7, block 8 synchronization, block 9 start, elements And 10, 13, 14, generator 11 clock pulses, trigger 12. The execution of the element And 14 with an open collector, by reducing the quantization interval, it is possible to increase the measurement accuracy, which is especially important when measuring the minimum values of time intervals, since in this with

In the case of a quantization error, there is more. 2 hp f-ly, 2 ill. R

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1485387-A1

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1485387

The invention relates to reference measurement 5, .a output connected to

and can be used to measure extreme values of time intervals in digital instrumentation and systems.

The aim of the invention is to improve the measurement accuracy and reliability by simplifying. ten

FIG. 1 is a block diagram of the device; in fig. 2 - timing diagram of the device.

A device for measuring the extra-: · Mums of time intervals contains 15 first 1 and second 2 registers, first 3 and second 4 indication blocks, first 5 and second 6 comparison blocks, counter 7, synchronization block 8, start block 9, first element 10 The generator is a 20 torus 11 clock pulses, a trigger 12 and a second element And 13, a third element And 14, which is designed as an element And with an open collector.

The device contains the first I and. 25

the second 2 registers, the outputs of which are connected to the inputs, respectively. the first and second display units and the first inputs, respectively, of the first 5 and second 6 comparison units, ‘30 whose second inputs are interconnected and connected to the first inputs of registers 1 and 2 and to the counter outputs!

7, the first input of which is connected to the first input of the starting unit 9, the second '35 input is connected to the first output of the synchronization unit 8 ,. and the third input is connected to the output of the first element 10, the first input of which is connected to the output of the generator, and there are 49 pulses and the first input of the synchronization unit 8, and the second input is connected to the first output of the trigger 12, the second output of which is connected to the second input of the unit 8 synchronization, the first _L 45 input is connected to the first input of the starting block 9 and the device input, and the second input is connected to the second output of the synchronization block 8, the third input of which is connected to the second output of the starting block 9, and the third output is connected to the second input of the starting block 9 ka and the first input of the second element I 13, the second input of which is connected to the output of the second comparison unit 6, $$ the first input of the element 14 with an open collector connected to the third output of the synchronization unit 8, the second

the input is connected to the output of the first second input of the first register-1 and the third output of the starting block 9, the third input of which is connected to the first output of the synchronization block 8, and the output of the second element And 13 is connected to the second input of the second register 2.

The synchronization unit 8 comprises a trigger 15, an AND 16 element and an OR element 17. The first input of the trigger 15 is connected to the first input of the synchronization unit 8 and the first input of the AND 16 element, the second input is connected to the second input of the synchronization unit 8, the third input is connected to the output of the OR element 17 and the second output of the synchronization unit 8, the first output is connected to the third output of the synchronization unit 8, and the second output is connected to the second input of the AND element 16, the output of which is connected to the first output of the synchronization unit 8 and connected to the first input of the OR element 17, the second input D which is connected to the third input of the synchronization unit 8.

The start block 9 contains the first 18 and second 19 triggers, the "Reset" button 20, element 21 and an open collector and resistor 22. The first output of the first trigger 18 is connected to the first output of the start block 9, the second output is connected to the second output of the block. 9, the first input is connected to the first input of the starting block 9, and the second input is connected to the Reset button 20 and the first input of the second trigger 19, the second input of which is connected to the third input of the starting block 9, and the output is connected to the first input of the AND element 21 with an open collector, the second input of which is connected to the second input of the starting block 9, and the output is connected to the third output of the starting block 9 and the first output of the resistor 22, the second output of which is connected to the positive power supply output (not shown).

FIG. 2. Accepted the following notation: a - impulse from the output of the "Reset" button 20; {G - measured pulse train; B - generator output 11 clock pulses;

Ί - The first output of the launch block 9;

- trigger output 19; b - the first

trigger output 12; F - output of the first

element and 10; the third output of the synchronization unit 8; And - the first exit

block 8 sync.

5 1485387

The device works as follows

In the initial state, after pressing the "Reset" button 20, the triggers 18 and 19 of the starting block 9 are set to one (Fig. 2.2, ^). The level of the logical unit from the first output of the trigger 18 arrives at the first input of the counter 7, and thus, for - -, θ stops its operation. From the second ^ inverse) output of the trigger 18, the logical zero level through the OR element 17 enters the second input of the trigger 12, setting it to the single state (15, e), and to the third input of the trigger 15, setting it to the zero state (Fig. 2, d).

A single signal level from the output of the trigger 12 is fed to the element 20

And 10 and allows the passage through it of pulses having the form of a meander, from the output of the clock generator 11 to the third input of the counter 7 (Fig. 2, g), which, however, does not switch, since it is kept in the zero state by a single signal level at its first the entrance (Fig. 2.2 ·). At the second input of the counter 7 at this time, the level of the logical unit is set (Fig. 2, c). A single signal level from the output of the trigger 19 (Fig. 2, ^) keeps the element 21 with an open collector in the unlocked state.

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When the first positive edge of the measured period arrives at the device input (Fig. 2.8 "), the trigger 18 switches to the zero state (Fig. 2.2). At the same time, the zero level of the signal received at the first input of the counter 7 permits his work and he starts counting the measured period from zero. Counter 7 switches over each positive front of the pulses of the clock generator 11, coming through the element And 10 (Fig. 2, g).

At the same time, the zero level of the signal is removed from the second input g _{0 of the} trigger 12, allowing its switching to the zero state. However, the first pulse of the measured period trigger 12 does not have time to switch to the zero state, since the removal of 55 blocking from the second input of trigger 12 occurs with some delay relative to the positive front of the input signal, due to the natural delay of the signal at the trigger time of trigger 18, the element OR 17 and trigger 12.

Since the trigger 12 does not switch over the first pulse of the measured period, the synchronization unit 8 does not start and the reset and strobe pulses, respectively, on the first and third outputs of the synchronization unit 8 are not generated.

After the arrival of the second positive pulse front of the measured period (Fig. 2, £), the trigger 12 switches to the zero state (Fig. 2, e) and thus prohibits the passage of the next pulse from the clock generator 11 through the element 10 (Fig. 2, f ) on the counting input of the counter 7.

With the arrival of the nearest positive edge of the pulse of the clock generator 11, the trigger 15 switches to one state, which is transmitted to the third output of the synchronization unit 8. The zero signal level at this moment from the second output of the trigger 15 acts on the second input of the AND element 16, which is a coincidence circuit for zero levels of logic signals. At the moment of transition of the pulse clock generator 1 1 to zero, the zero levels of the signals at the inputs of the element 16 coincide, the output of which sets the level of logical zero, which passes through the element OR 17, and acting on the third input of the trigger 15, sets it to the zero state. Thus, after the receipt of the second positive front of the pulse of the measured period, the synchronization unit 8 provides for the generation of strobe and reset pulses at its third and first outputs, respectively.

The first comparison unit 5 is constructed in such a way that if the binary number in the counter 7 is less than the binary number in the first register 1, then the output of the comparison unit 5 is set to the level of the logical unit, otherwise the output of the comparison unit 5 will be the logical zero level. The second block 6 of the comparison is constructed in such a way that, if the number in the counter is 7 · more than the number written in the second register 2, then its output is

one . 1485387 ' ⁸

Do set the level of the logical unit, otherwise the output of the second block 6 comparison will be the level of the logical .. zero.

The reset pulse arising at the third output of the synchronization unit 8 at the moment of arrival of the second positive edge of the measured period impulse arrives at the input of the element IU 21 with an open collector, which at this time still remains unlocked by the level of the logical unit coming from the output of the trigger 19. through it, the pulse 15 of the gate enters the gate input of the first register 1 and puts into it the value of the first measured time interval, which is stored in the counter 7. Since initially in the 20 source channel the registers contained all zeros, then on. the output of the second comparison unit 6 in the first measurement cycle will always be the level of a logical unit, because any 25 in the counter 7 is always greater than zero. Therefore, in the first measurement cycle, the strobe pulse passes through the second element I 13 to the input of the second register 2 and records the value of the first 30 measured time interval from the outputs of counter 7. Thus, the result of the first measurement cycle is recorded in both registers at once. ^ 5

After the strobe pulse, a reset pulse appears on the first output of the synchronization unit 8, which sets the counter 7 to the initial state. In addition, the reset pulse, appearing after the second positive pulse of the first measured period, resets the trigger 19 to the zero state, which leads to blocking of the AND 21 element with the open collector and further the passage of the gate pulses to the input of the first register 1 is possible only through the element And 14 with an open collector. The duration of the reset pulse is determined by the delay of the operation of the elements AND 16, OR 17. and trigger 15 and must be selected taking into account the speed of the counter 7. When implementing this scheme, the K155 or K555 series logic elements easily provide a two-fold margin in comparison with the technical requirements for these chips that guarantee their reliable operation. '

The initial state of the counter 7 in each subsequent measurement cycle is the installation of all its bits in the zero state, except the youngest, which is set to one. This installation is necessary to preserve the accuracy of the measurement, since the generation of control pulses by the synchronization unit 8 takes one clock cycle of the generator 11 clock pulses. Since in this case one pulse from the pulse sequence is eliminated ^ FIG. 2, g) _; then this is taken into account when setting counter 7 to the initial state by adding one to the lower order.

When the next positive edge of the measured period arrives, the trigger 12 is set to the zero state, prohibiting the passage of the next pulse of the clock generator 11 to the counting input of the counter 7. The unit signal level from the second output of the trigger 12 goes to the second input of the synchronization unit 8, which starts the strobe pulse generation at its third output and a reset pulse at its first output, as described above.

The strobe impulse arrives at the first inputs of an And 14 element with an open collector and the second element of And 13, which also receives signals from the outputs of the first 5 and second 6 comparison units. Depending on the result of comparing the current measured period with the value of the values previously recorded in the registers, the contents of counter 7 can be overwritten in one of the registers.

If the current measured period is the minimum or maximum of the previously measured, then the gate pulse passes through the open collector element 14 or the second element 13 and enters the gate input of the first 1 or second 2 registers. This rewrites the contents of counter 7, i.e. values of the current measured period, in the corresponding register.

After the strobe pulse should reset pulse used in setting initial states ¹ meter 7 and Trigg ry 12 and 15.

9 1485387

] about

In the future, the process of measuring current time intervals' is repeated, and in each measurement cycle the value of the current time interval is compared with the extreme values stored in the first 1 and second 2 registers. If the current measured period is less than the minimum or greater than the maximum, the value of the current period is rewritten to one of the registers of the corresponding extremum. Otherwise, the contents of the registers do not change.

The measurement accuracy of the device depends on the magnitude of the quantization interval, the reduction of which, or the increase in the frequency of the clock pulse generator, is associated with the following limitation: an increase in the measurement accuracy of 20 "by reducing the quantization interval to the extent that the device can still perform within one such an interval, rewrite the contents of the counter 7 to one of the registers and reset it to its original state. nosti momentum interval clock 30 pulses, wherein the discharge is less critical on speed because performed very narrow pulses. A critical from this point of view, dubbing is ₃₅ informa- tion from the counter 7 to the registers 1 and 2.

But since the recording is made on the positive front of the pulse of the strobe, it is possible to reduce its duration. ₄₀

Thus, the time of rewriting the information of the PB compared to the known is reduced by 20%, and this can significantly reduce the quantization interval and thereby increase the measurement accuracy 45, which is especially important when measuring the minimum values of time intervals, since in this case the quantization error affects more.

Claims (3)

Claim 1. Device for measuring the extremes of time intervals, containing the first and second registers, the outputs of which are connected to the inputs of the first and second display units, respectively, and the first inputs of the first and second comparison units, respectively, the second inputs of which are interconnected and connected to the first inputs the first and second registers and to the outputs of the counter, the first input of which is connected to the first output of the starting block, the second input is connected to the first output of the synchronization block, and the third input is connected to the output of the first elec K, the first input of which is connected to the output of the clock generator and the first input of the synchronization unit, and the second input is connected to the first output of the trigger, the second output of which is connected to the second input of the synchronization unit, the first input is connected to the first input of the start-up unit and the device input, and the second input is connected to the second output of the synchronization unit, the third input of which is connected to the second output of the starting block, and the third output is connected to the second input of the starting block, the first input of the second And element, the second input of which only with the output of the second comparison unit, and to the first input of the third element And, the second input of which is connected to the output of the first comparison unit, characterized in that, in order to improve measurement accuracy and reliability, the element And with an open collector is used as the third element, the output of which is connected to the second input of the first register and the third output of the startup unit, the third input of which is connected to the first output of the synchronization unit, and the output of the second element I is connected to the second input of the second register. 2. Device by π. 1, which is based on the fact that the synchronization unit contains a trigger, an element AND and an element OR, the first input of the trigger is connected to the first input of the synchronization unit and the first input of the AND element, the second input is connected to the second input of the synchronization unit, the third input connected to the output of the OR element and the second output of the synchronization unit, the first output of the trigger is connected to the third output of the synchronization unit, and the second output is connected to the second input of the And element, the output of which is connected to the first output of the synchronization unit and connected to the first input the element OR, the second input 1485387 ¹² which is connected to the third input of the synchronization unit. 3. Device by π. 1, since the starting block contains the first and second triggers, the Reset button, the open collector element I, and a resistor, the first output of the first trigger connected to the first output of the block started the second output connected to the second output the start block, the first input is connected to the first input of the start block, and the second input is connected to the Reset button and the first input of the second trigger, the second input of which is connected to the third input of the start block, and the output is connected to the first input of the I element with an open collector, the second input a second input connected to the start block, and an output connected to a third output of the start and the first terminal of the resistor, a second terminal of which is connected to the positive terminal of the power source.