SU1476521A2 - Method of displaying data on crt screen - Google Patents

Abstract

The invention relates to computing and automation, can be used to display information from a computer, and is an improvement to the device according to the author. St. N 1291956. The purpose of the invention is to increase the speed of the device. The device contains two memory blocks, twelve registers, a symbol generator, a block of permanent memory of symbols, a raster line shaper, a modulation unit, a CRT, a control unit, seven groups of AND elements, a group of OR elements, two groups of inhibition elements, four comparison blocks , decoder, four AND elements, three OR elements, two NOT elements with corresponding links. The coordinates of the corner points of the masked window are brought from the input of the device through groups of elements And in the registers and in the comparison blocks are compared with the current coordinates of the screen beam. At the outputs of the elements, prohibition pulses are NOT formed, which prohibit the passage of video signals through the first and second groups of elements, thereby achieving masking of a part of the image on the CRT screen. The contents of the memory blocks are not violated. 3 il.

Description

one

The invention relates to computing and automation, can be used to display information from a computer and is an improvement of the invention according to the author. No. 1291956.

The purpose of the invention is to increase the speed of the device.

FIG. 1 and 2 are a functional block diagram of the device; in fig. 3 is a block diagram of the control unit.

The device contains the first 1 and second 2 blocks of memory, the first register 3, the generator of 4 characters, block 5 of the permanent memory of symbols, shaper 6 raster, line, block 7

 modulation, cathode-ray tube (CRT) 8, control block 9, from the first to the third groups of 10-12 elements And, the group of 13 elements OR, the second register 14, the first 15 and second 16 groups of prohibition elements, the third register 17, information device input 18, outputs 19-30 and input 31 of the control unit 9.

The control unit 9 includes a generator of 32 pulses, a counter 33 numbers

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elements of decomposition of characters along the X coordinate, counter 34 of the number of characters in the lines of displayed symbolic information, counter 35 of the number of elements of decomposition of symbols along the Y coordinate, counter 36 of the number of lines of the displayed symbolic information, first decoder 37, block 38 of the microinstructions constant memory, outputs 39- 67 of the block 38 of the fixed memory, the outputs 68 of the generator 32 pulses and the outputs 69-74 of the counters of the control unit.

The device additionally contains (FIG. 3) the third input 75 of the second group 11 of elements II, the third input 76 of the first group of 10 elements I, the fourth group 77 of the elements I, the fourth register 78, the first block 79 of comparison the tenth register 80, the first element I .81 , fifth group 82 of elements AND, fifth register 83, second comparison block 84, first element OR 85, sixth group 86 elements And, sixth register 87, (third comparison block 88, eleventh register 89, seventh group of 90 elements And, seventh register 91, fourth compare block 92, second element AND 93, second element OR 94 second the second decoder 95, the eighth register 96, the third element AND 97, the first element NOT 98, the twelfth register 99, the ninth register 100, the fourth element AND 101, the second element NOT 102, the third element OR 103 and information inputs 104-112 devices .

The device works as follows.

The generator 32 synchronization pulses produces pulses that synchronize the operation of the entire device. From its output, the pulses go to the inputs of block 7 (output 68) and counter 33. The pulses from the second output of the counter 33 are fed to the first input of the counter 34. The pulses from the second output of the counter 35 arrive at the first input of the counter 36

The status codes of the device from the first outputs of counters 33 and 35, the second outputs of counters 34 and 36 (outputs 71 and 74) and the output of register 14 (input 31) are fed to the inputs of the decoder 37 connected to block 38.

With the help of block 38, in which the codes of micro-instructions are recorded, all the main signals controlling the operation of the device are generated.

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At the first output 39 of block 38, a signal is written from Block 2, output 40 is a signal from Block 2, output 41 is a signal from Block 1, output 42 is a signal from Block 1, and output 43 is a signal to the fourth sub-register 3 (register 3 consists of four sub-registers), output 44 - a signal Reset the fourth sub-register, output 45 - a signal Record. third subregion, output 46 - signal Reset third subregister, output 47 - signal Record the second subregister, output 48 - signal Reset the second subregister, output 49 - signal Record the first subregister, output 50 - signal Reset the first subregister, output 51 - signal General reset of register 3, output 52 - signal Read-, block 5, output 53 - signal Record block 6, output 54 - signal 5 Begin line, output 55 - signal Begin frame, on output 56 - signal Return stroke along the line, at output 57 - signal Reverse move along the frame, at output 58 - with signal Reset block 7, output 59 - signal Ready to receive a code, output 60 - signal Transfer for block 35, output 61 - signal Reset counters of block 9, output 62 - control signal of unit 10, output 63 - control signal by block. 115 at output 64 is the control signal of unit 12, output 65 is a signal Reset - block 17, output 66 is a signal Recording to the first bit of block 17, and output 67 is a signal Recording to the second bit of block 17.

The counters 34 and 36 form the addresses of the first memory block 1 (character memory) outputs 70 and 73, the counters 35 and 36 form the addresses of the second memory block 2 (raster memory) outputs 72 and 73. Additionally, the addresses generated by the counters 34 and 35, are used to control blocks 5 and 6 of the 4-character generator (outputs 70 and 72).

From the outputs of block 38, additional control pulses of the first 10, second 11 and third 12 groups of elements I are output (outputs 62-64 and control pulses of the third register- (outputs 66 and 67).

Block 9 implements four basic modes of operation of the device and additional modes — erasing and masking in the window.

The mode number that is currently being implemented is recorded from the device input 111 to the register 14 at its first input. The reset of register 14 is effected by a signal from the input 112 of the device each time it switches to a new mode of operation.

Through register 3 (the first subregion) and the block of 16 character codes in the mode of exchange with a computer (input 18) are fed to the input of the first memory block 1. Here, they are recorded in consecutive cells in the order of arrival at its entrance. According to the signals from the output of the control block 9 in the raster generation mode, they are selected from the memory block 1 and, through the second register block 3, alternately pass into the 4-character generator.

From the output of block 5 of the permanent memory, the codes corresponding to the raster lines of the television decomposition of characters enter the raster line shaper 6 and through it, the third group of 12 And elements, the register 3 (third subregister) and the first group of 15 prohibition elements in the second block 2 of memory ti. At this moment, the register 17 is cleared and the information through the groups 16 and 15 of the prohibition elements in the memory blocks passes unchanged, since at their second prohibiting inputs the signals from the outputs of the register 17 are zero.

In the raster regeneration mode, informational words with a length of kxm bits through register 3 (fourth sub-register), the first group of 10 elements AND and a group of 13 elements OR arrive at block 7 (k is the number of characters per line, m is the length of the line video code of one character).

At this time, the second group of 11 elements And the signal from the output of block 9 is closed, the registers 96 and 100 are reset (input 110) and units are installed at the third inputs of groups 10 and 11 elements And.

An image is displayed on the screen of the CRT 8.

With the help of groups 11 and 12 elements AND and group 13 elements OR of the device, the fourth mode of operation is realized.

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In this mode, using the third group of 12 elements, AND, the connection between the output of the 4-character generator with register 3 and then with memory block 2 is broken.

Using the second group of 11 elements AND and a group of 13 elements OR, a direct connection of the 4-character generator with block 7 is established to display the variable component of the image. Due to this, while simultaneously implementing the third and fourth modes, the combination of the constant and variable components of the image is provided.

In memory block 1, information may change many times with the same contents of memory block 2.

If it is necessary to erase the image on the CRT 8 screen, the device is transferred to the first additional image erase mode, which is implemented by commands from the device input 2g 111, entering the input of register 14, previously cleared at input 112, in the form of signs of modifying the main mode numbers (additional Dov ko30, D ° C)

The modified codes of the main mode numbers translate the addresses of block 38 into the cell area, where they are stored from the microinstruction with units in bits of codes that correspond to the outputs connected via outputs 66 and 67 to the second input of the register 17. Register 17 is reset from the output of the block 9, connected to its first input through output 65. This allows you at the right moment to coerce one or both of the register 17 triggers and to prohibit the signals from their outputs from passing codes through the first 15 and 5 RUY 16 groups of prohibition elements or both at once depending on t What is erased is the contents of the first memory block 1, the contents of the second memory block 2, or the contents of both blocks at the same time.

The device using blocks 77- 103 also implements a second additional mode of operation — masking the image in the window. The window is part of a g rectangular image. It is masked as part of the image stored in block 1 of the symbolic memory, applying zero to the third input 75 of the second group of 11 elements AND

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and the part of the image in block 2 of the raster memory by feeding zero to the third input 76 of the first group of elements 10 I, as well as image fragments in both blocks 1 and 2 of the memory simultaneously. Zeros are supplied from the outputs of the elements HE 98 and 102 at .. units at the outputs of the elements 97 and 101. These elements switch the signal from the output of the element 81 and depending on the state of registers 96 and 100, which are cocked individually or together by signals from a computer at inputs 108 and 109 after resetting at input 110,

The signal at the output of the element AND 81 is equal to one only within the window. The size and position of the window are given by the coordinates of the upper left and right lower corners.

The coordinates of the window angles are entered at four receptions into registers 77, 82, 86, and 90 at input 104 from a computer after a pulse is applied to input 107 General reset.

The coordinate code X is first entered (the upper left corner of the window. In this case, the coordinate code is fed to the input 104, the register number to which the coordinate will be written is fed to the input 105. The register number goes to the first input of the register 99 and through it to the decoder 95's input

The signal from the first output of the decoder 95 enters the second input of the fourth group 77 of the elements And, and opens it to pass the coordinate code to the register 78,

After recording the information in register 78, the codes at inputs 104 and 105 are removed, register 99 with a pulse from the computer at input 106 through the OR element 103 is reset and new information is set at inputs 104 and 105.

The second is the coordination code.

You X4 lower right corner of the window. The signal from the second output of the decoder 95 through the fifth group of 82 elements And it is written in the fifth register 83,

The third is the code for the Y coordinate of the upper left corner of the window. The signal from the third output of the decoder 95 through the input 104 and the sixth group of 86 elements And it is recorded in the sixth register 87,

The fourth is the Y coordinate code of the lower left corner of the window. On the signal from the fourth output deshi0

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Fractional 95 through input 104 and the seventh group of 90 elements. And it is written into the seventh register 91,

After each entry, the register 99 is reset by a pulse from the output of the computer, coming through the first input of the third element OR 103 to the second input of the register 99,

Codes from the outputs of registers 78, 83, 87 and 91 are received respectively at the second inputs of blocks 79, 84, 88 and 92 of the comparison.

When the device operates, the signals from the outputs of the counters of the control block 9 are fed to the first inputs of the blocks 79, 84.88 and 92 of the comparison. At the output of comparator 79, signal 1 appears when the coordinate Qf coincides with the current content

counters 33 and 34, at the output of comparison block 84, when the X.J coordinate coincides, with the current contents of the same counters i

At the output of comparator block 88, a signal appears when the coordinate

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40

45

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dinata Y4 with current content score 50

35 and 36, at the output of the compare block 92, if the Ya coordinate coincides with the contents of the same counters,

The signal from the output of the comparison block 79 each time sets the tenth register 80 at its first input, the signal from the output of the comparison block 84 through the first element OR 85 resets the register 80 at its second input.

The active state of register 80 corresponds to the left and right edges of the window and its contents in the image decomposition rows.

The signal from the output of the compare block 88 cocks the eleventh register 89 at its first input, the signal from the output of the compare block 92 resets the register 89 at its second input through the second element AND 93 and the second element OR 94.

The signal from the output of the comparator block 88 corresponds to the upper edge of the window, the signal from the output of the comparator block 92 to the lower edge of the window, the signal from the output of the AND 93 element to the right-hand corner of the window. The signals from the outputs of the registers 80 and 89 are fed to the inputs of the element And 81.

Upon completion of the cycle of operation of the device in the second additional mode, blocks 78, 83, 87, 91, 95, 80, 89, 96, 92 and 14 are reset all together or in groups depending on the mode,

which will be set at the next stage of the device operation,

The signal at the output of the element And 81. Equal 1 within the window. Using a window, a masker can use part of an image contained in one memory block to occupy its place on the screen with an image from another memory and vice versa.

In order to perform masking with a known window size, one command from a computer is sufficient.

Claims (1)

Thus, the invention provides an increase in the speed of the device by implementing hardware masking of rectangular image fragments. Invention Formula A device for displaying information on the screen of a cathode ray tube according to Aut. No. 1291956, characterized in that, in order to increase the speed of the device, it contains the fourth, fifth, sixth and seventh groups of elements And, the fourth, the fifth, the sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth registers, the first, second, third, and fourth blocks of comparison, the first, second, third, and fourth elements of AND, the first, second, and third elements of OR, the second decoder, the first and the second elements are NOT, whose inputs are connected to the output the third and fourth And elements respectively, the first inputs of which are connected to the output of the first And element, the first input of which is connected to the output of the tenth register, whose information and control inputs are connected to the outputs of the first comparison unit and the first OR element, respectively, the first inputs of the And fourth elements , the fifth, sixth and seventh groups are the information input of coordinates, points of the device, whose address input is the information input . one 15 20 47652110 connected to the input of the second decoder, the first, second, third and fourth outputs of which are connected to the second inputs of the And elements, respectively, of the fourth, fifth, sixth and seventh groups, the outputs of which are connected to the information inputs of the fourth, fifth, respectively JQ of the sixth and seventh registers, the control inputs of which, the first inputs of the first, second and third elements OR are the first reset input of the device, the second input. The reset of which is the second input of the third OR element, the output of which is connected to the control input of the twelfth the registers, the outputs of the fourth, fifth, sixth and seventh registers are connected to the first inputs of the first, second, third and fourth comparison blocks, the second inputs of which are connected to the tenth output of the control unit, the output of the second the comparison unit is connected to the second input of the first OR element and the first input of the second element AND, the second input of which is connected to the output of the fourth comparison unit, the output of the second element AND is connected to the second input of the second OR element, the output of which is connected to the control input of the eleventh register, whose information input is connected to the output 35 of the third comparison unit, the output of the eleventh register is connected to the second input of the first element I, the reset inputs of the eighth and ninth registers are the third input of the device reset, the first and second inputs of installation 1 of which are the inputs of installation 1 of the eighth and ninth registers respectively, the outputs which are connected to 45 to the second inputs. According to the third and fourth elements AND, the outputs of the first and second elements are NOT connected to the third inputs of the AND elements of the first and the second. 2B thirty 40 the twelfth register, the output of which 50 groups. 69.70 19.72.73., 104 20 72 21 22 23 24 / ÁА26 27 7066 from72 73 73 W U 39 41 45 60 42 46 47 48 49 50 51 62 59 68 61 61 nineteen L 55 69 70 72 73 G 35 12 7F 61 61 s 28 70 53 29 30 68 54 39 55 40 56 4f 57 42 5B 43 44 45 46 63 47 48 70 71 60 49 31 69 50 51 52 37 38 53 54 36 74 S5 56 73 74 57 58 59 60 Fa & W