SU1325702A1 - Time-pulse value-ratio converter - Google Patents

Abstract

The invention relates to the conversion of analog values to code and can be used in automation and computing, in particular in telemetry systems for monitoring parameters and gas wells during their drilling. The invention makes it possible to increase the conversion accuracy by distributing the deviation value of the reference value N from the reference value N over the entire range of determination of the value being converted. The outputs of the filters 12 and 11 form the reference tires and convert (L

Description

132570

my nelichin. The signals present in the bus of the reference value, together with the output signals of the control unit 6, allow the pulses from the generator 3 to pass through the AND 5 element to the counter 4 of the reference value, determined by NN-N, and the dividing unit 7. Signals from the pin of the converted value and block 7 goes to block 8, then to block 9

one

The invention relates to the conversion of analog values into a code and can be used in automation and computing, in particular in telemetry systems for monitoring parameters of oil and gas wells during their drilling.

The purpose of the invention is to improve the accuracy of the conversion.

FIG. 1 shows a block diagram of a converter; fig.2 is an electrical circuit of the converter; Fig. 3 shows timing diagrams explaining the operation of the device (the number tbm corresponds to the number of the element),

The time and differential ratio converter contains the element AND 1, the counter 2 of the converted quantity, the generator 3 pulses, the counter 4 of the reference value, the element 5, the block 6 controls, the blocks 7 and 8 divisions, the correction block 9, the block 10 determining the sign, the filters G and 12 convertible and reference values

Correction block 9 (FIG. 2) contains a delay line 13, a pulse extender 14. Pulses, an element 15 that performs the NOT-3 OR-2I functions, and the sign definition block 10 includes a character trigger 16, and a zero-organ 17. The block 7 division consists of a reversible counter 18 and counter 19, element AND 20 and element OR.21. Division 8 is made as an operational counter. Filters 11 and 12 of the converted and reference values are necessary to infuse the specified parameters from the signals separated in time. - SteveIala x in the input bus. Outputs

and through the element And 1 to the counter 2 of the converted value. In the zero state of the discharge outputs of the counter 4, the zero-body 17 prohibits the passage of pulses from the generator 3 to the input of the division unit 8. Thus, the output result of the conversion is corrected depending on the deviation of the reference value from the reference value. 4 hp f-ly, 3 ill.

five

about

five

filters 12 and 11 form tires reference and convertible values. The signals present in the tires of the reference and convertible values, respectively, each at their own time interval or together with the output signals of the control unit 6, allow the pulses to pass through the AND 5 element to the counter 4 of the reference value and the division unit 7 or enter the division unit 8, its previously in a given state, and through the element AND 1 to the counter 2 of the converted quantity.

The control unit 6 (represented by a trigger, a counting input connected to the reference value bus, determines the order of operation of the entire device, first connecting to the generator 3 counter 4 of the reference value, setting it to the NO (reference value) state and subsequently recalculating the code stored in the counter 4 of the reference value into the division unit 7. The zero-output 17 prohibits the passage of pulses from the generator 3 to the input of the block 8 when the discharge outputs of the counter 4 are in the zero state, the trigger 16 characters changes its state when counter 4 transitions through a logical zero state and determines the direction of operation of correction block 9, connecting the elements OR element HE-3 Ш1И-2И 15, Counter 18, which is part of block 7, is set to a logical state, corresponding to the output code of the reference counter 4, a signal from the output of the control unit 6 and from its transfer output, which

3

It is also connected to the counter 19, which calculates the number of transitions of the counter 18 through the zero state during the time of the signal of the reference value.

The output code of the counter 19 to the front of the signal of the converted value is rewritten into block 8, the pulse from the transfer output of which sets it to the same logical state. The number of pulses at the transfer transfer unit B of division corresponds to the ratio of the quantity being converted and the number corresponding to the output code of block 7 of division.

The device works as follows.

The inputs of filters 12 and 11 from the input bus receives pulses separated by time and modulated by duration, which correspond to the reference and converted values. The pulse of the reference value at the counting input changes the state of the control unit 6, determining the operation cycles of the entire device. In the first cycle, the control unit 6 permits the passage of pulses from generator 3 through element 5, the output of which generates a pulse sequence, the number of pulses of which corresponds to the numerical value of the reference value, to the counting input of counter 4, which is pre-pulse from the first output of block 6 control is set to the state NH, and through the trigger 15 characters on the control input switches to the subtraction mode, i.e. subtracts the input number N.

If the number of pulses. N, which corresponds to the reference value and arrives at the counting input of the counter 4 of the reference value, is equal to the number of pulses NJJ of the reference value; the counter 4 is set to the zero state at the end of the reference value signal. Thus / lN n-No 0.

In this case, with the account successively;

impulses corresponding to the converted value, at the transfer output of dividing unit 8, pulses do not occur, because its estimated input is closed by a signal from the output of the null organ 17 and at the inputs of the HE-3 OR-2 and 15 element associated with the output of dividing unit 8 and exit extender 14 long7024

impulses, keeps potential low.

The trigger 16 characters, set to the state of the logical unit by the pulse front from the output of control unit 6, remains in the same state, allowing the delay of pulses delayed by line 13 to pass from the generator 3 to the output of the correction unit 9 and only through the lower half of the NE-3 IPI element -2and 15.

From the output of the correction block 9, the pulses are fed to the input of the element AND 1 and pass through it to the counter 2 of the converted value during the action on the first input of the element AND 1 of the signal of the converted value. Thus, with N-NO jN-Ov, the counter 2 of the converted value comes from generator 3 all the pulses during the time at the first input of the And 1 element of the signal of the converted value.

Under the influence of external factors, the pulse duration corresponding to the reference value can vary, as a result of which the number of filling pulses of the reference value N also changes and becomes different from Ng by the value

JN N - Ы „,

where N is the number of pulses corresponding to the reference value; Ng is the number of pulses corresponding to the reference value. In this case, the sign of the increment 4N depends on the ratio of the values of N and Np. Evenly distributing and N over the entire interval of the reference value, get the correction interval n, i.e.

n 4N N.

n or

N

In the general case, the number n is fractional, however, if we operate only with integers.

n 4N + n N,

N

where Pv is the remainder of the division,

J n

provided that n is an integer.

If N: N a, on the bit outputs of Counter 4, upon completion of the reference value signal, the number ii N is set in the binary code, and the character determination trigger 16 does not change its initial logic state.

If N is NJ, then counter 4, after counting N pulses, is reversed, after which the number / iN is formed at its outputs, and the character determination trigger 16 changes its logical state.

The dividing unit is produced 7

divisions - A N

i.e. getting

the correction interval p, with the recording of the result in the counter 19

When counting the number of pulses corresponding to a non-convertible, dividing unit 8, after receiving n pulses from generator 3, nullified its input from its transfer output and generated a control signal to correction unit 9, which, depending on the logical state of the trigger 16 characters the moment either generates an additional pulse, which is superimposed on the output sequence of the generator of 3 pulses (with NN), or prohibits the passage of one pulse of the same sequence to the input of an And 1 element (with NN,).

In this way, a code is formed in the counter of the quantity being converted that is proportional to the duration of the quantity being converted and at the same time is a ratio of the value being converted and the reference quantity.

Claims (5)

1. Time pulse ratio converter containing the first element I, the output of which is connected to the counter input of the conversion quantity, the second element I, the first input of which is connected to the output of the pulse generator, the output connected to the first input of the counter of the reference value, the second input connected to the first the output of the control unit, characterized in that, in order to increase the accuracy of the conversion, filters of the reference and convertible values, two division units, a sign definition unit and a correction unit, output cat cerned pervyg- connected to input of the first AND gate, a second 13257026 the input of which is combined with the first input of the first dividing unit and connected via a filter of the conversion value to the input bus, to which is connected to the input of the filter of the reference value, the output of which is connected to the input of the control unit, the third input of the second element And the first input of the second dividing unit p the second input the JO is connected to the second output of the control unit, the third input is connected to the output of the pulse generator, the fourth input is combined with the first input of the sign definition unit and is connected to the output of 15 bits of the reference value counter The transfer output of which is connected to the second input of the sign determining unit, the first output of which is connected to the second input of the first division unit 20, and the second and third output respectively to the first and second inputs of the correction unit, the third input of which is combined with the third input of the first division unit and connected to the output25 of the pulse generator, and the fourth input is connected to the output of the first dividing unit, the fourth input of which is connected to the output of the second dividing unit, the third input of the determining unit The 30 characters are combined with the second counting input of the reference value and connected to the first, output of the control unit, and the second output of the character determining unit is connected to the third input of the counter This reference value. 2. A transducer according to claim 1, characterized in that the correction unit is executed on the delay delay, the pulse width expander and The 40 HE-3 OR-2I element, the output of which is the output of the block, the first and second inputs are respectively the first and second inputs of the block, the third and fourth inputs are combined and connected to the output of the delay line, the input of which is the third input of the block The ka, five input is connected to the output of the pulse extender, the input of which is combined with the sixth inlet 5Q house of the element IE-3 OR-2I and is the fourth input of the block. 3. The transducers according to claim 1, O t - characterized by the fact that the sign definition unit is made in the form 2 null organ and trigger, the first and second inputs of which are the second and third inputs and the block, respectively, and the first and second outputs are the second and third, respectively: the output, the first output of which is connected to the second input of the first dividing unit, and the second and the third output, respectively, to the first and second inputs of the correction unit, the third input of which is combined with the third input of the first division unit and connected to the output of the pulse generator, and the fourth input is connected to the output of the first division unit, the fourth input of which By connecting the output of the second dividing unit, a third input determination unit the character is combined with the second counting input of the reference value and connected to the first, output of the control unit, and the second output of the character determining unit is connected to the third input of the counter reference value. 2. A transducer according to claim 1, characterized in that the correction unit is executed on the delay delay, the pulse width expander and the NOT-3 OR-2I element, whose output is the output of the block, the first and second inputs are respectively the first and second inputs of the block, the third and fourth inputs are combined and connected to the output of the delay line whose input is the third input of the block, The five input is connected to the output of the pulse extender, the input of which is combined with the sixth input of the element IE-3 OR-2I and is the fourth input of the block. 3. The transducers according to claim 1, O t - characterized by the fact that the sign definition unit is made in the form zero-organ and trigger, the first and second inputs of which are the second and third inputs and block respectively, and the first and second outputs are respectively the second and third: output71 The unit is a block, and the input of the null organ is the first input of the block, and its output is the first output of the block. 4. A transducer according to claim 1, characterized in that the control unit is complete on a trigger whose input is the input to the unit, and the direct and inverse outputs are respectively the second and first outputs of the unit. 5. The transducer according to claim 1, T is characterized in that the second division unit is made on the elements AND OR, the reversible counter and counter of the counting input of which is combined with eight the first input of the OR element and connected to the overflow output of the reversible counter, and the reset input is combined with the first input of the AND element, the second input of the OR element and is the second input of the block, the first and third inputs of which are the second and third inputs of the AND element, the output of which connected to the subtracting input of the reversible counter, the setup input of which is connected to the output of the OR element, and the installation inputs of the codes are the fourth input of the block, the output of which are the outputs of the counter. Vhad Mzh 8bi) i.lZ L I I I I I I I I I I I I I I I I JJL P P III I I III I I III I I III I I I III IIIShU Fig.Z 1 I-g g g P