SU1314473A1 - Synchronizing device - Google Patents

Abstract

The invention relates to a technique of discrete information. The purpose of the invention is to improve the synchronization stability. The device contains four mixers 1-4, two blocks of phase-locked loops 5 and 6, two dividers 7 and B frequencies, a multiplier 9 frequencies, an adder 10, two band-pass filters 11 and 12, and three delays of 13, 14 and 15 The goal is achieved by introducing mixers 3 and 4, which eliminate the synchronization failure, adder 10, the output signal of which contains all the frequency components available in the input signals, a band-pass filter 12 that separates the difference frequency, and delay elements 13, 14, and 15 each of which delays a signal for a period T of clock frequencies . 2 Il. (L 00 s 00

Description

113I4A7

The invention relates to a technique for transmitting discrete information and is intended for synchronization in synchronous communication systems with minimal frequency shift keying, 5

The aim of the invention is to improve the stability of synchronization.

FIG. 1 is a diagram of the synchronization device in FIG. 2 is a graph of the formation of discrete spectral components at various points in the circuit.

fO

The synchronization device contains the first, second, third and fourth mixers 1-4, the first and second PLL blocks 5 and 6, the first and second frequency dividers 7 and 8, frequency multiplier 9, adder 10, first and second band-pass filters 11 and .12, pert5

20

when (k-l) at the input of the synchronization device, there is a signal y (t) S (t) with an instant hour / g

Totoj SOHD - with Uj; -1 or c

t instantaneous frequency 03

about + -2t

at

the second and third elements of the delay U +1 (Fig. 2 a, b) are fed to

vy,

ki on T 13, 14 and 15.

The device works as follows.

The signal with the minimum frequency manipulation of the form

the inputs of the mixer 1, one of which has a delay for the duration of the clock interval T, at the output of mixer 1, the signal is

S (t) A sin

(t -. X,),

kT. & t (k + l) T,

where, 1 ± 1 sequence

information symbols k are integers;

-Uj, y, (t) contains frequencies 2 CO

and

UK-I Y, (t) contains the frequency 2 (tjp + -ij ;;)

 k-t

and -, p;

/ h

-1 y, (t) contains the frequency 2 (o „- J) 5

II

about 2T

PLL 5 and 6 blocks are tuned respectively to twice the carrier frequency (2 Schd) and half clock

o frequency (). FIG. 2v weekend

the mixer 1 signal, which is fed to the inputs of the PLL units 5 and 6 through the adder 10, contains these frequency components only in the case. 11 Therefore, in the case of U and, a synchronization failure could occur, the method / (T

at Uy -Uj,., - yj (t) contains the frequencies 4cjg, 2 (0) 0+ j x 2 (Wo

at U U ,, -1 - y (t) contains frequencies 2 (2cOo- j: ;-) and -;

when U UK ,, 1 -) contains the frequencies 2 (2cOo + -J) and ---.

time;

Duration of the clock interval;

average angular frequency of the signal;

amplitude;

X.

XK., + (And,., - and;) - 2

- the initial phase is constant during the k-ro clock interval,

when (k-l) at the input of the synchronization device, there is a signal y (t) S (t) with an instant hour / g

Totoj SOHD - with Uj; -1 or c

t instantaneous frequency 03

about + -2t

at

U +1 (Fig. 2 a, b), is fed to

the inputs of mixer 1, one of which has a delay for the duration of the clock interval T, At the output of mixer 1, the signal is equal to

Y, (t)) - y „(t-T).

Depending on what the neighboring information symbols are, the signal y, (t) contains different frequency components. Three cases are possible (Figure 2B):

living frequency 2 (tjp + -ij ;;)

II

about 2T

a thread that allows the introduction of mixers 3 and 4,

The output signal of the PLL 5 YyCt), contains only about; the frequency component is 2-oo. - This signal is fed to the second input of the mixer 3 with a delay of T time, as well as to the input of the frequency divider 7. The output signal of the mixer 3 contains the sum and difference frequency components of the signals y (t) and yyCt-T). Three cases are possible (Fig. 2g);

0

3 13) 44734

Similarly, frequency congruence forms only frequency ---. Thus, the pressing signals of the signal V4 (s) T

mixer 4. The output signal y (t) way, Y (t) contains the following

PLL 6 at any interval co-frequency components (Fig, 2h):

with and, -and ,,, - 2 (and „+), 2 (“ „-), -C-;

/

with and, and,., -1 - 2a) and 2 (with „- ---);

/ 17 with and. UK., 1 - 2со „and 2 (Mo + ---).

The signals y, (t), y, (t) and y (t) are the sum of the 5 components that are present in the adder 10 and are output in the input signals, and the nominal signal y, (t) contains all frequency (fig.2g):

at and c -U) (., - frequency components

20 „, - | -,, - | -, 2 (co, -) 2 (a)„ + / -);

with and - - frequency components

l

2a, -f, 2 (0), - ---.). 2 (20 „-), 2 (сО- -f-) J

with and Ufc., 1 - frequency components

20,,. - | -, 2 (with -fj-), 2 (2i -f--), 2 (u, +).

The output signal of the adder 10 y (t) is separated by the corresponding filter; it contains components with frequencies 11 and 12. In the multiplier 9, frequencies

“ITJC multiplies the frequency by two,

2 sop and ---, which are configured with-35,

Therefore, its output signal

corresponding PLL blocks 5 and 6, neza-2 G

 has a frequency ---. depending on the sequence of information

national symbols and. Thus, regardless of the occurrence, a stable synchronization of the instantaneous frequencies of qi at an arbitrarily long sequence of the input signal y (t), a device of a sequence of identical symbols, is provided. Zah- stably allocates three frequencies: synchronization clock after signaling - 2 ii

la y (t) to the input of the device, the incident frequency --- at the output, is multiplied after the first change of the symbol Пц 45 resident of frequency 9; frequency o + T (fig. 2 d, e) .2Т

In dividers 7 and 8, the frequency is the corresponding U 1; the output is a division of the frequencies of the input signals of the band-pass filter 1I; frequency by two. After that, the output of the divider, (j-corresponding to U l 7, always contains a signal with a frequency of 50 ° СОо, and at the output of the divider 8 -1, at the output of the bandpass filter 12.

signal with frequency ---. These signals are the best mode of operation of the blocks.

PLLs 5 and 6 are provided when they are available at the inputs of the mixer 2, as amplitudes of the components c, whose input signal contains a sum of

 jTfrequencies 2 co ,, and ----, the corresponding fre- quency of edc + -5: ;; and difference

; at their entrances; This is achieved

frequency by selecting gain ratios

the inputs of the adder 10. The amplitudes will be constant if

.kiА 2

i. k.

Ab 2

h.L

where k, is the transfer coefficient of the adder 10 at the input connected to the output of the mixer 1;

k., is the transfer coefficient of the adder 10 at the input J connected with the output of the mixer 3;

k is the transfer coefficient of the adder 10 on the input connected to the output of the mixer 4;

And, - the amplitude of the signal at the output of the PLL 5;

Ag is the amplitude of the signal at the output of the PLL 6.

Claims (1)

Invention Formula A synchronization device containing the first mixer, the first and second PLL units, the outputs of which through the corresponding first and second frequency dividers are connected respectively to the first and second inputs of the second mixer, the output of which is connected to the input of the first bandpass filter, the frequency multiplier whose output is first (l / fJxT -1 () T 1 {-g) D 1) D -1 (x "} T 1 fK 5) T -1 (-1 () T I I T I I I I (a, -} f / 2T,, / гт Шц g / гт, ш,: / гт ш, - / г I1f. ( VNIIPI Order 2221/56 Circulation 639 Random polygons pr-tie, Uzhgorod, st. Project, 4 the output of the device, characterized in that, in order to increase the synchronization stability, the third and fourth mixers, the second band-pass filter, the first, second and third delay elements T, where T is the period of the clock frequency, and the adder, the first input of which is connected are entered into it to exit first mixer and connected to the first inputs of the third and fourth mixers, the outputs of which are connected respectively to the second and third inputs of the adder, the output of which is connected to the inputs of the first and second PLL units, the outputs of which through the second and third delay elements on T are connected respectively to the second the inputs of the third and fourth mixers, the output of the second PLL unit is connected to the input of the multiplier, and the output of the second mixer is connected to the second bandpass filter, the input of the device is connected to one input of the first mixer and through the first delay element T to the other input of the first mixer, and the outputs of the first and second band-pass filters are the second and third outputs of the device, respectively. Subscription