SU1387178A1 - Random process generator - Google Patents

Description

(21) 4142705 / 24-21

(22) 11/03/86

(46) 04/07/88. Bul № 13

(71) Taganrog Radiotechnical Institute. V.D. Kalmykova

(72) A. A. Afonin, V. M. Glushan and G. X. Khon

(53) 621.384.2 (088.8)

(56) USSR Author's Certificate No. 484626, cl. H 03 K 3/84, 1975. USSR Copyright Certificate No. 1205261, cl. H 03 K 3/84, 1985.

(54) GENERATOR OF A RANDOM PROCESS

(57) The invention can be used in radio engineering and computer engineering. The purpose of the invention is to expand the functionality of the generator. The device contains generators 1 and 8 of the Poisson stream of pulses and clock pulses, a block of 3 switches, elements OR 4 and 5, elements AND 6 and 7, counter 9, a reversible counter 10, a buffer register 11, a digital-analogue converter 12, an integrator 13 and an element 14 delays. The introduction of a cyclic shift register 2 and the formation of new functional connections increases the number of generated processes. 1 il.

but

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The invention relates to a pulse technique and can be used in radio engineering and computer engineering.

The purpose of the invention is to expand the functionality of the generator by increasing the number of generated processes.

The drawing shows a flowchart of a random process generator.

The proposed generator contains a generator 1 Poisson pulse flow, cyclic register 2 shift, block 3 switches, the first 4 and second 5 elements OR, the first 6 and second 7 elements And, the generator 8 clock pulses, counter 9, connected in series reversing counter 10, the buffer register And, the digital-to-analog converter 12 and the integrator 13, the element 14. delay. The output of the generator 1 Poisson flow is connected to the input of the cyclic shift register 2, the corresponding outputs of which through the block 3 switches are connected to the corresponding inputs of the first 4 and second 5 OR elements, the outputs of which are connected to the inputs of the first 6 and second 7, respectively, and the outputs of the latter are connected with the first and second inputs of the reversible counter 10, the installation of which is connected to the output of the delay element 14, the input of the latter is connected to the synchronization input of the buffer register 11 and c the output of the counter 9, the input of which is connected with the first inputs of the first b and second 7 elements And, and with the output of the generator 8 clock pulses.

The random process generator works as follows.

Under the action of pulses from the generator I output of a Poisson pulse stream, a single signal, at the time of arrival of the next clock pulse from the generator output 8 clock pulses, can appear uniformly at any output of the cyclic shift register 2 and depending on the position of the switches in the 3 switch block at the output the first element OR 4 or at the output of the second element OR 5, or does not appear on any of them. The transitions of the reversible counter 10 (“wandering”) from one state to another occur under the action of pulses from the generator output of 8 clocks passing to the input of the forward (through element 6) or the reverse (through element 7) of the account of the reverse counter 10 depending on which of the outputs of the elements OR 4 and 5 there is a single signal at this moment. At the same time, the clock pulses are fed to the input of the counter 9, the overflow pulse from the output of which provides the recording of the state of the reversible counter 10 to the buffer register 11 and through the delay element 14 sets the reversible counter 10 to the initial state. State

0

the buffer register 11 is converted by the digital to analog converter 12 to analog voltage, which is smoothed by the integrator 13.

For example, let the cyclic shift register 2 have nine outputs, with the first three connected to the inputs of the element OR 4, the next three connected to the inputs of the element OR 5, and the last

Q three are not connected to any of them. Let the capacitance of counter 9 be equal to two, and by the time of arrival of the first clock pulse from the generator output 8 clock pulses the signal appears at the third output of cyclic register 2 shift. it

5 leads to the fact that a single signal appears at the output of the element OR 4 and through the element AND 6 a clock pulse arrives at the input of the direct count of the reversible counter 10, which is set to the state "1. Let, by the time of arrival of the second clock pulse, the signal appears at the seventh output of the cyclic register 2 shift. As a result, the signal does not appear on any of the outputs of the OR elements 4 and 5, as a result of which the reversible counter 10 remains in the same, i.e. in the first state. Upon the arrival of the second clock pulse at the input of the counter 9, an overflow pulse appears at its output, which rewrites the code of the first reverse state

0 of the counter 10 to the buffer register 11 and after passing through the delay element 14 resets the reversible counter 10 to the initial zero state. The process then repeats.

In order for the generator to generate

5, a random process with a uniform law of probability distribution, it is sufficient to input the logical level “1. To obtain the binomial distribution of a random variable, half of the outputs of the cyclic register 2 shift must be connected to the inputs of the OR 4 element, and the other half to the inputs of the OR 5 element.

45

Claims (1)

Invention Formula A random process generator containing a Poisson pulse generator, the first and second elements And, the outputs of which are connected respectively to the first and second inputs of the reversible counter, the outputs of which are connected to the corresponding inputs of the buffer register, the outputs of which are connected to the corresponding inputs of the digital-to-analog converter, the output of which is connected with the input of the integrator, a clock pulse generator, the output of which is connected to the first inputs of the first and second elements And and to the input of the counter, in which is connected with the course five the synchronization input of the buffer register directly, and with the input of the reversible counter installation through a delay element, characterized in that in order to expand the functionality of the generator by increasing the number of generated processes, a cyclic shift register is entered into it, the corresponding outputs of which are connected to the corresponding outputs through switches the inputs of the first and second elements OR, the outputs of which are connected to the second inputs of the first and second elements, respectively, the output of the generator PUA The sonson stream is connected to the synchronization input of the cyclic shift register.