SU1367147A2 - Pulse selector - Google Patents

Abstract

The invention can be used to protect digital devices from impulse noise. The purpose of the invention — improving reliability — is achieved by monitoring the integrity of the input circuit of the pulse selector. To do this, the pulse selector containing the first delay element 1, the AND-NOT 2 element, the OR 3 element and the RS-flip-flop 4, additionally introduced the inverter 5, the resistor 6, the equivalence element 7, the second delay element 8 and the AND 9 element In this case, the delay time of the second element B is equal to the delay time of the signal of the first delay element 1 from the input to the first intermediate output. The introduction of the inverter 5 and the resistor 6. Provides the transition device in the self-oscillatory mode in violation of the integrity of the input circuit. 1 il.

Description

The invention relates to a pulse technique and can be used to protect digital devices from impulse noise.

The aim of the invention is to increase reliability by monitoring the integrity of the input circuit of the pulse selector.

The drawing shows a block diagram of a device.

The device comprises a first delay element 1, an NAND element 2, an OR element 3, an RS trigger 4, an inverter 5, a resistor 6, an equivalence element 7, a second delay element 8 and an AND 9 element, the input of the first delay element 1 being an input to the device and connected to one of the inputs of the AND-NOT 2 elements, the OR element 3 and the equivalence element 7 directly and through the resistor 6 to the other input of the equivalence element 7. the output of the inverter 5, the outputs of the first delay element 1 are connected to other inputs of the AND-NOT 2 element and the OR element 3, and the first output of the first delay element 1 is also connected to the inverter 5 input, the output of the AND-NOT 2 element is connected to S -input of the RS-trigger 4, the output of the OR element 3 is connected to the R-input of the RS-trigger 4, the output of which is the first output of the device, the output of the equivalence element 7 is connected to one of the inputs of the element And 9 directly and through the second delay element 8 with another input element And 9, the output of element And 9 is another output ohm device.

The delay time of the second delay element 8 is selected equal to the delay time of the signal of the first delay element 1 from the input to the first intermediate output.

The device operates as follows.

If in the initial state of the pulse selector * * the signal of the device received a zero level signal, then after the arrival of a single signal with a duration exceeding the propagation time of the signal along the delay element 1, single signals are set at all outputs of the delay element 1 and the inputs of the AND-NOT 2 element. The signal from the output of the element AND-NOT 2 RS-trigger 4 is switched to a single state.

If a short zero level interference comes now, then during its passage along element ₅ and 1 of the delay at the inputs of the element

AND-NOT 2 does not occur simultaneously at a unit level signal, and at the inputs of an OR 3 element there does not occur the simultaneous appearance of signals at level 10. Therefore, neither the AND-NOT 2 element, nor the OR 3 element supplies a control signal to the inputs of the RS-trigger 4 and the latter does not change its state.

If a long zero level signal arrives at the device input, then after a time equal to the duration of the signal propagation through delay element 1, at all inputs of the element

OR 3, zero signals are set, the OR 3 element outputs a zero signal at the output, which switches the RS-trigger 4 to the zero state.

If in this state of the device 25 a short unit level noise appears at its input, then it does not cause a zero signal at the output of the AND-NOT 2 element, since at all outputs of the delay element 1, a single signal simultaneously caused by an interference cannot appear 30. Therefore, the RS-trigger 4 does not change its state.

If there is a violation of the integrity of the device’s 35 circuit, the signal at the input of the device is determined by the level coming from the output of the inverter 5 through the resistor 6. This signal, lingering on the delay element 1, arrives at the input of the inverter 5 and switches the latter. This process is repeated many times until the integrity of the input circuit is restored. Short pulses propagating along the delay element 1 do not allow either the AND-NOT 2 element or the OR element 3. The RS-trigger 4 remains in its original state. Unipolar signals appear at the inputs of the equivalence element 7 and the equivalence element 7 generates a long unit signal, which, passing the second delay element 8, coincides at the input of the And 9 element with the signal at its other input. Element And 9 produces a single signal indicating an open circuit of the input circuit of the device.

The introduction of the inverter 5 and the resistor 6 into the device leads to the transition of the device into self-oscillating mode in case of violation of the integrity of the input circuit. These high-frequency oscillations at the input of the device are perceived by the device as interference signals. Therefore, the switching of the RS-trigger 4 does not occur and it retains the state preceding the violation of the integrity of the input circuit. Yu

Claims (1)

Formula of the invention Pulse selector by ed. No. 993467, characterized in that, in order to increase reliability by controlling the integrity of the input circuit, an inverter, a resistor, an equivalence element, a second delay element and an I element are introduced, the inverter input being connected to the first output of the first delay element, the output the inverter is connected to one of the inputs of the equivalence element directly, and to the other input of the equivalence element and the input of the selector through a resistor, the output of the equivalence element is connected to one of the inputs of the AND element and the input of the second delay element, the output to is connected to the second inputs of the element AND, the output of the element I. is the second output of the pulse selector.