SU1356220A1 - Analog-digital delay device - Google Patents

Abstract

This invention relates to radio engineering and can be used in a shaper of antenna patterns. The purpose of the invention is to expand the range of durations for 73 held analog signals. The device contains a n-bit analog-to-digital converter 1, a recirculation memory consisting of a switch 2 and a block of 3 registers, a digital-to-analog converter 5. a generator of 6 pulses, a decoder 9, a key 11 and a low-pass filter 12. Introduction of the register 4, the pulse counter 7, the AND 8 element, the OR 10 element and the formation of new functional connections allows the delay of the low-frequency analog signal of unlimited duration. Moreover, to change the delay time, it is enough to connect to the corresponding output of the device or use a tunable decoder. 1 il. I cl oo cl C5 tsD Yu

Description

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The invention relates to radio engineering and can be used in waveform formers of antenna patterns, filters, correlation analyzers, linear antenna signal simulators, and other signal processing equipment requiring a delay of low frequency signals in time.

The purpose of the invention is to expand the range of durations of delayed analog signals.

The goal is achieved by writing samples of the input analog signal, converted into digital form, to the recirculation memory, the function of which is performed by the register block and the switch, where they are stored for the required delay time, after which they are combined and fed to the appropriate low-pass filter. which restores the continuous waveform.

The drawing shows a structural diagram of an analog-digital delay device.

The device contains an n-bit analog-to-digital converter 1, switch 2, a block of 3 registers consisting of parallel shift registers, register 4, a digital-to-analog converter 5. a generator of 6 pulses, a counter 7, and an element 8 as well as a formation circuit delayed signal, including the decoder 9, the element OR 10 and the number of delay channels connected in series key 11 and the filter 12 of the lower frequencies. The input signal is fed to the input 13, the output of the delayed signals is carried out on the outputs -.

The device input is connected to the input of an n-bit analog-to-digital converter 1, the outputs of which are connected to the first information inputs of switch 2. The outputs of switch 2 are connected to the inputs of a block of 3 registers consisting of n shift registers connected in parallel Outputs of the shift registers of block 3 the registers are connected to the second information inputs of the switch 2 and to the inputs of the register 4. The clock inputs of the shift registers of the block 3 of registers are connected to the output of the generator 6 pulses. Generator output 6 im10

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pulses are also connected to the 7-pulse counter input, the outputs of which are connected to the inputs of the decoder 9, as well as through the element 8 to the control input of the switch 2 and to the second input of the analog-digital converter 1. The outputs of the decoder 9 are connected to the control inputs of the corresponding keys - The outputs of which are connected to the inputs of the filters 12-1 - 12-p low frequencies, the outputs of which are the outputs 14-1 - 14-p of the device. The outputs of the decoder 9 is also connected to the inputs of the element OR 10, the output of which is connected to the synchronous input register 4.

The outputs of the register 4 are connected to the inputs of the digital-to-analog converter 5, the output of which is connected to the inputs of the keys 11-1 - 11-p.

The device works as follows.

The input signal samples are recorded in a recirculation memory, which is the main unit for recording, time compression and signal delay. The recirculation memory device consists of a series-connected switch 2 and a block of 3 registers, which includes n parallel shift registers, the outputs of which are connected to the corresponding inputs of switch 2. To synchronize the recording processes and shift the signal in the recirculation memory the shift registers of the block of the 3 registers are clocked by signals from the generator of 6 pulses, followed by a period Trc, and a write pulse, following from the output of the element And 8 from iodine, 45 cAB - 1) where N - a width of unit 3 registers shift registers. The circulation period of the signal samples is. . differs from T by value. This leads to the fact that the sampling of the input signal, recorded at the moment of arrival of the recording pulse, shifts with each circulation. On a relatively write pulse. Therefore, opening the keys 11 in the i-M clock cycle following a pulse from the generator output 6 pulses, which follows the write pulse (FROM), can be read a sample of the signal that passed through the i35

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lectures, i.e. having a delay relative to the input signal. The described principle is used to obtain a delayed signal in all read channels consisting of a corresponding key 11 and a low pass filter 12.

The process of shifting the signal samples relative to the CI continues for (N 1) circulation, after which the sample coincides in time with the CI. In this case, the circulation ring is opened and instead of the previous sample, a new one coming from the output of the analog-digital converter 1 is recorded. Thus, in each circulation there is a continuous update of the recorded information by one sample, which leads to the possibility of a delay of unlimited duration uninterrupted low-frequency analog signals.

When reading, the code corresponding to the sample number relative to the CI, is fed from the output of the counter 7 to the input of the decoder 9, as a result of which the outputs of the latter alternate pulses, the temporary position of which corresponds to the desired signal delay (the number of the clock pulse relative to the C). The pulse from the output of the decoder 9 is sent to the control input of the corresponding key 11-1 - 11-p and through the element OR 10 - to the synchronous input of the register 4, where the i- (relative to OZ) sample of the input signal is recorded on the leading edge of the incoming pulse. This sample restores the analog form in the digital-analog converter and is fed through the corresponding unlocked key 11-1 - 11-p to the filter 12-1 - 12-p low frequencies. The restored continuum signal is fed to the corresponding output 14 of the device. Due to the fact that the time shift of the pulses at the outputs of the decoder 9 relative to the IZ increases with increasing output number, the delay of the signal at the outputs of the device increases accordingly, i.e. the device performs the function of a multi-drop delay line of a low-frequency analog signal.

Compared with the known device, the analog-digital delay device with the same bit size N of the shift registers of the block of registers provides (N - 1) times a wider delay range of the input signal. This saves hardware costs while ensuring the required range of delays.

The device can be completely h

performed on integrated circuits 140, 155, 505 and 594 in accordance with RTM for their use.

Introducing new devices and Tai: the same new functional elements.

connection, it allows you to delay a low-frequency analog signal of unlimited duration, and to change the delay time, it is enough to connect to the corresponding

device output or apply a tunable decoder.

Claims (1)

Invention Analog-to-digital device for a holder containing an n-bit analog-to-digital converter, a register block consisting of n shift registers connected in parallel, a clock pulse generator connected by an output to the clock inputs of the register block shift register, a digital-analog converter the purpose of expanding the range of durations of delayed analog signals, a pulse counter, a register, an OR element, an AND element, a switch, a decoder with the number of outputs n, r identical are entered into it circuits consisting of a key and a low-pass filter connected in series, the outputs of which are the outputs of a device whose input is the first input n-times An analog-to-digital converter whose outputs are one bit connected to the first information inputs of the switch, whose outputs are connected to the corresponding inputs of the register shift registers, the output of the shift registers the registers are connected to the information inputs of the register and the second information inputs of the switch; the outputs of the register are connected to the inputs of the digital-to-analog converter, the output of which is connected to the first inputs of the keys, the control inputs of which are connected to the corresponding 513562206 the decoder's outputs and the elemental inputs are connected to the generator output OR, the output of which is connected to the pulses and inputs of the AND element, a register output, the inputs of the decoder which are connected to the controller input are connected to the corresponding laziness of the switchboard and the second inputs pulse counter, input of a co-analogue converter.