SU1348985A1 - Multichannel programmable pulse generator - Google Patents

Abstract

The invention can be used in test equipment and. digital computers, in particular, in functional control devices of integrated circuits with a higher level of integration, as a generator of synchronizing pulses, building and controlling signals for control objects and amplitude-time discriminators. The aim of the invention is to expand the functionality. To achieve this goal, 3 delay lines, counters 4 and 5, reset circuit 6, control block 7 are additionally introduced into the device. The device also contains a reference frequency generator 1, a period former 2, pulse shaping channels 8.1-8.N, each consisting of memory blocks 9 and 10, switches 11 and 12, and output trigger 13. 1 cp f-ly, 5 ill. (L 00 4 00 so 00 ate FI. 1

Description

one

The invention relates to a pulse technique and can be used in instrumentation and digital computing devices, in particular in functional control devices of integrated circuits with a higher level of integration, as a generator of synchronizing, strobe and control signals for control objects and amplitude temporary discriminators.

The purpose of the invention is to increase the reliability of work and expand the functionality of the device.

FIG. 1 is a block diagram of a U-boxed programmable pulse generator; FIG. FIGS. 2-A are diagrams of a period former, a reset device and a control unit; figure 5 - timing charts of the device.

The device contains a reference frequency generator 1, a period former 2, a delay line 3, counters 4 and 5, a reset circuit 6, a control block 7, 8.1-8.N pulse shaping channels, each of which consists of blocks 9 and 10 of memory, switches 11 and 12 and output trigger 13.

The output of the generator 1 of the reference frequency is connected to the clock input of the former 2 periods and through line 3 delays with the first inputs of the switches 11 and 12 channels of 8.1-8.N pulse. The power supply, the 1st period spanner 2, is connected to the counting inputs of counters 4 and 5, the second output is connected to the installation of 1 inputs of counter 4 and the reset circuit 6, the output of KoTopoii is connected to the installation input 5. The information sources of the periodizer 2 are connected to the first group of outputs of control block 7, the second group of outputs of which are connected to information inputs of counters 4 and 5. The bits of the bits of counter 4 are connected to the address inputs of memory block 9 of each channel; 8.1-8.N pulse shaping, oscillator outputs counter 5 - to bit inputs I will give 6 reset circuits and anpecHiiiM inputs to memory block 10 of each channel 8.1-8.N. Tert1) I group-: t; 1 gateways of block 71111: 1 of the field are connected to the control inputs of blocks 9 and 10 of memory that are combined in each channel. First exits

489852

blocks 9 and 1 (the memory is connected respectively to the second and third inputs of the switch 11, the second outputs of the memory blocks 9 and 10 are connected to the second and third inputs of the switch 12, the outputs of the switch 11 and 12 are separately connected to the inputs of the output trigger 13.

10 A period generator 2 (FIG. 2) includes a register 14, the outputs of which are bitwise connected to the inputs of the counter 15, the output of which is connected to the installation input of

15 and through the inverter 16 is connected to the first input of the element AND 17, the second input of which is connected to the counting input of the counter 15, and the inputs of the register 14 are information inputs, the counting input of the counter 15 is a clock input, the output of the element 17 is the first output, and the output of the counter 15 - the second output of the former 2 periods.

25 Circuit 6 reset (fig.Z) consists of a t-input element And 18, the first input of which is connected to the output of the inverter 19, and the output is connected to the first input of the element OR 20,

30 wherein (t is 1) the inputs of the element AND 18 and the input of the inverter 19 are the bit inputs, the second input of the element OR 20 is the installation input, and the output of the element OR 20 is the output of circuit 6

og reset.

The control unit 7 (FIG. 4) contains a memory device 21, the outputs of which are connected to the inputs of the buffer register 22, the decoder 40 23 and the inputs of the arithmetic logic unit (LLU) 24, the output1 of which is connected to the inputs of the buffer register 25, and outputs bu (} 1 merge registers 22, 25 and decoder 23

45 are, respectively, the first, second and third group of outputs of control unit 7.

The multichannel programmable pulse generator works in the following way.

In the initial state, in all the cells of blocks 9 and 10 of the memory of channels 8.1-8.N, O is set, triggers 13 are reset. In accordance with the specified

The gg values of the delay and duration of the output pulses, the information about which is stored in the memory 21 of the control unit 7, the ALU calculates the cell addresses.

3P489YA5.

blocks 9 and 10 of memory channels 8,1-8.N, pulses with a period T

in which must be written 1, the calculation is carried out according to the following formulas:

Some go to the meters of counters 4 and 5 (directly, and through a reset circuit 6),

.r T

 - 2 K

BUT

-Li

- ( 1 TO;

ij) al T,

- 2

TO;

.illli - (2--1)

de a

A „A, A, the addresses of the first bits in memory blocks 9 and 10;

the addresses of the second bits in memory blocks 9 and 10;

the delay of the generated pulse;

the duration of the generated pulse; period of reference frequency generator 1; bit counter A and 5; K Oh, 1, 2, ...

m

30 strobe gating of the coincident signals 1 from the outputs of the first channels of blocks 9 and 10 of the memory. At the output of the switch 11, a pulse is formed (Fig. Zi, moment

Then from the memory unit 21 of the control unit 7, via the buffer register 22, the formation register 14 ((time t)) which sets the period bed 2 rewrites the input trigger 13 to state 1.

Formation about the value of the period T. The addresses A, A7, A, Aa calculated by the ALU 24 through the buffer register 25 of the control block 7 are entered into counters 4 and 5. The decoder 23 selects the channels 8.1-8.N.

In selected channels in blocks 9 and 10

blocks 9 and 10 of memory, and since time t ,. on the outputs of the second Kana50

the catch of blocks 9 and 10 of memory is set to 1 (fig. 5g, g). At time t,

the memory is written 1 to co and 5 form the next addresses A and correspondences with the addresses set to 45 A, arriving at the address inputs at the outputs of counters 4 and 5.

Upon completion of the process of recording information in blocks 2, 9 and 10, counters 4 and 5 are set to the initial (zero) state and the reference frequency generator 1 is started (the Start button is not shown).

At the output of the reference frequency generator 1, clock pulses are generated with the period T following (Fig. 5a), which post fall on the counter 15 of the generator 2 periods and the delay line 3. At the output of the counter 15, the driver 2 periods are generated

 this information is gated and a pulse coming from the output of the delay line 3 to the switch 12 (Fig. 5d), at the output of which a pulse is formed (Fig. 3k), gg arriving at the second input of the trigger 13. The last is reset, forming the back front of the pulse the duration of the image (Fig. 5l, time t).

, impulses with period T

(fig.Zb), which arrive at the installation inputs of counters 4 and 5 (directly to counter 4, and to counter 5 through reset circuit 6),

Clock pulses from the reference frequency generator 1 pass through the logic element AND 17 of the driver 2

10 periods at the counting inputs of counters 4 and 5 (fig.Sv); The clock pulses delayed by line 3 arrive at the first inputs of switches 11 and 12 of the channels 8.1-8.N,

15 gating information from the outputs of memory blocks 9 and 10 (FIG. 5d). At time t, gating of information recorded in memory cells with zero

20 address.

Upon the arrival of clock pulses at the counting inputs of counters 4 and 5 at time t, their state changes, therefore, changing 25 from the address of memory cells of blocks 9 and 10, respectively, to A and A. Information of the first bits of blocks 9 to 10 memories These are shown on fig.5d, e, respectively. At time t

30 strobe gating of the coincident signals 1 from the outputs of the first channels of blocks 9 and 10 of the memory. At the output of the switch 11, a pulse is formed (Fig. Zi, moment

-., (- time t), which sets the output trigger 13 to state 1.

At the output of the trigger 13, the front of the pulse is formed with a predetermined delay 1, (FIG. 5l, time t). Thus, the pulse delay is generated.

After the programmed number of pulses, counters 4

blocks 9 and 10 of memory, and since time t ,. the outputs of the second channel 5 form the next address And And coming to the address inputs

the catch of blocks 9 and 10 of memory is set to 1 (fig. 5g, g). At time t,

 this information is gated and a pulse coming from the output of the delay line 3 to the switch 12 (Fig. 5d), the output of which forms a pulse (Fig. 3k) arriving at the second input of the trigger 13. The last is reset, forming the back front of the pulse with the duration yl (Fig. 5l, time t).

Thus, pulses are formed with a given delay and duration in one of the m channels.

At the moment of time tg, the installation inputs of the counters D and 5 from the output of the counter 15 of the generator 2 periods receive a pulse, which resets the counters to the initial state. Then the next channel is selected,

ten

in which the impulse is a logical way.

anaFormula 15 is formed

Claims (2)

1. Multichannel programmable pulse generator, content reference frequency generator, the output of which connected to the outputs of the first counter, the setup input of which is connected to the second output of the period generator and, through a reset circuit, to the setup input of the second counter, the outputs of which are connected to the discharge inputs of the reset circuit and the second bit integrated pulse address buses of which pulse gates combine) and are connected to the output of the delay line, the input of which is connected to the output of the reference frequency generator. 2. The generator according to claim 1, about tl and - due to the fact that each of the pulse shaping channels contains the first and second memory blocks, is connected to the clock input for 20–20 whose first outputs are connected to the period, the pulse shaping channels, characterized in that, in order to improve the reliability and enhance the functional capabilities, the control unit, the first and the second driver, and the reset circuit, the adversion line, the first group of outputs of the control unit connection 1a with the information cDiiibibOi shaper inputs period of time, the first output of which is connected to the counting inputs of the first and second counters, whose information inputs are bitwise connected to the second group of control unit outputs, the third group of Koiuporo outputs are connected respectively to the control inputs of the impulse 1c control channels , the first address of which are bitwise united and ,, j () responsibly to the first and second inputs of the first switch, the output of which is connected to the first input of the trigger, the second input of which is connected to the output of the second switch, the first second inputs of which are connected to the second outputs of the first and second memory blocks, respectively, the combined control of the first and second blocks the memory is the control input of the pulse shaping channel, the address inputs of the first and second memory blocks are respectively the first and second address channels of the forging channel the pulse, the combined third inputs of the first and the first switches are the gating input, and the trigger output is the output of the pulse shaping channel. 2. The generator according to claim 1, which is based on the fact that each of the pulse shaping channels contains the first and second memory blocks, the first outputs of which are connected with responsibly to the first and second inputs of the first switch, the output of which is connected to the first input of the trigger, the second input of which is connected to the output of the second switch, the first second inputs of which are connected to the second outputs of the first and second memory blocks, respectively, the combined control of the first and second blocks the memory is the control input of the pulse shaping channel, the address inputs of the first and second memory blocks are respectively the first and second address channels of the forging channel mpulsa combined inputs of the first and third switches are cerned strobiru- YU1TSIM input and output trigger - channel pulse generating output. 21 - Fick. 2 Fi.Z periodical} To counter, S To block 9, U G memory Phie. if Well five I n tv , nd Gdl. Comp. B. Kirillov Editor L.Pcholinska Tehred L.Oliynyk Proofreader G.Reshetnik ., ..... "...; g ...- Order 5199/56 Circulation 899 Subscription VIIII11I USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d.A / 5 Production and printing company, Uzhgorod, Projecto st., 4 P. tB five t l7 -t f FIG. five