SU1226485A1 - Device for implementing discrete fourier transform in radio engineering systems - Google Patents

Abstract

The invention relates to the field of computing and radio measuring technology for signal processing. The purpose of the invention is to increase the speed. For its implementation, the device further comprises a group of N shift registers, adders, multipliers, subtractors, NOT elements, blocks, memories, keys, switches, a counter, etc. with appropriate communications. Due to the preliminary permutation and partial inversion of the input sequence of signal samples, the device allows one to reduce the Fourier transform to filtering with a finite impulse response and to obtain two frequency samples simultaneously for each clock cycle. 1 il. (L to 10 O5 4 00 ate

Description

S, so that the real (group 10) and imaginary (group 11) parts of the sequence h, defined by the expression

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11226485

The invention relates to radio engineering and can be used in signal processing.

The purpose of the invention is to increase the speed by pre-permutation and partial inversion of the input sequence of signal samples, which reduces the Fourier transform to filtering with a finite impulse response and simultaneously obtains two frequency samples for each clock cycle.

The drawing shows a functional diagram of the proposed device, performing a 2N -point DFT, where IV 2.

The device contains a generator of 1 clock pulses, a (M + 1) -disable binary counter 2 (), a constant memory unit 3, two blocks A and 5 memories of switch 6 and 7, two keys 8 and 9, two groups of N serially connected maintenance registers and 11 shifts, two elements NOT 12 and 13, four groups of N multipliers (the first and second groups are block 14, the third and fourth are block 15), four N-input adders 16–19, and 20, two adders 21 and 22,

A clock generator 1 controls the operation of counter 2 and shift registers 10 and 11. In blocks 4 and 5, emphasis was recorded for complex samples of 5, n 6, m and g of the input signal: N real, in block 4, and N imaginary - in block 5,

Block 3 is programmed to rearrange and partially invert the samples.

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r - any odd number. Block 3 consistently outputs (M + 1) -diagonal numbers i, M younger

The other bits of which set the addresses of blocks 4 and 5, and the most significant bit controls the operation of switches 6 and 7 (if it is equal to one, the input signal is inverted, otherwise the inversion is not performed.

The addresses of block 3 are set by the M lower bits of counter 2, while its highest bit controls the operation of keys 8 and 9 — when it is zero, the keys are in position 1 and ensure that the shift register groups 10 and 11 are populated;

5 units, the keys 8 and 9 are switched to position 11 and provide a cyclic shift through the elements 12 and 13 of the samples in the registers 10 and 11 of the shift. The multipliers 14 and 15 multiply samples on the numbers c, -, b (,,), where pCoz (liijN); b Sin (ijN); defined by the formula (1).

The device starts to work after the signal is reset by the counter 2. The first N clock cycles of the converted sequence of samples 41. is entered into shift registers 10 and 11, the next N / 2 clock cycles are cyclically shifted through the 12 elements and 13 samples in shift registers 10 and 11 and after Each shift cycle at the outputs of devices 20 n 22 and 2} to 23 forms the validity and imaginary part of the sums t (S) and 2: (5), up to a phase multiplier coinciding with the values of the DFT sequence & h. In just 3N / 2 cyclic shift cycles, N DFT values are output.

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Claims (1)

Invention Formula A device for implementing a discrete Fourier transform in radio systems, containing the first group of N serially connected shift registers, the output of the 1st (1-0, N -) shift register of the first group connected to inputs 1 -X multipliers by the first and second factors groups, first A 50 adder, characterized in that, in order to increase speed, a second group of N shift registers is introduced into it, a third and a fourth group of multipliers per 55 coefficient, second, third, fourth, fifth and sixth adders, first and second subtractors, first and second keys, first and second comm J. tators, first and second memory blocks, first and second elements NOT, a permanent memory block, a counter and a clock generator, the output of which is connected to the counting input of the counter, whose information output is connected to the address input of the permanent memory block, the output of which is connected to the address inputs of the first and second memory blocks, the outputs of which are connected to the information inputs of the first and second switches respectively, the outputs of which are connected to the first information inputs of the first and second keys, respectively, the outputs of which are connected to the information inputs of the first shift registers of the first and second groups respectively, the outputs) -X of which registers are connected to the inputs of the first and second elements, respectively, the outputs of which are connected to the second information inputs of the first and second keys, respectively, of the i-th register the shift of the second group is connected to the inputs of the i-th multipliers by the coefficient of the third and fourth groups, the outputs of the i-th multipliers by the coefficient of the first and third groups are connected to the i-th inputs of the first and second respectively of adders, the first adder outputs are connected to first inputs of the first subtractor and a third adder and the second adder to the first inputs of the fourth and the second and subtractor, the outputs of the i multiplicators by the coefficient of the second and fourth groups are connected to the m inputs of the fifth and sixth adders, and the inputs of the fifth adder the adder and the second subtractor, and the sixth adder - to the second inputs of the first subtractor and the third adder, the output of the clock generator is connected to the clock inputs of the shift registers of the first and second groups, the transfer output of the counter is connected to the control The inputs of the first and second keys, the output of the higher bit of the block of permanent memory is connected to the control inputs of the first and second switches, the input is reset. The meter is the installation input of the device, the inputs of the real and imaginary parts of the operands of which are the information inputs of the first and second memory blocks respectively, the output of the first subtractor and the output of the third adder are the outputs of the real and imaginary parts of the first operand, respectively and the imaginary parts of the second operand of which are respectively the output of the fourth adder and the output of the second subtractor. Editor O. Bugir Compiled by A. Baranov Tehred L.Oleynik Proofreader O. Lugova Order 2136/50. Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035i Moscow, Zh-35, Raushsk nab., 4/5 .- Production and printing company, Uzhgorod, st. Project, 4