SU1290320A1 - Device for distributing jobs to processors - Google Patents

Abstract

A device for distributing tasks to processors is related to computing and can be used in multi-machine and multiprocessor systems for load distribution. The invention can be used in fault-tolerant multiprocessor systems. The purpose of the invention is to simplify the device. The device contains two memory blocks, a counter, a pulse generator, a delay element, a decoder, a NOT element. The essence of the invention is that, for simplicity, a memory block, a decoder and a NOT element are inserted in it. 1 silt

Description

The invention relates to computing and can be used in multi-machine and multiprocessor systems for distributing the load between processors.

The drawing shows the structural diagram of the device.

The device contains a memory block 1, a counter 2, a pulse generator 3 delay element 4, a memory block 5, a decoder 6 and a HE element 7, an information highway 8, a start input 9, a signal output 10, a group of code outputs 11, information outputs 12.

The operation of the device consists in the fact that it performs the dynamic distribution of requests among the processors (computers), taking into account their functionally loaded in the previous cycle, then the output from the memory unit 5 selects the decoder 6 connected to the output of the counter 2 and sets it selectable processor address. The unitary code from the output of the decoder 6 selects the loadable processor. In this case, the signal from the output of the decoder is fed to the input of the processor interrupt. The code of the requested function (interrupt vector) is received by the computer processor from trunk 8 (outputs 12). After loading the selected processor with some delay, element 4 generates a signal confirming the completion of the distribution of the next request. At this signal in code 10, the load source delivers

national opportunities. Functional-20l into the device the following intended capabilities of the processors are displayed in memory block 1. If this processor is able to perform this function, M is entered into the corresponding cell of memory 1, if not, then O.

To ensure uniformity of processor loadings, the advantage of loading is given to processors that were not loaded when distributing previous queries. To implement this distribution principle, a memory block 5 is inserted into the device, in the corresponding cell,. Secondly, O is recorded if it has not been loaded in the previous loading cycles. Otherwise, the cell of memory block 5 is written 1.

Let us consider in more detail the process of distributing requests to trunk 8 and accompanied by a signal at input 9. Signal at input 9 triggers a pulse generator 3 connected to a clock input of counter 2, the contents of which determine the choice of processor that can be checked for loading. . The output of counter 2 is associated with the address inputs of memory blocks 5 and 1. The code of the requested function on line 8 is simultaneously the address of the row of memory 1. If the selected processor is capable of performing the requested function, then 1 is generated at the output of memory 1 memory block sample 5. If the cell of the memory block 5 contains O, i.e. CPU

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distribution request. A signal from the output of the delay element 4 stops the pulse generator 3, at the falling edge of the pulse from which (input to the recording input of the memory block 5), if there is a signal at the output of the memory block 5, is put into the corresponding cell of the memory block 1.

If the selected processor is able to perform the requested function, but there is 1 in the corresponding cell of memory block 5 (this processor was loaded on the previous loop), when selecting memory block 5, no output is generated at its output and the processor is not loaded. A confirmation signal at the output 10 in this case is also not generated, therefore, at the falling edge of the pulse ,. From generator 3, O is written to the corresponding cell of memory block 5, as a result of which, at the next sampling cycle of this processor, it will have a preferential right to load. During the next pulse from generator 3, the contents of counter 2 are increased, and the next processor is checked for the possibility of loading the requested function into it. If this processor is not able to perform the requested function, then at output 55 of memory 1, O is generated and

sampling of memory block 5 does not occur, a signal is not generated at its output, and no processor is loaded. In this case, as before, with

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was not loaded in the previous loop, the signal from the output of the memory unit 5 selects the decoder 6 connected to the output of the counter 2 and sets its address of the selected processor. The unitary code from the output of the decoder 6 selects the loadable processor. In this case, the signal from the output of the decoder is fed to the input of the processor interrupt. The code of the requested function (interrupt vector) is received by the computer processor from trunk 8 (outputs 12). After loading the selected processor with some delay, element 4 generates a signal confirming the completion of the distribution of the next request. At this signal in code 10, the load source delivers

Into the device the following is intended5

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distribution request. A signal from the output of the delay element 4 stops the pulse generator 3, at the falling edge of the pulse from which (input to the recording input of the memory block 5), if there is a signal at the output of the memory block 5, is put into the corresponding cell of the memory block 1.

If the selected processor is able to perform the requested function, but there is 1 in the corresponding cell of memory block 5 (this processor was loaded on the previous loop), when selecting memory block 5, no output is generated at its output and the processor is not loaded. A confirmation signal at the output 10 in this case is also not generated, therefore, at the falling edge of the pulse ,. From generator 3, O is written to the corresponding cell of memory block 5, as a result of which, during the next sampling cycle of this processor, it will have a preferential right to load. During the next pulse from generator 3, the contents of counter 2 increase and the next processor is checked for the possibility of loading the requested function into it. If this processor is not able to perform the requested function, then at output 5 of memory 1, O is generated and

sampling of memory block 5 does not occur, a signal is not generated at its output, and no processor is loaded. In this case, as before, with

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When the next pulse arrives from generator 3, the possibility of loading the next processor in turn is performed, etc. ,

Thus, a cyclical (round-robin) polling of the processors is carried out until the first processor is able to fulfill the request and has the right of first priority, after which the distribution of the next request in turn begins.

Claims (1)

Invention Formula A device for assigning processors to the first memory block, a counter, a pulse generator, a delay element, the device’s information line being connected to the first address input of the first memory block, the counter count input connected to the output of the pulse generator, the trigger input of which is connected to the input start the device, the stop input of the pulse generator is connected to the output of the device 8  . 0 five 0 five and to the output of the delay element, characterized in that, for the sake of simplicity, the device contains a second memory block, a decoder and a NOT element, while the output of the pulse generator is connected to the write control input of the second memory block whose output is connected to the input of the element delays and to the control input of the decoder, the output of the counter is connected to the second address input of the first and to the address input of the second memory blocks and to the input of the digitizer, whose outputs are a group of code outputs of the device, the output of the first memory block connected to the read control input of the second memory block, whose information input is connected to the output of the NOT element connected to the output of the delay element; the read control input of the first memory block is connected to the start input of the device whose information output group is connected to the information highway of the device.