SU1288708A1 - Interface for linking digital computer with magnetic tape stores - Google Patents

Abstract

The invention relates to the field of digital computing, in particular to devices for interface, and can be used to interface the IJBM with external magnetic memory. The aim of the invention is to increase the reliability of the exchange due to the self-test, autonomous copying of magnetic tapes, providing step-by-step operation and the ability to read the control points of the control program of the device. The device contains a communication unit with a digital computer channel, a communication unit with magnetic storage devices tape, synchronization unit, data transfer unit, operation mode control unit. The device has a powerful 16-bit high-speed processor and an original architecture that allows externally to fill in all the internal blocks of the device. All this provides increased intelligence of the device. 2 hp f-ly, 10 ill., 1 tab. CL 00 00

Description

eleven

The invention relates to the field of digital computing, in particular to devices for interface, and can be used to interface a digital computer with an external magnetic memory.

The aim of the invention is to increase the reliability of the exchange by self-testing, autonomous copying of magnetic tapes, providing step-by-step operation and the ability to read the control points of the device’s control program.

FIG. 1 shows a block diagram of the device; in fig. 2 is a diagram of a communication unit with a digital computer channel; in FIG. 3 is a diagram of a data transmission unit j in FIG. 4 a diagram of a synchronization unit; FIG. 5 a diagram of a communication unit with magnetic tape drives; in fig. 6 is a diagram of a mode control block; in fig. 7 is a block diagram of the device firmware algorithm in FIG. 8 - operation of the device in the operating mode; in fig. 9 shows the execution of the Record and Record operations of the end of file j in FIG. 10 - performing the Rewind operation.

The device contains (Fig. 1) a channel of a digital computer 1, input-output input 2 of the device for connecting the input-output address of the data address of the digital computer, input-output 3 of the device for connecting the input-output of the control signals of the digital computer, input-output drives 4 on the magnetic tape, block 5 connection with the digital computer channel, communication unit 6 with magnetic tape storage devices, synchronization unit 7, data transmission unit 8, operation mode control unit (BURR) 9.

The communication unit 5 with the digital computer channel (BSC) contains (Fig. 2) the transceiver 10, the first address decoder 11, the address register 12, the second decoder 13 addresses, the interface unit 14-.

The data transfer unit 8 (TU) contains (FIG. 3) the exchange register 15, the operation unit 16, the condition multiplexer 17, the next address selection unit 18, the address control unit 19, the permanent memory unit 20, the micro-command register 21 forming the microprogram block control, parity check block 22, address multiplexer 23.

Block 7 synchronization (BS) contains (Fig. 4) pulse generator 24

frequency divider 25, first, second switches 26 and 27, programmable timer 28. Communication unit 6 with magnetic tape drives (BSNML) contains (FIG. 5) first decoder 29, first data register 30, driver unit 31, unit 32 matching elements, the second data register 33, the second decoder 34, block 35 of the flip-flops.

The operation mode control unit (BURR) 9 contains (FIG. 6) a mode decoder 36, a mode register 37, an address control decoder 38, a synchronization unit control decoder 39.

The operation of the entire device is controlled by the microprocessor system, which is part of the TU, performed on the microprocessor set 1804. The main parameters of the system are: micro-command 32 bits, length of data word 16 bits, addressable microprogram memory 0-4095 ,. the number of checked characters for conditional transitions is 32 (of which 16 is a data word), the clock frequency is 6 MHz. Any command is executed in one cycle.

The device allows you to perform arithmetic and logical operations with 16-bit numbers, perform various types of shifts, check the result of the operation (zero result

tata, sign, transfer), check

Any data bit, conditional and unconditional jumps, subroutine calls, input to the processor registers constants stored in the field of microinstructions, output and input to. data processor from external registers. In two cycles, the microcommand is sampled at the address stored in one of the process registers (indirect addressing).

The microprocessor system includes an operating unit consisting of four microprocessor sections 1804 BC1, a block for selecting the next address (UCA) 1804 university, three sections of the microcommand address control unit (AMA) 1804 VU2, a block of fixed memory (PIC) with a bit size The PT5 ROM 556, the micro-command register (RNA), consisting of eight 1804 IR1 registers, and the 32-bit multiplexer of conditions with an inverter and a trigger condition. Data exchange between internal system nodes

we and other units of the device are transmitted via a 16-bit data bus. It also transmits the transition address and constants, which, if necessary, arrive at the bus from the RMK.

The order of operation of the device is as follows.

When power is turned on, the channel of the digital computer 1 receives a signal Reset to the cleaning inputs of the device registers and to the input of setting the zero address of block 19. The last sends a zero address to the input of block 20. From the memory, the command goes to the input of register 21. At the time of the signal Reset, the output clock pulses from the generator, but through the switch 26 and timer 28 in the BSU, a single pulse is generated, arriving at the clock inputs of the block 19 and the register 21. On its leading edge, the command is entered into the register 21, the micro-command is fed to the bus the teams, and in the microinstruction unit 19 recorded address counter I. From the output of microinstruction register 21 is supplied to the command bus and, on the tire - by coma inputs different nodes, devices according to the active end of the reset signal is permitted to output clock pulses from the generator. The sequence of command execution is as follows. During one clock period, which is 6 MHz, the command is executed.

On the clock edge, the result is fixed, the next microinstruction is entered in register 21, and block 19 generates the address of the new command, i.e. during the time the command is executed, the next command is selected from the memory.

The system of commands and assignment of various fields are given in the table. In total there are six types of commands: processor, which ensures the execution of arithmetic operations in the processor and the shift of the result; input - input data into the processor from external registers; output - output from the processor to external registers, input of constants - input to the processor of a 16-bit constant from the field of microinstructions, address of the transition - entering into block 19 of the 12-bit address of the next reset command, acting through the BS similarly to the signal Reset from the channel.

When executing all the commands, except Entering constants and Reset, any condition, the type of condition (o or 1) is checked and the source of the next address is selected depending on the execution in the previous command.

Lyuba team is divided into several fields. Units 14, 15, and 21 define the command code, which in the BS are involved in the generation of control pulses. Bit 0-12 enters the inputs of all microprocessor sections. They encode the type of operation ALU (3-5), the source of operands (0-2), the receiver of the result (6-8), the address of one of the processor registers (9-12). Bit 13 is the transfer signal to the lower microprocessor section for ALU operations. From 16 to 20 bits, depending on the type of command, they set either the address of the internal register of the processor, or the address of the register of the exchange, or, through the BS, generate control pulses to the device nodes. In the processor instruction, bit 20, together with 21, determines the type of shift of the operation result. Bit 22-27, entering the conditions multiplexer input, determine the address of the condition being checked and its value (0 or 1). Bit 28-31 through block 18 set the source address of the next microcommand after the current one. It can be a micro-command counter of block 19 (in this case the address of the next micro-command is one more than the previous one), the stack, the address register, the data bus. In the case of the command, the Jump Address in bits 0-11 contains the address of the micro-command that comes from register 21 to the data bus, and from it if the conditions or are fulfilled. in unconditional transitions, to block 19. In this case, the processor does not execute any command, but it checks the external conditions (for example, the timer operation, the end of the exchange with the NML, etc.).

The command for entering constants in bits 16–31 contains a constant, which from register 21 goes to the data bus and then to the processor. In this command, the conditions are not checked and the source of the address of the next command can only be the counter of microcommands of block 19. A communication unit with a digital computer channel (BSK) is designed to exchange data between the device and the digital computer in three modes of operation: in software, direct access mode and interrupts. The data and the address (bits - 16) between the digital computer channel and the internal backbone are made by the transceiver 10, which consists of four channel transceiver chips. Each channel line is bidirectional. The control of receiving and issuing information is performed from the internal nodes of the device after processing the control signals.

Received information arrives on the internal bus. In particular, the address goes to the address decoder 11, performed on a single PLM chip. The higher part of the 16-bit address is decrypted, with the exception of the lower four bits. The older part defines the address of the DVR to the device, the younger part determines the specific block of the device and is fixed at the time of addressing in the address register.

In order to implement the modes of data exchange between the device and the digital computer, there is a unit 14 for channel exchange performed on the LSI: Interface circuit. Block 14, in program mode, receives control signals and transmits them to the internal nodes of the device. Thus, the synchronization signal goes to the address register and records in it the smaller bits of the address.

According to requests from the internal nodes of the device, the exchange device generates the appropriate exchange protocols with digital computers in direct access and interrupt modes. In addition, for the Read or Write operations, the device generates control signals to the device nodes in all the listed modes, B performed on the BIS PLM decoder 13, the logical processing of the signals from the exchange device and the address register is performed, and the following signals are generated on the TU exchange registers: register address, gate enable audio recording into the low byte of the register and older, the read signal. In addition, the PLA controls the bus driver and generates a CIP signal to the exchange device during program access.

The main device communicating between the eyelids and TUs is the exchange register 15, which is itself eight registers with the possibility of writing and reading in two directions. One direction is the input and output of the data bus from the digital computer. The other direction is bus entry and exit.

dt and JO

15

20

25

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BDC data, i.e. internal device data. When writing-reading from the DVR channel, the exchange registers are sent from the BSK. When writing-reading from the device, the address comes from the TU through the multiplexer. The purpose of the latter is to provide direct access to the internal data bus from the digital computer channel. When the device is translated in diagnostics mode, the address multiplexer 23 does not address the address from the bus of the TU commands, but the constant address (address register 7) through which data is transmitted in directions from the BSK data bus to the data center bus and vice versa . The read-write modes of the exchange registers are set from BSK.

BSNML is designed to transmit control signals and data from the internal circuits of the device to the NML, as well as receive and transmit signals from the NML.

On the internal data bus side of the device, there are a number of registers in the block. The registers available for recording information from the BDT are as follows: the NML control register, the data register for the NML.

The registers are readable in the BPD-: NML status register, NML data register.

The synchronization of the recording of the first and the reading of the second is carried out by special signals from the BS. The registers are made on medium-integration microcircuits.

The information intended for transmission to the NML from the registers is received by a pair of amplifier drivers, which transmit data and control signals via cables to the NML. The information supplied to both NMLs is the same. The NML is selected radially.

The data and control signals from the NML implant a set of matching elements, which are resistive dividers and receivers of logical signals. After forming these signals go to the inputs of the registers accessible for reading for the device. Writing to these registers takes place via the sync signals from the NML.

Information about the exchange procedures between the device and the NMP goes to the node of signs of the end of the exchange.

thirty

35

40

45

50

55

It is intended to notify information about the information from the device for the NML and about information in the opposite direction.

A node consists of two triggers, stars in the preparation of information and reset when synchronization occurs. Thus, the outputs of these triggers notify the device of the transmission or reception of information.

BS is designed to generate the main clocking and control signals for the device nodes.

The main clock frequency is generated by a 12 MHz crystal oscillator; Pulses are fed to two frequency divider chips, the output of which is frequency 6; 2; one; 0.5 O, 125 MHz. They arrive at the site of production of clock pulses. This node controls the transmission of clock pulses from the BURR. The timer, using clock frequencies, generates the time delays and pulse sequences necessary to control the NML. Timers are controlled from the data bus by writing control words from the BPD. The timer is made on one BIS 580 series. In the control pulse generation unit, individual bits of micro-instructions are decrypted to form radial control lines for the various components of the device. In addition, decoding the micro-instruction bus bits allows you to determine the type of micro-command that is needed for control. When generating control pulses, time ratios are taken into account, which are determined by the nodes of the block: a generator, a frequency divider and a node for generating clocking pulses. The control pulse generation unit allows, when a command from the BURR is received, to switch to different modes of operation. In this case, the clocking of the exchange registers, the address control node of the next microcommand, and the jpeg of microcommands in the BPD are changed.

To select the mode of operation of the device is BURR. Depending on the command sent to it from, it can stop the device at an arbitrary time, select a micro-command from the memory at any address, read its contents in the digital computer and issue a clock to fix the results of its execution.

-

. JO

f5

20

2887088

nothing Thus, by means of BURR, the digital computer emulates the operation of the device, but at the same time, after executing each command, it can verify the result. In addition, through the BURR, it is possible to load any address into block 19, which makes it possible to select, depending on the operating mode of the microprogram, realizing functions other than the regular ones. These include performing operations such as copying information from one NML to another without. the fate of the program in the digital computer, verification of checksums on magnetic tapes, the launch of programs / testing internal controller nodes, with the issuance of a result; tatov in digital computers through the register 15 exchange. In the event of a failure, selecting certain sequences of commands and controlling their execution through BURR, it is possible to localize the fault in many cases with precision to the chip or communication.

The sequence of work of the BURR is as follows. From the digital computer at the mode register address, the control word of the following format is entered: bits 0-11 are the microcommand address, 12 is the command to form one clock pulse during reversal, 13 is to stop the internal production of clock pulses, 14 is the choice of the lower or higher 16 bits The microcommand reads for reading in a digital computer, as well as with a value of 0, bit 12, the resolution of entering the address of the MC in block 19. Discharges 13-14 are stored in the mode register when a control pulse appears from the decoder of the mode register. The rank 12 in the case of its single value at the time of circulation forms one cycle. Bit 0-11 arrive at the input of the register 15 exchange. If value

25

thirty

40

bit 14 is O, and bit 12 is 1, then address multiplexer 3 connects the exchange register 8 to the data bus that is accessed from the digital computer, i.e. in this case, the information from the digital computer directly goes to the internal data bus. At the described values of bits 12 and 14, the block 19 proceeds to receive the address from the data bus and transmit it to the input of the block 20. The selected microcommand enters the input of the register 21. Through for some time, special logic generates one impulse, according to which the microinstruction

is written to register 21, and the microcomputer counter of block 19 records the address plus 1.

At the end of the cycle of accessing the BURR from the DVR device (bw, the firmware can start executing the firmware from the specified address, if bit 13 is equal to O or is in the state of waiting for the next call to it. With values of 1, bits 12 and 14 per mouth

In real time, no switching occurs, but through the switch 26 a single clocking pulse is generated. This allows you to go to the next microcommand from block 20. When reading in the digital computer at 172536, the BURR suspends the switch 26, outputs a part of the microcommand indicated by bit 13 to the data bus and connects the register 16 to the data bus with the multiplexer 23. the contents of the tire

This is connected to the input-output device for connecting data input-output and control signals to accumulators on a magnetic tape, characterized in that, in order to increase the reliability of the exchange, a mode control module is inserted into it and the data input of the mode control module connected to the output of this communication unit with a digital computer channel, the address output of which is connected to the mode selection input of the operation mode control unit, the address selection control output of which is connected to the address input input of the data transmission unit, by strobe The operating unit control unit is connected to the enable input of the synchronization unit, the data output of the data transfer unit is connected to the control input of the synchronization unit, the command output of the data transfer unit is connected to the inputs of the sync data unit through the exchange register 15 to the digital computer. The control of the multiplexing and the command input of the block by the address 23, as well as by the communication unit 19 with the digital computer channel, is accomplished by the special logic implemented in the decoder 38.

a communication unit with a digital computer channel, a synchronization unit and a communication unit with magnetic tape accumulators are connected to a group of inputs of the state of the data transmission unit; the operating mode control unit contains a mode decoder, a mode register, an address control decoder and a sync control decoder, moreover the control unit of the operating mode, the data input of the block is connected to the first input of the decoder of the mode register, to the information input of the register of the formula of the invention

Claims (3)

1. A device for interfacing a digital computer with accumulators on a magnetic tape, comprising a communication unit with a digital computer channel, a data transmission unit, a synchronization unit and a communication unit with magnetic tape accumulators, the input data of the communication unit address A digital channel is connected to the input-output of the device to connect the input-output of the ad-Q mode and to the first input of the decoder data center of the digital computer, the input-output of the control signals of the channel of the communication unit with the channel of the digital computer are connected to the input-output of the device for connecting the input-output by the synchronization unit, the second input of the KOToi orp and the input of the address control decoder are connected to the output of the mode register, gating the course of the control signals of the digital computer whose input-5 input is connected to the output of the data output and the output of the strobirona of the mode register decoder, the second data of the communication unit with the digital-computer channel, whose input is connected to the input and respectively, to the data synchronization input block mode blob, the address control decoder output is connected to the data transfer terminal, from the first to the third Q control, the block address, the outputs of the synchronization block of the control decoder block are synchronized with the sync inputs communication units with a digital computer channel, communication with connection is connected to the gate output of the unit. accumulators on a magnetic tape and data transmission, data output-output is blocked by the fact that the data transfer transfer unit is connected to the data input-output of the communication unit with magnetic accumulators, the input and output data and control signals of which This is connected to the input-output device for connecting data input-output and control signals to accumulators on a magnetic tape, characterized in that, in order to increase the reliability of the exchange, a mode control module is inserted into it and the data input of the mode control module connected to the output of this communication unit with a digital computer channel, the address output of which is connected to the mode selection input of the operation mode control unit, the address selection control output of which is connected to the address input input of the data transmission unit, by strobe The operating unit control unit is connected to the enable input of the synchronization unit, the data output of the data transfer unit is connected to the control input of the synchronization unit, the command output of the data transfer unit is connected to the inputs of the synchronization unit mode and the command input of the communication unit to the DVR channel, state outputs station and command input of the communication unit with a digital computer channel, status outputs a communication unit with a digital computer channel, a synchronization unit and a communication unit with magnetic tape accumulators are connected to a group of inputs of the state of the data transmission unit; the operating mode control unit contains a mode decoder, a mode register, an address control decoder and a sync control decoder, moreover the control unit of the operating mode of the data input of the block is connected to the first input of the decoder of the mode register, to the information input of the mode register and to the first input of the decoder control unit, the second KOToi orp input and the address control decoder input are connected to the output of the mode register, strobe the OSH input of which is connected to the output of the mode register decoder, the second input of which is connected to the input of the block mode borax, the address control decoder output is connected to the control output, the block address, the output of the control decoder of the syncro block connection is connected to the gate output of the unit. 2, the device according to claim 1, the data transfer layer comprises an address multiplexer, an exchange register, an operation unit, a firmware control unit and a parity check unit. the first data input of the block is connected to the first information input of the exchange register, the information input / output of which is connected to the data input / output of the operation unit, to the logic input of the microprogram control unit, to the microcommand output of the microprogram control unit, to the data input of the parity block and with the data input-output of the block, the data synchronization input of the block is connected to the gate input of the exchange register, the synchronization input and the second information input of which are connected according to At the unit's synchronous side and with the output of the address multiplexer, the command output of the block is connected to the output of microcommands and the address input of the microprogram control block, to the command input of the operation block and to the first information input of the multiplexer address, the second information input that controls the input of the address multiplexer is connected to the input of the selection of the address, the block, the synchronous input of the block is connected to the synchronization inputs of the parity check block, the microprogram control block and the operation unit, whose output output is connected to the input of the microprogram control command unit, the second and third tii inputs logical conditions which Command system Id-IB KoS team ALU processor BO-83 Processor Register Number SHO-SH1 Type of result result 20-Z4 Mres Prober Emago Dslobits AO-A3 Non-registro processor TST value npoSepffCMOso yc / toSuir (f) XQ-X3 Team with German and has the following address CO Input transfer ALU processor SO-S3 Current Register Address K & Type of external registers KQ-K15 Constant WO-WH Address transition They are connected respectively to the group of state inputs of the block and to the output of the parity check block. 3. The device according to claim 1, characterized in that the communication unit with the channel of the digital computer contains a transceiver, a first address decoder, a re0 five / source address, interface unit and second address decoder, the input / output address data and control signals of the block are connected. Respectively to the first input output of the sensor and the input interface of the transceiver, the second input output of the transceiver is connected to input input the data output of the block and the first information input of the address register, the information output of the transceiver is connected to the input of the first address decoder, the output of which is connected to the second information input of the address register, strobe input The first and the first input of the second address decoder are connected to the sync output of the interface unit, the output of the address register is connected to the second input of the second address decoder and to the address output of the block, the sync input of the block is connected to the sync input of the interface block, the command input of which is connected to the command input of the block, the output of the second decoder dres is connected to the output of the strobiran Tire Bus tire FIG. (rig 5 Computer data bus Navapd Management from 6SK 36 39 NABS 6 Ndzalo jl I Initialization of registers and knots ± Team team from RO Write b register NO / f Reading state of NML No team Ustamobi / pb sign mistakes Clear the readiness flag. Determine the address of the firmware that performs the operation. II Perform an operation || one "MBHH HMBi HwdMMMMIIMWiMMNiMMMMBHHMMM Install a sign of readiness device Breaking 1Served Record of the 6 C C K for the processing of the breakout bector Delay on magnetic tape retention Not 7 Start ±. Writing Into the NML Control Register, the Ndbizhenae command and the stock status Delay for overclocking IL J Record command b bydachi timer sync pulse on NML 238b data register on NML Reading data through a direct access channelJ Calculation of check, sums, write 6 data register to NML Record of the longitudinal control code / Iff of the data register on the NML S I Test Read from NML QMM) FIG. eight Warped) Zisapispb b the NML control register command "Rewind Remove sign of readiness The state register of the NML Cieiiotndiz RO F Rewind No (.Koney} Fia.9 (Yachalo 3 jL Notes on the register control code Record team 6 dl timer dbidaiju sync on NML. chick data from one of the register s exchange Record danb1) (6 data register on NML Reading the NML status register, status record 6 exchange register Editor L.Gratillo Order 7810/48 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 (Yachalo 3 jL Fig 10 Compiled by I.Khazov Tehred L.Oleynik Proofreader M.Sharoshi