SU1264170A1 - Differentiating device - Google Patents

Abstract

The invention relates to automation and numerical technology. The purpose of the invention is to improve the accuracy of differentiation. The device contains a tracking analog-to-digital converter, two shift registers, two switches, a reversible counter, and a clock generator. During operation, a sequence of ternary-encoded increments of the input analog signal from the outputs of the following analog-digital converter is fed to the information inputs of the switches and shift registers. The pulses from the outputs of the shift registers are also fed to the information inputs of the switches, the outputs of which are connected to the summing and subtracting inputs of a reversible counter. The content of the reversible counter, starting with the N 1 th cycle of the generator (where ft is the register width), is equal to the algebraic sum of the input signal increments over the last N cycles. Rea (Listing the following calculation mode C derivative when ternary coding the increments of the input signal allows to increase the accuracy of calculations by eliminating fluctuations of the derivative code in the counter, which occurs during the binary coding of alternating increments. 1 Il.

Description

The invention relates to automation and computer technology and can be used, in particular, in the construction of digital measuring and control devices operating in real time.

The purpose of the invention is improving accuracy.

The drawing shows a block diagram of a differentiating device.

The device contains a tracking analog-to-digital Converter 1, the first and second shift registers 2 and 3, the first and second switches 4 and 5, a reversible counter 6 and a clock generator 7. Each of the switches is made on an OR element and two AND elements connected by outputs to the inputs of an OR element, with the first inputs of the AND elements being the information inputs of the switch, and the second inputs being the control inputs. The generator 7 generates two sequences of pulses. The appearance of pulses at the first output of the generator corresponds to odd clock cycles of its operation, and at the second output of the generator to even cycles. The device has an input 8 and a bus 9 of the initial installation,

The device operates as follows: _l.

Differentiating analog signal. Is fed to input 8 of the device. An impulse is applied to the initial installation bus 9, resetting the tracking analog-to-digital converter 1, shift registers 2 and 3, and the reverse counter 6. The input analog signal from 'input 8 of the device is converted by the tracking analog-to-digital converter 1 in a sequence of terminal encoded increments, which are received: positive - to the information input of the shift register 2 and to the first information input of the switch 4; negative - to the information input of the shift register • 3 and to the second information input of the switch 5.

During the first N clock cycles of a clocking series of pulses (N is the width of shift registers 2 and 3.) at the outputs of shift registers 2 and 3 and, respectively, the first information input of switch 5 and the second information input of switch 4 are zero values. In this case, on each clock cycle of a clocking series of pulses, positive or negative increments pass respectively to the summing and subtracting inputs of the reverse counter 6. Starting from N + 1 clock cycles of a clocking series of pulses, positive or negative increments delayed by 14 'clock cycles appear on the outputs of the shift registers 2 and 3, which, at each step of a delayed series of clock pulses, are respectively supplied to the subtracting and summing inputs of the reverse counter 6.

Thus, at any time after N + 1 cycle of the device, the contents of the reverse counter 6 is equal to the algebraic sum of the increments of the input signal for the last N cycles of the device. This achieves a follow-up mode of operation of the device. The contents of the reverse counter 6 at each operation cycle is determined as the digital value of the first derivative of the input analog signal, and the device’s speed is determined by the frequency of the generator 7 clock pulses, which should not be higher than half the maximum allowable frequency of operation of the reverse counter 6.

Thus, the proposed device implements a tracking mode for calculating the derivative with ternary coding of input signal increments, which allows to increase the accuracy of calculations by eliminating fluctuations in the derivative code in counter 6 that occur during binary coding of alternating increments of the input signal and saving the result counter as a significant minor digit.

Claims (1)

The invention relates to automation and computing and can be used, in particular, in the construction of digital measuring and control devices operating in real time. The purpose of the invention is to increase accuracy. The drawing shows a block diagram differentiate its device. The device contains an analog-to-digital converter 1, a first and second register: 2 and 3 shifts, first and second switches 4 and 5, a reversible counter 6, and a generator of 7 clock pulses. Each of the switches on the OR element and two AND elements connected by the outputs. To the inputs of the element is OR, the first inputs of the AND elements are the information inputs of the switch, and the second inputs are control inputs. The generator 7 generates two sequences of pulses. The appearance of pulses at the first output of the generator corresponds to odd cycles of its operation, and at the second output of the generator to even cycles. The device has an input 8 and a bus 9 of the initial installation. The device works as follows. Differentiating analog signal. - is fed to the input 8 of the device. A pulse is applied to the initial setup bus 9, which resets the following analog-digital converter 1, the shift registers 2 and 3, and the reversing counter 6. The input analog signal from input 8 of the device trans. It is developed by the following analog-digital converter I in the sequence of turn-encoded increments, which are received: positive - to the information input of the 2 shift register and to the first information input of the switch L; negative - to the information input of the 3 shift register and to the second information input of the switch 5. During the first N cycles of the clock pulse train (N is the width of the 2 and 3 shift registers) at the outputs of the 2 and 3 shift registers and the first information input of the switch 5 and the second information input of the switch 4 are zero values. At each clock cycle, a positive or negative increments are passed respectively to the summing and subtracting inputs of the reversing counter 6. Starting from N + 1 clock cycles of the clock series of pulses, positive or delayed by K clock cycles appear at the outputs of the shift registers 2 and 3. negative; increments that are on each clock; The delayed clock series is fed to the subtracting and summing inputs of the reversing counter 6, respectively. Thus, at any time after the N + 1 device ticks, the contents of the reversing counter 6 are equal to the algebraic sum of the input signal increments for the last N cycles of the device. This achieves the next operation mode of the device. The content of the reversible counter 6 at each clock cycle is determined as the digital value of the first derivative of the input analog signal, and the device’s speed is determined by the frequency of the clock generator 7, which must be not more than half the maximum permissible frequency of the reversing counter 6. Thus, the proposed device realizes the following mode of calculating the derivative when ternary coding the increments of the input signal, which allows to increase the accuracy of calculations by eliminating and fluctuations of the derivative code in counter 6, arising from the binary encoding of the alternating increments of the input signal and preserving the result counter as the significant least significant bit of the counter. Claims of the invention Differentiating device containing the following analog-digital converter connected by information input to the device input, clock input - to the first output of the clock generator, first control inputs of the first and second switches and clocked; their input of the first shift register, the setting input - with the thickness of the initial installation of the device and the installation inputs of the first shift register and reversible counter, and the output of positive increments - with the first information input One of the first switch and the information input of the first shift register connected by the output to the first information input of the second switch connected to the second control input with the second output of the clock generator and the second control input of the first switch, and output to the subtracting input of the reversible counter, connected a summing input to the output of the first switch, and an output to the output of the device, characterized in that, in order to improve accuracy, a second shift register is inserted into it, connected th data input to the output of negative increments servo analog-to-digital converter and a second data input of the second switch, a timing input - to the first output of the clock generator, bus ustanovochnm input initial setting unit j as output - to the second data input -First switch. -.