SU1264160A1 - Device for calculating sets of logic functions - Google Patents

Abstract

The invention relates to the field of computer technology and is intended to implement logical function systems. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that the device contains memory matrixes, two decoders, m groups of OR elements and m switches, two groups of information inputs, m outputs. When applying variables x, x to the first group of inputs and variables x.,) Xf, to the second group of inputs at the outputs of the device, logical functions f ... fm of n variables are implemented. 2 Il.

Description

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4i The invention relates to computing and is intended for the implementation of logic functions systems describing the operation of digital converters. The purpose of the invention is to increase the speed of the device for calculating logical function systems. Figure 1 shows the structural diagram of the proposed device; 2 shows a functional diagram of the device for the considered example. The device contains the first T and second 2 groups of information inputs, ha (by the number of logic functions implemented by the device) outputs 3, -3t, the first 4 and second 5 decoders, g of memory matrix b 6m, m groups of elements OR 7-7t and m switchboards 8y. The first 1 and second 2 groups of information inputs of the device are connected to the inputs of the first 4 and second 5 decoders, respectively. The outputs of the first decoder 4 are connected to the address buses of the memory matrices 6i bgp, the outputs of which are connected to the information inputs of the switchboards W, respectively. The outputs of the second decoder 5 are connected to the inputs of the elements OR 7-7, the outputs of KOTORsrx are connected to the control inputs of the switches 8 — respectively, the outputs of the switches 8 —Bin are the outputs of the device Zsh The device operates as follows. The system of logical functions and variables f (x), ni -decomposes along the cervical in terms of k (kn) variables x ,, xj. on the function of the variable variables 4iJ (XcTTT n) Thus, each function f; corresponds to 2 functions U, Ii functions are located in the memory so that each of them occupies one word (row) in the i-th memory matrix. Obviously, with the same name, the S (,) functions of the vfLi () (J 1,2) will correspond to v Boolean functions .S (V) q) each of which occupies the Sth column in the ith memory matrix. Therefore, the variables Xc, x define the function 4is in the ith matrix, and the variables x, x (is the value of the selected function, which coincides with the value 02 of the function f (x, x,) on the given set of variables x, x. If the variables x, x to apply to the first decoder, the output of which is connected to the address buses of the memory matrices, variables Xj ,, n to the second decoder, the output of which is connected to the control inputs of the switches, the information inputs of which are connected respectively to the outputs of the memory matrix, switch outputs are implemented f - (x, x), However, in order to reduce hardware costs, all pairwise identical functions H. V, f (S 1, I 1, ..., S / 1), which correspond to signals on and outputs of the second decoder, are placed in memory so that they occupy one column, then the corresponding control input of the switch is connected to the output of the OR element, whose inputs are connected to the outputs of the second decoder. A more detailed operation of the proposed device is considered on the example of implementing a system of three Boolean functions of five variables (Table 1 ), but functional scheme The device for this example is shown in FIG. 2; We decompose f (xTTxg) in variables (Table 2). Obviously .H „V, j S, jf (x, x„), y., f2 (x, hg); f ,, (x ,, hg); F6 f 3 (x, X j) Therefore, the functions Y ,,, 4 ,, Y are placed in one column of the first memory matrix 6j, the output of which is connected to the information input of the switch 8, the corresponding control input of which is connected to the output of the element OR groups 7, the inputs of which are connected to the first, second and eighth outputs of the second decoder 5. The functions H and Hi, and 7 also occupy one column each in the memory matrix 6j, the corresponding control inputs of the switch 8 are also connected to the outputs of the elements OR groups 7, since the function has no identities constant function, then sootvetstvuyu312641

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Thus, when applying, inputs 1 of the first decrypted x, x are variable.

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Claims (1)

Claim 1 A device for calculating systems of logic functions containing first and second decoders, m groups of elements OR (m is the number of logic functions implementing a device), m switches and m memory blocks, the outputs of each i-ro (, m) memory block are connected to informational the inputs of the i-ro switch, the output of which is the i-th output of the device, the first group of information inputs of which are connected 6l Si 3i the inputs of the first decoder, the second group of information inputs of the device are connected to the inputs of the second decoder, characterized in that, in order to improve speed, the outputs of the first decoder are connected to the address inputs of m memory blocks, the outputs of the second decoder are connected to the inputs of the OR elements of the first to The knc outputs of the elements OR of the i groups are connected to the control inputs of the Lcr switch. 6t 8t Ut t at (Rig.1